Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/1.2/patches/2231895/?format=api
{ "id": 2231895, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2231895/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/patch/7-v1-b7dc0a0d4aa0+3723d-smmu_no_cmdq_ent_jgg@nvidia.com/", "project": { "id": 21, "url": "http://patchwork.ozlabs.org/api/1.2/projects/21/?format=api", "name": "Linux Tegra Development", "link_name": "linux-tegra", "list_id": "linux-tegra.vger.kernel.org", "list_email": "linux-tegra@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<7-v1-b7dc0a0d4aa0+3723d-smmu_no_cmdq_ent_jgg@nvidia.com>", "list_archive_url": null, "date": "2026-05-01T14:29:16", "name": "[7/9] iommu/arm-smmu-v3: Directly encode CMDQ_OP_ATC_INV", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "343c494716fb059ba61ffe764adad1ae7f778c55", "submitter": { "id": 79424, "url": "http://patchwork.ozlabs.org/api/1.2/people/79424/?format=api", "name": "Jason Gunthorpe", "email": "jgg@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-tegra/patch/7-v1-b7dc0a0d4aa0+3723d-smmu_no_cmdq_ent_jgg@nvidia.com/mbox/", "series": [ { "id": 502465, "url": "http://patchwork.ozlabs.org/api/1.2/series/502465/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/list/?series=502465", "date": "2026-05-01T14:29:09", "name": "Remove SMMUv3 struct arm_smmu_cmdq_ent", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/502465/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2231895/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2231895/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-tegra+bounces-14141-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-tegra@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=khV++btL;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c04:e001:36c::12fc:5321; helo=tor.lore.kernel.org;\n envelope-from=linux-tegra+bounces-14141-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)", "smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com\n header.b=\"khV++btL\"", "smtp.subspace.kernel.org;\n arc=fail smtp.client-ip=52.101.52.21", "smtp.subspace.kernel.org;\n dmarc=pass (p=reject dis=none) header.from=nvidia.com", "smtp.subspace.kernel.org;\n spf=fail smtp.mailfrom=nvidia.com", "dkim=none (message not signed)\n header.d=none;dmarc=none action=none header.from=nvidia.com;" ], "Received": [ "from tor.lore.kernel.org (tor.lore.kernel.org\n [IPv6:2600:3c04:e001:36c::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g6YN54B4xz1yHZ\n\tfor <incoming@patchwork.ozlabs.org>; Sat, 02 May 2026 00:29:57 +1000 (AEST)", "from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby tor.lore.kernel.org (Postfix) with ESMTP id DAF163024460\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 1 May 2026 14:29:41 +0000 (UTC)", "from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id 9F96B3CBE76;\n\tFri, 1 May 2026 14:29:41 +0000 (UTC)", "from BL2PR02CU003.outbound.protection.outlook.com\n (mail-eastusazon11011021.outbound.protection.outlook.com [52.101.52.21])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby smtp.subspace.kernel.org (Postfix) with ESMTPS id E082D3CB2D5\n\tfor <linux-tegra@vger.kernel.org>; Fri, 1 May 2026 14:29:39 +0000 (UTC)", "from LV8PR12MB9620.namprd12.prod.outlook.com (2603:10b6:408:2a1::19)\n by SA1PR12MB8096.namprd12.prod.outlook.com (2603:10b6:806:326::22) with\n Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9870.23; Fri, 1 May\n 2026 14:29:26 +0000", "from LV8PR12MB9620.namprd12.prod.outlook.com\n ([fe80::299d:f5e0:3550:1528]) by LV8PR12MB9620.namprd12.prod.outlook.com\n ([fe80::299d:f5e0:3550:1528%5]) with mapi id 15.20.9870.022; Fri, 1 May 2026\n 14:29:26 +0000" ], "ARC-Seal": [ "i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1777645781; cv=fail;\n b=nk0m5lDP4nvNeb35Rz0yYSFybSmDUWeb49dJVmMxosAD5ztXnKXJfvSKTmEMxMN9Pf/+xK3Y9p3tGCYr0FQLZ7UdEjNFYo6huj7is46u2JWzusTnCWg/cQxreSwpqEYpBSCMy0BFui8cUzKS0mTET7ayq25zSo4bWupFSj6yGx0=", "i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none;\n b=FLD0LYIfmHC6OkV16ZHFyZ++PEjqjg82fN+5teN30K1h23eDvEzk78qorXtxZ6F2U8wNGLsFrdlYD+CxNcfHQkrOg8CFigAfgBfhrTOz6KkRqGa4rHvOQO3bL6HyyDs/zaGr7Gty3OjFD8zz79F+L9rk1T1qPMTrd1O2PHwonMYSEeAyVY4sbi/zFwLTPKcMjspbLrJbXtrLE3tukvzy1tJWx6BKO31UUpM2DUV6Kh2kCK6C0mq+H0J2LZ6GZEpIny2DohTaTWFZhPQB9m5Uzxy1n1bI5Tk92RENKlkheai1Okwc0zVFucKXzErv+1FvYh2DQNsz5uo0KdjsqzvRSg==" ], "ARC-Message-Signature": [ "i=2; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1777645781; c=relaxed/simple;\n\tbh=0DiZO4rPrp8Dq+oG//ohq4PLiX7J+sApLhLL8xPePjM=;\n\th=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References:\n\t Content-Type:MIME-Version;\n b=WpYOswXe5QGX7q9qkmTam4FAofpEUEke2fswqujgwUg0MGbkNTGV2n5ynwbQ9PRtkpMM7y2M7DzevYrOFSPBEpFfe11C0H22ds9RdFHtaR7Pl2UsGSLfLpZWJhz8JURIOAl88U5yqWCgeAjx9hi4aluQwNPtPS2APdi2OA17dc8=", "i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;\n s=arcselector10001;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1;\n bh=uNjJ5QHnutlgt5Uk9IPWdQzl2DOPiAyg06fxlD64Ep0=;\n b=Z8eWy5avSKljw9oLJOGxEeg/UGv/1RBO6k90QrlPksyEF99mMTMXdOSVMScRA+v83mtFV1TmJYNshfODxpHdwVlGNluS0YnvjkAqywm1BoD2k30WhllcQn3OKDTIcL4Y86BysHCwdrJtOzejqdoPLRzn3Yib3vakm2fEw/G81LQAFfnRfZb3/YazstBT4sxEpDogOcpY5alMBgygECv18qRqoT05s46977pW1NULtvQ+IXTXdi0aIc+LZUH3me4aLg/BOISSw+00mz8npLKHbhFxzYws2G7q19hvywGHbVPwybt+pFGA6B/WQTGW3wpCCcfBz/wQPcJbNs0+np1P9A==" ], "ARC-Authentication-Results": [ "i=2; smtp.subspace.kernel.org;\n dmarc=pass (p=reject dis=none) header.from=nvidia.com;\n spf=fail smtp.mailfrom=nvidia.com;\n dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com\n header.b=khV++btL; arc=fail smtp.client-ip=52.101.52.21", "i=1; mx.microsoft.com 1; spf=pass\n smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com;\n dkim=pass header.d=nvidia.com; arc=none" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=uNjJ5QHnutlgt5Uk9IPWdQzl2DOPiAyg06fxlD64Ep0=;\n b=khV++btLMqnYLVeW3aLdYV4itK/Xv60G8nUNi7yVXqx90bjn3bj2ECaZ5pXBDujl7ltQjB9tVh4cb3wh/MVRfuYI4+LX+KE11Gh6QwLEGc3Ah9F+hQri1r9GBhJiaEf+3SnYT5Lm4oX/4DdZtjAP0reX3esRR8Y8LTzWz+i7Ilanh+UopDJewt2hpgrjQfEQVTSxVl8iKIxX0neyoEXBElyNGm6PtVUwjfvpn2B9tQQav0ueDKBTZZjBjU9KfwfGcUqwG0a73Rm3tY/7/QHeBZIwe/oG5mmEcOEA2r6sHFOI/VeA0eiyJTSRhuLWqCVQyxV79jwgJaAABovhxSfmBA==", "From": "Jason Gunthorpe <jgg@nvidia.com>", "To": "iommu@lists.linux.dev,\n\tJonathan Hunter <jonathanh@nvidia.com>,\n\tJoerg Roedel <joro@8bytes.org>,\n\tlinux-arm-kernel@lists.infradead.org,\n\tlinux-tegra@vger.kernel.org,\n\tRobin Murphy <robin.murphy@arm.com>,\n\tThierry Reding <thierry.reding@kernel.org>,\n\tKrishna Reddy <vdumpa@nvidia.com>,\n\tWill Deacon <will@kernel.org>", "Cc": "David Matlack <dmatlack@google.com>,\n\tPasha Tatashin <pasha.tatashin@soleen.com>,\n\tpatches@lists.linux.dev,\n\tSamiullah Khawaja <skhawaja@google.com>,\n\tMostafa Saleh <smostafa@google.com>", "Subject": "[PATCH 7/9] iommu/arm-smmu-v3: Directly encode CMDQ_OP_ATC_INV", "Date": "Fri, 1 May 2026 11:29:16 -0300", "Message-ID": "<7-v1-b7dc0a0d4aa0+3723d-smmu_no_cmdq_ent_jgg@nvidia.com>", "In-Reply-To": "<0-v1-b7dc0a0d4aa0+3723d-smmu_no_cmdq_ent_jgg@nvidia.com>", "References": "", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-ClientProxiedBy": "BL1P221CA0039.NAMP221.PROD.OUTLOOK.COM\n (2603:10b6:208:5b5::17) To LV8PR12MB9620.namprd12.prod.outlook.com\n (2603:10b6:408:2a1::19)", "Precedence": "bulk", "X-Mailing-List": "linux-tegra@vger.kernel.org", "List-Id": "<linux-tegra.vger.kernel.org>", "List-Subscribe": "<mailto:linux-tegra+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-tegra+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "LV8PR12MB9620:EE_|SA1PR12MB8096:EE_", "X-MS-Office365-Filtering-Correlation-Id": "9da3e7b2-ecc3-4348-e963-08dea78e09e1", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "\n\tBCL:0;ARA:13230040|376014|7416014|366016|1800799024|56012099003|18002099003|22082099003;", "X-Microsoft-Antispam-Message-Info": "\n\tQHsVPgIFf9hMijehBynNBpgxgiTCAjhb18Ig9v5oneEqtfszHeWPmVzS1D/ApXlzsBvtz8lxX6gUoCrWHo4JiLeUxH2om9t6xyFfR1I5QMSWjfLhoj5r29OCGYelNweihpH2QgY4ydxi1yzNg80R7pA/LuB3gR8QODmpmtxL9xddZ4GdFIlbKgVSgDGoH8io+E8loAUBmUhGfN5BR86YGIyou6Bnaj2ErWLr5SC7JXmAvB057FuFhSGH7/LlrGTklNnmr5juiK5l4GUXtxfoK7FjkqY5+b3OZP+0JYpxnbyF5bZED2SvzWARwDIJfRXIk1hk3V3GHx7Brhncc9ovYTdg3XLennG/DEShqKDJgfRdPqfYlXvVExRYRvE4lcpRXQGzwqx5Tx5lhoD+BqSgT9Y1uT0eGc3h3XkJfNXGXiXPuEo/wSshzQFJdKyg6arKGEUhAeUKhIrRwJVg5spuZcQVDimCu63Gpqc3Jr+pPH4ohF73jTLV0ZS+ZEMHzwnlRO9jlOW1ZH9f74YCZkFRk3NqL1dKkJ6wE68hLutwkZQbNa//J3cvU4qDkB9czUwXE8yeRBxUigfl2U/vanyACBf0n2GbxfpdRUEs2d2rzgaSserSM+83IhlAFSxffvm+PFdWTRuiojNz6L4UXmbvQvYg9IXB+CBrMajdx23XnSbmu93OloO87utS+90Z8CoC", "X-Forefront-Antispam-Report": "\n\tCIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:LV8PR12MB9620.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(376014)(7416014)(366016)(1800799024)(56012099003)(18002099003)(22082099003);DIR:OUT;SFP:1101;", "X-MS-Exchange-AntiSpam-MessageData-ChunkCount": "1", "X-MS-Exchange-AntiSpam-MessageData-0": "\n 8uPOq5M9IFwzc+czo5K+q9mlanNy/wv1wb0IzDCIHIKQ/LAj6UdWcQ+M6981Jz1XEULFnZOWShImV8Vfi+5KjZIfyRfGFxyR0dscQMRS9Ynzn+vylXX8O81reSTlj99uJxb+5oDKIVZpWrT7pYPEeL30TLuY14smMhewJwc40cX1N/BTiBjCuKj1NgLENnwe2J2StTkdNwVnqnobG8GcrJgfDd+lcSxt9QRXWN7Q7s3bfjL8tyoNlx6NRIR3A5PZ7fkEMrrgMJh5X1pNFWRoN/WnlQ0AeV8hdgWac+HO8QktW71HJl4nrod+Rd8MDTwr20RrlRtTI61fFOvoJXQeytMzTnom8c2+t1RMhaI1pEBMKe2dvoUTrQQYS5xg6asYXPzngiENOI9wfXyx0m74Oj4Jl6Iy++Z6XSdHFqa0CRUAJjPi2y4vzLOBy452pPxw3mpb3p40/aIbQgx4Wn8wFVMDzUEKOuqzavf08cn27TS4LEzS5ymreOBwqi1j+iXEL4PsMRpwl85iVufVb041BfrWhRMzhSlsu8Sh7/sYRQsIKYy+m+qmDE7XGQBPpRnwc5bNhsUIX6WnzipjnzcqHN+P7UAPycsZQXJLcpPMpUNos++dG1FgQre1JVBM6KkVQsZLrMH8Sb7CeI6cyXgEPGmJ7LRpIuTHbSRHJR6c+DEejKgVguZgFkzMUWhcRnX6WzYwvzw51UV4iWWnTwh+Cj1qpYLa7EAJqTd3RctHeADjhZd+rRqCYEep6dbUPLcqqWMmBhadRGH5PNSYnk4xDF+wSSiX4xyXLPEbtNTTTFTZATqLXimn6AjD62QAt+Zgz27t0CURDcoIcfb6z33LhMb1xr6/ZOsjy6K6T0lbK2xLeTTIkjYM9t3c4J/NaQBRWwjRP7fEoIWnUPzC1ILCK5GUiR2VQMfz7hBN6YUPqhl9cTDxslZ95WDHIlNacyavQNSWoDPb/n8BKjS0qoHzxigP4Yyg0BOs7x/wATpmb8Fs/UAEODh94gPH1qOJkZzNd4Dd0OSIYLlG8mpu/6rdod/ItfjBaDbDUOAxYjlHfPRtfIKRACPfqds5ghX7oYkX0wq7D118udyn3H/zAtt76QeWijsayfY8yWn/u+fJx04s/va+Fq/ka1SHnKumT01lNd7Z8oxNeXinv372ij6Iw4Y14XUJRbrwG3bkZhYPzchMLTw4tavM5Pvc3ASbnneto1Q7psFz/7hM+/PxIa0dhY/RB9T7wAtjgcKChG3EoFCJLq2kY/9jvhsrm6jxdGhIhjSyPzTlwXRo8/CT7ugD6+C+Lk7x9bV3Fw+dUDgYrHDeMtscONbMKMmHGncQkvmHc2SmGsT/g0K92U3K/RNqWgZ3OJwixD7gKFKTvROhlblHzYTsdZ+AbYCKNmEjoUWITQgaiirVWlyygQRi09U6mHpz6KHBFo0s3jqr4z+mZus0yh6wFcM6XeH6TTjtOJXfNhrXcaQn6QBc19uz8j/FkqFZbXPrqTPDiDyB42aAY7CBUbcwG+P+rl9HY3GHlxYgjaH9n5cJEkrQu8Lo7UdsaiOyRGXuS+kbdomxO+xY34CwV6KjLLPVL9C0IpEc5KVM3BnkoB/7vYC/jW71vZq8AADITNHBlTWK7vi1cH56T/d7iV1Whrb/E5Kz/lIkFIaQ7wXdXop1iZEuDIgfP2yX9mnuOeWGxn2FtibJZEnefkI2OfV3zCc+RknRbaXEinqz", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 9da3e7b2-ecc3-4348-e963-08dea78e09e1", "X-MS-Exchange-CrossTenant-AuthSource": "LV8PR12MB9620.namprd12.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Internal", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "01 May 2026 14:29:22.9672\n (UTC)", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-MailboxType": "HOSTED", "X-MS-Exchange-CrossTenant-UserPrincipalName": "\n DWk6GsbMv0Ftd2rhPInw2Qtt0CSgcN5NNa/gU1UIjkQcdaxMSpV34MlNiedPJFB8", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "SA1PR12MB8096" }, "content": "Add a new command make function and convert all the places using\nATC_INV.\n\nSplit out full invalidation to directly make the cmd instead of\noverloading size=0 to mean full invalidation.\n\nSigned-off-by: Jason Gunthorpe <jgg@nvidia.com>\n---\n drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 59 ++++++++-------------\n drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 27 +++++++---\n 2 files changed, 40 insertions(+), 46 deletions(-)", "diff": "diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c\nindex f9c25ca9a9e7b8..0cdf0752ff6d62 100644\n--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c\n+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c\n@@ -308,14 +308,6 @@ static int arm_smmu_cmdq_build_cmd(struct arm_smmu_cmd *cmd_out,\n \tcase CMDQ_OP_TLBI_EL2_ASID:\n \t\tcmd[0] |= FIELD_PREP(CMDQ_TLBI_0_ASID, ent->tlbi.asid);\n \t\tbreak;\n-\tcase CMDQ_OP_ATC_INV:\n-\t\tcmd[0] |= FIELD_PREP(CMDQ_0_SSV, ent->substream_valid);\n-\t\tcmd[0] |= FIELD_PREP(CMDQ_ATC_0_GLOBAL, ent->atc.global);\n-\t\tcmd[0] |= FIELD_PREP(CMDQ_ATC_0_SSID, ent->atc.ssid);\n-\t\tcmd[0] |= FIELD_PREP(CMDQ_ATC_0_SID, ent->atc.sid);\n-\t\tcmd[1] |= FIELD_PREP(CMDQ_ATC_1_SIZE, ent->atc.size);\n-\t\tcmd[1] |= ent->atc.addr & CMDQ_ATC_1_ADDR_MASK;\n-\t\tbreak;\n \tcase CMDQ_OP_CMD_SYNC:\n \t\tif (ent->sync.msiaddr) {\n \t\t\tcmd[0] |= FIELD_PREP(CMDQ_SYNC_0_CS, CMDQ_SYNC_0_CS_IRQ);\n@@ -2371,9 +2363,8 @@ static irqreturn_t arm_smmu_combined_irq_handler(int irq, void *dev)\n \treturn IRQ_WAKE_THREAD;\n }\n \n-static void\n-arm_smmu_atc_inv_to_cmd(int ssid, unsigned long iova, size_t size,\n-\t\t\tstruct arm_smmu_cmdq_ent *cmd)\n+static struct arm_smmu_cmd\n+arm_smmu_atc_inv_to_cmd(u32 sid, int ssid, unsigned long iova, size_t size)\n {\n \tsize_t log2_span;\n \tsize_t span_mask;\n@@ -2395,17 +2386,6 @@ arm_smmu_atc_inv_to_cmd(int ssid, unsigned long iova, size_t size,\n \t * This has the unpleasant side-effect of invalidating all PASID-tagged\n \t * ATC entries within the address range.\n \t */\n-\t*cmd = (struct arm_smmu_cmdq_ent) {\n-\t\t.opcode\t\t\t= CMDQ_OP_ATC_INV,\n-\t\t.substream_valid\t= (ssid != IOMMU_NO_PASID),\n-\t\t.atc.ssid\t\t= ssid,\n-\t};\n-\n-\tif (!size) {\n-\t\tcmd->atc.size = ATC_INV_SIZE_ALL;\n-\t\treturn;\n-\t}\n-\n \tpage_start\t= iova >> inval_grain_shift;\n \tpage_end\t= (iova + size - 1) >> inval_grain_shift;\n \n@@ -2434,24 +2414,25 @@ arm_smmu_atc_inv_to_cmd(int ssid, unsigned long iova, size_t size,\n \n \tpage_start\t&= ~span_mask;\n \n-\tcmd->atc.addr\t= page_start << inval_grain_shift;\n-\tcmd->atc.size\t= log2_span;\n+\treturn arm_smmu_make_cmd_atc_inv(sid, ssid,\n+\t\t\t\t\t page_start << inval_grain_shift,\n+\t\t\t\t\t log2_span);\n }\n \n static int arm_smmu_atc_inv_master(struct arm_smmu_master *master,\n \t\t\t\t ioasid_t ssid)\n {\n \tint i;\n-\tstruct arm_smmu_cmdq_ent cmd;\n+\tstruct arm_smmu_cmd cmd;\n \tstruct arm_smmu_cmdq_batch cmds;\n \n-\tarm_smmu_atc_inv_to_cmd(ssid, 0, 0, &cmd);\n-\n-\tarm_smmu_cmdq_batch_init(master->smmu, &cmds, &cmd);\n-\tfor (i = 0; i < master->num_streams; i++) {\n-\t\tcmd.atc.sid = master->streams[i].id;\n-\t\tarm_smmu_cmdq_batch_add(master->smmu, &cmds, &cmd);\n-\t}\n+\tcmd = arm_smmu_make_cmd_atc_inv_all(0, IOMMU_NO_PASID);\n+\tarm_smmu_cmdq_batch_init_cmd(master->smmu, &cmds, &cmd);\n+\tfor (i = 0; i < master->num_streams; i++)\n+\t\tarm_smmu_cmdq_batch_add_cmd(\n+\t\t\tmaster->smmu, &cmds,\n+\t\t\tarm_smmu_make_cmd_atc_inv_all(master->streams[i].id,\n+\t\t\t\t\t\t ssid));\n \n \treturn arm_smmu_cmdq_batch_submit(master->smmu, &cmds);\n }\n@@ -2650,14 +2631,16 @@ static void __arm_smmu_domain_inv_range(struct arm_smmu_invs *invs,\n \t\t\tarm_smmu_cmdq_batch_add(smmu, &cmds, &cmd);\n \t\t\tbreak;\n \t\tcase INV_TYPE_ATS:\n-\t\t\tarm_smmu_atc_inv_to_cmd(cur->ssid, iova, size, &cmd);\n-\t\t\tcmd.atc.sid = cur->id;\n-\t\t\tarm_smmu_cmdq_batch_add(smmu, &cmds, &cmd);\n+\t\t\tarm_smmu_cmdq_batch_add_cmd(\n+\t\t\t\tsmmu, &cmds,\n+\t\t\t\tarm_smmu_atc_inv_to_cmd(cur->id, cur->ssid,\n+\t\t\t\t\t\t\tiova, size));\n \t\t\tbreak;\n \t\tcase INV_TYPE_ATS_FULL:\n-\t\t\tarm_smmu_atc_inv_to_cmd(IOMMU_NO_PASID, 0, 0, &cmd);\n-\t\t\tcmd.atc.sid = cur->id;\n-\t\t\tarm_smmu_cmdq_batch_add(smmu, &cmds, &cmd);\n+\t\t\tarm_smmu_cmdq_batch_add_cmd(\n+\t\t\t\tsmmu, &cmds,\n+\t\t\t\tarm_smmu_make_cmd_atc_inv_all(cur->id,\n+\t\t\t\t\t\t\t IOMMU_NO_PASID));\n \t\t\tbreak;\n \t\tdefault:\n \t\t\tWARN_ON_ONCE(1);\ndiff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h\nindex 10b3d95d9ee660..194f73cabef5c9 100644\n--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h\n+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h\n@@ -552,6 +552,25 @@ static inline struct arm_smmu_cmd arm_smmu_make_cmd_pri_resp(u32 sid, u32 ssid,\n \treturn cmd;\n }\n \n+static inline struct arm_smmu_cmd arm_smmu_make_cmd_atc_inv(u32 sid, u32 ssid,\n+\t\t\t\t\t\t\t u64 addr, u8 size)\n+{\n+\tstruct arm_smmu_cmd cmd = arm_smmu_make_cmd_op(CMDQ_OP_ATC_INV);\n+\n+\tcmd.data[0] |= FIELD_PREP(CMDQ_0_SSV, ssid != IOMMU_NO_PASID) |\n+\t\t FIELD_PREP(CMDQ_ATC_0_SSID, ssid) |\n+\t\t FIELD_PREP(CMDQ_ATC_0_SID, sid);\n+\tcmd.data[1] |= FIELD_PREP(CMDQ_ATC_1_SIZE, size) |\n+\t\t (addr & CMDQ_ATC_1_ADDR_MASK);\n+\treturn cmd;\n+}\n+\n+static inline struct arm_smmu_cmd arm_smmu_make_cmd_atc_inv_all(u32 sid,\n+\t\t\t\t\t\t\t\tu32 ssid)\n+{\n+\treturn arm_smmu_make_cmd_atc_inv(sid, ssid, 0, ATC_INV_SIZE_ALL);\n+}\n+\n /* Event queue */\n #define EVTQ_ENT_SZ_SHIFT\t\t5\n #define EVTQ_ENT_DWORDS\t\t\t((1 << EVTQ_ENT_SZ_SHIFT) >> 3)\n@@ -630,14 +649,6 @@ struct arm_smmu_cmdq_ent {\n \t\t\tu64\t\t\taddr;\n \t\t} tlbi;\n \n-\t\tstruct {\n-\t\t\tu32\t\t\tsid;\n-\t\t\tu32\t\t\tssid;\n-\t\t\tu64\t\t\taddr;\n-\t\t\tu8\t\t\tsize;\n-\t\t\tbool\t\t\tglobal;\n-\t\t} atc;\n-\n \t\tstruct {\n \t\t\tu64\t\t\tmsiaddr;\n \t\t} sync;\n", "prefixes": [ "7/9" ] }