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GET /api/1.2/patches/2231893/?format=api
{ "id": 2231893, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2231893/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/patch/8-v1-b7dc0a0d4aa0+3723d-smmu_no_cmdq_ent_jgg@nvidia.com/", "project": { "id": 21, "url": "http://patchwork.ozlabs.org/api/1.2/projects/21/?format=api", "name": "Linux Tegra Development", "link_name": "linux-tegra", "list_id": "linux-tegra.vger.kernel.org", "list_email": "linux-tegra@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<8-v1-b7dc0a0d4aa0+3723d-smmu_no_cmdq_ent_jgg@nvidia.com>", "list_archive_url": null, "date": "2026-05-01T14:29:17", "name": "[8/9] iommu/arm-smmu-v3: Directly encode CMDQ_OP_SYNC", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "6a9db7b6474e4f79f9e73c1f61d9177d497e1416", "submitter": { "id": 79424, "url": "http://patchwork.ozlabs.org/api/1.2/people/79424/?format=api", "name": "Jason Gunthorpe", "email": "jgg@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-tegra/patch/8-v1-b7dc0a0d4aa0+3723d-smmu_no_cmdq_ent_jgg@nvidia.com/mbox/", "series": [ { "id": 502465, "url": "http://patchwork.ozlabs.org/api/1.2/series/502465/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/list/?series=502465", "date": "2026-05-01T14:29:09", "name": "Remove SMMUv3 struct arm_smmu_cmdq_ent", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/502465/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2231893/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2231893/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-tegra+bounces-14139-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-tegra@vger.kernel.org" ], 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header.d=nvidia.com; arc=none" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=+23ibNiV1Yc2rzUh1l1KkI6KdwxQfsvZjfYHXBaB5PU=;\n b=n3qcdOBnYZSV2Mio7nLBXu4dWB9jTDouDc21FwW3UnDLuVwqwszq2amA0r13gdvv4bPAJLT8YC61NkJ1wEngA7kQzwmuNKYVrXhFbI8S5+YIq/PLsijDQU9YAniCQlnywF++AYZE86bDMNEeAw44HghkO7S/X+5KVUpDqgFjJrVpUuTRe1aeQBbKvHBKq/uH2eNx0UVpioMEC5JU4OGjM+q8QniKQpJ7krttOEEy0DkI1hnnJV1/GqHQ7AfJAp5zTdcp8Wlb9uZabV7jRGmO1SkDxjaLo1l9qu1LH/sCjpGiH+zHen4SkYrSIiyvCyTM+wrWkxG8G7tz4b25apTMeA==", "From": "Jason Gunthorpe <jgg@nvidia.com>", "To": "iommu@lists.linux.dev,\n\tJonathan Hunter <jonathanh@nvidia.com>,\n\tJoerg Roedel <joro@8bytes.org>,\n\tlinux-arm-kernel@lists.infradead.org,\n\tlinux-tegra@vger.kernel.org,\n\tRobin Murphy <robin.murphy@arm.com>,\n\tThierry Reding <thierry.reding@kernel.org>,\n\tKrishna Reddy <vdumpa@nvidia.com>,\n\tWill Deacon <will@kernel.org>", "Cc": "David Matlack <dmatlack@google.com>,\n\tPasha Tatashin <pasha.tatashin@soleen.com>,\n\tpatches@lists.linux.dev,\n\tSamiullah Khawaja <skhawaja@google.com>,\n\tMostafa Saleh <smostafa@google.com>", "Subject": "[PATCH 8/9] iommu/arm-smmu-v3: Directly encode CMDQ_OP_SYNC", "Date": "Fri, 1 May 2026 11:29:17 -0300", "Message-ID": "<8-v1-b7dc0a0d4aa0+3723d-smmu_no_cmdq_ent_jgg@nvidia.com>", "In-Reply-To": "<0-v1-b7dc0a0d4aa0+3723d-smmu_no_cmdq_ent_jgg@nvidia.com>", "References": "", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-ClientProxiedBy": "MN2PR05CA0004.namprd05.prod.outlook.com\n (2603:10b6:208:c0::17) To LV8PR12MB9620.namprd12.prod.outlook.com\n (2603:10b6:408:2a1::19)", "Precedence": "bulk", "X-Mailing-List": "linux-tegra@vger.kernel.org", "List-Id": "<linux-tegra.vger.kernel.org>", "List-Subscribe": "<mailto:linux-tegra+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-tegra+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", 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O5peZc8YjgPt3aTpr6qpzTLkPtzAokA8Avop1UrEw0GpDq2XWIMZurJhl+Ec+Wx6n/mPJhimiX5XNVAuruT5kE57ponEsQpCkRLQ3AzLoWoG/ikjn9rYmRYx2kq91XlnBaOdP+1xi25kNSTbMZ3K9UvBbHCX5wGWSbEM+QLubBnh2yWyJ5ji/FQCRrkihf8E7BgTfmX/TnEM4hup506JcOtfkleJQKBahAjVAQFynpTR8fL3fh8mCTTaepVzPIeN4/Rsw2YqHRS3lTohiiUiskRlP2v/AXLbC9qSfbXtSQlHxMqr6ES/D7JFFQgVgsPpsMSEtdSn691wvXkvhIiFdZioB80976Tfn7KuQwMWiFS2EWWGvAYUUCPGnOGJVGrqxCsIetSenOR85aPc2pdHoWrTXW5it7SVEva4hjFc53JYh91jpLjV5KeqEZmopCCNru0M+VzNjQSRWxVeA5DHENjYBdAz7tKx3gAlirZqahr5xgMW+umhSwqjEH07nSf44tKx4oJ2oJcWYaFLO+W7Y/sZYkAISdPPIapZHthkm53qAgqBNAx4USqNyr9YmpOgX/1aEPK0hSUGxdjT5DSeWym3QcSoRJR02gL7WEL8W6eGjPMv907n1PwsEf9npfO7McFQarrq7N0FUa1BqF/c/ZCR+Lisi3aP0BGfCGpb69fHTwZT4sZGXpjTioHLj9DBJ7TlAOC0m/YBiIekE6LLY97wMmLJYlWO+7Gln/o45a4lMF5zKUhq2HhJFuV3FXM8TqG+0pI721z5QOUSiAuHZ5r1B3fKY6/rbPMIOt+Kaw3ytuPSWm1a6lVzV3PEFw8jFHS9UGJlvAX2/6ASl4fSrdrorqO+g5i8DC7TjtOIOltjfrmLbN4a0Ct1eJhRomImfgvrn/e43vBunBaeTuVJv40wr5k94O/l+EHFsJfm/Ng+cODhCkd91SEAXvhQK7j6GbRioCRwNsb2nOiO8I1a96HZMMEuPdbQ3TXY1Gop0zhUwqUJtXSm2TKPdmj2e4nrQVBbHw1THg2NfQeYdLrZDcDvtQw82GpFJ5fdlcTXv9aQZptht4IUmJ7R+Utl10MNJZzKU8OTO1IM6/K6p0lMPw8dfk9r61NKKjZvhR6GFSb321jzOnsVZVCU9roy5Vo4jcSbaiHB79SYsmBpAO2srIlqZ9uV/eXPZF+hFxT+48d37KctmVpL58lDH070SVRZApWh+M9XdtJf8dGgOqI9qtsZ5Nw/OwttHECFyVZdzTnyTCnSf8rNTz1e+Ftt7r/g/xbkdAPqNlx2YgIdPoONmn3U8buTLrI1HSlL2fatmIZfDMlMSAPqP3r0ybbAgr3TsLEHIuUsUz97jgT1vFkhLVWkR/+jzWO1yF5lOBC9L1Q+qV+s1cWfITVNOTszlGx7zM4VZosxRKPQdfErLomF1RmIDQ0VtzsxsFhAPFV/TmP2+kv+nwcZFkAjdmPA8xBxlig+o/jtvmvrqroOdu0HflNs6N9hY8Z9Z/oOIlkXP51xpAG65UdVmGzY0/aw41DnR6qRBhghKVVBj0aCuRP8ayyAw8jzCZYHsKDtNnYEIpNVUaIDNF3ciVS5fMNl8Ml3RY40kVTxXvqlSnHRfFvELV5tB2h0WasEvU5Dm2LU2BOAJeWV32HP34JTXKO2MqzFHKZZjjVWLVMfRnUG0wqUFrzSagKUl/24Sr5t9y/fQvchCFgQNMivGkJlCxz0c2fa", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 8e0aaf7e-3170-4d8a-fbd7-08dea78e0949", "X-MS-Exchange-CrossTenant-AuthSource": "LV8PR12MB9620.namprd12.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Internal", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "01 May 2026 14:29:22.5517\n (UTC)", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-MailboxType": "HOSTED", "X-MS-Exchange-CrossTenant-UserPrincipalName": "\n S9+XF/YgrUCS0tQyZhqyIyq5i0EA4KApDP3I7b9ekCmdRP0u3tGLnNDSEEHpG2OH", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "SA1PR12MB8096" }, "content": "Change the flow so the caller controls the CS field and remove the\nweird u64p_replace_bits() thing to override it.\n\nSigned-off-by: Jason Gunthorpe <jgg@nvidia.com>\n---\n drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 42 ++++++++-------------\n drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 16 ++++++--\n 2 files changed, 27 insertions(+), 31 deletions(-)", "diff": "diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c\nindex 0cdf0752ff6d62..8147b9cdcc6b99 100644\n--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c\n+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c\n@@ -308,16 +308,6 @@ static int arm_smmu_cmdq_build_cmd(struct arm_smmu_cmd *cmd_out,\n \tcase CMDQ_OP_TLBI_EL2_ASID:\n \t\tcmd[0] |= FIELD_PREP(CMDQ_TLBI_0_ASID, ent->tlbi.asid);\n \t\tbreak;\n-\tcase CMDQ_OP_CMD_SYNC:\n-\t\tif (ent->sync.msiaddr) {\n-\t\t\tcmd[0] |= FIELD_PREP(CMDQ_SYNC_0_CS, CMDQ_SYNC_0_CS_IRQ);\n-\t\t\tcmd[1] |= ent->sync.msiaddr & CMDQ_SYNC_1_MSIADDR_MASK;\n-\t\t} else {\n-\t\t\tcmd[0] |= FIELD_PREP(CMDQ_SYNC_0_CS, CMDQ_SYNC_0_CS_SEV);\n-\t\t}\n-\t\tcmd[0] |= FIELD_PREP(CMDQ_SYNC_0_MSH, ARM_SMMU_SH_ISH);\n-\t\tcmd[0] |= FIELD_PREP(CMDQ_SYNC_0_MSIATTR, ARM_SMMU_MEMATTR_OIWB);\n-\t\tbreak;\n \tdefault:\n \t\treturn -ENOENT;\n \t}\n@@ -350,23 +340,24 @@ static void arm_smmu_cmdq_build_sync_cmd(struct arm_smmu_cmd *cmd,\n \t\t\t\t\t struct arm_smmu_cmdq *cmdq, u32 prod)\n {\n \tstruct arm_smmu_queue *q = &cmdq->q;\n-\tstruct arm_smmu_cmdq_ent ent = {\n-\t\t.opcode = CMDQ_OP_CMD_SYNC,\n-\t};\n+\tu64 msiaddr = 0;\n+\tunsigned int cs;\n \n \t/*\n \t * Beware that Hi16xx adds an extra 32 bits of goodness to its MSI\n \t * payload, so the write will zero the entire command on that platform.\n \t */\n-\tif (smmu->options & ARM_SMMU_OPT_MSIPOLL) {\n-\t\tent.sync.msiaddr = q->base_dma + Q_IDX(&q->llq, prod) *\n-\t\t\t\t q->ent_dwords * 8;\n+\tif (arm_smmu_cmdq_needs_busy_polling(smmu, cmdq)) {\n+\t\tcs = CMDQ_SYNC_0_CS_NONE;\n+\t} else if (smmu->options & ARM_SMMU_OPT_MSIPOLL) {\n+\t\tcs = CMDQ_SYNC_0_CS_IRQ;\n+\t\tmsiaddr = q->base_dma + Q_IDX(&q->llq, prod) *\n+\t\t\t q->ent_dwords * 8;\n+\t} else {\n+\t\tcs = CMDQ_SYNC_0_CS_SEV;\n \t}\n \n-\tarm_smmu_cmdq_build_cmd(cmd, &ent);\n-\tif (arm_smmu_cmdq_needs_busy_polling(smmu, cmdq))\n-\t\tu64p_replace_bits(&cmd->data[0], CMDQ_SYNC_0_CS_NONE,\n-\t\t\t\t CMDQ_SYNC_0_CS);\n+\t*cmd = arm_smmu_make_cmd_sync(cs, msiaddr);\n }\n \n void __arm_smmu_cmdq_skip_err(struct arm_smmu_device *smmu,\n@@ -383,9 +374,6 @@ void __arm_smmu_cmdq_skip_err(struct arm_smmu_device *smmu,\n \tstruct arm_smmu_cmd cmd;\n \tu32 cons = readl_relaxed(q->cons_reg);\n \tu32 idx = FIELD_GET(CMDQ_CONS_ERR, cons);\n-\tstruct arm_smmu_cmdq_ent cmd_sync = {\n-\t\t.opcode = CMDQ_OP_CMD_SYNC,\n-\t};\n \n \tdev_err(smmu->dev, \"CMDQ error (cons 0x%08x): %s\\n\", cons,\n \t\tidx < ARRAY_SIZE(cerror_str) ? cerror_str[idx] : \"Unknown\");\n@@ -419,10 +407,10 @@ void __arm_smmu_cmdq_skip_err(struct arm_smmu_device *smmu,\n \t\tdev_err(smmu->dev, \"\\t0x%016llx\\n\", (unsigned long long)cmd.data[i]);\n \n \t/* Convert the erroneous command into a CMD_SYNC */\n-\tarm_smmu_cmdq_build_cmd(&cmd, &cmd_sync);\n-\tif (arm_smmu_cmdq_needs_busy_polling(smmu, cmdq))\n-\t\tu64p_replace_bits(&cmd.data[0], CMDQ_SYNC_0_CS_NONE,\n-\t\t\t\t CMDQ_SYNC_0_CS);\n+\tcmd = arm_smmu_make_cmd_sync(\n+\t\tarm_smmu_cmdq_needs_busy_polling(smmu, cmdq) ?\n+\t\t\tCMDQ_SYNC_0_CS_NONE : CMDQ_SYNC_0_CS_SEV,\n+\t\t0);\n \n \tqueue_write(Q_ENT(q, cons), cmd.data, q->ent_dwords);\n }\ndiff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h\nindex 194f73cabef5c9..538380de7d48a0 100644\n--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h\n+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h\n@@ -571,6 +571,18 @@ static inline struct arm_smmu_cmd arm_smmu_make_cmd_atc_inv_all(u32 sid,\n \treturn arm_smmu_make_cmd_atc_inv(sid, ssid, 0, ATC_INV_SIZE_ALL);\n }\n \n+static inline struct arm_smmu_cmd arm_smmu_make_cmd_sync(unsigned int cs,\n+\t\t\t\t\t\t\t u64 msiaddr)\n+{\n+\tstruct arm_smmu_cmd cmd = arm_smmu_make_cmd_op(CMDQ_OP_CMD_SYNC);\n+\n+\tcmd.data[0] |= FIELD_PREP(CMDQ_SYNC_0_CS, cs) |\n+\t\t FIELD_PREP(CMDQ_SYNC_0_MSH, ARM_SMMU_SH_ISH) |\n+\t\t FIELD_PREP(CMDQ_SYNC_0_MSIATTR, ARM_SMMU_MEMATTR_OIWB);\n+\tcmd.data[1] |= msiaddr & CMDQ_SYNC_1_MSIADDR_MASK;\n+\treturn cmd;\n+}\n+\n /* Event queue */\n #define EVTQ_ENT_SZ_SHIFT\t\t5\n #define EVTQ_ENT_DWORDS\t\t\t((1 << EVTQ_ENT_SZ_SHIFT) >> 3)\n@@ -648,10 +660,6 @@ struct arm_smmu_cmdq_ent {\n \t\t\tu8\t\t\ttg;\n \t\t\tu64\t\t\taddr;\n \t\t} tlbi;\n-\n-\t\tstruct {\n-\t\t\tu64\t\t\tmsiaddr;\n-\t\t} sync;\n \t};\n };\n \n", "prefixes": [ "8/9" ] }