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GET /api/1.2/patches/2231892/?format=api
{ "id": 2231892, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2231892/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/patch/3-v1-b7dc0a0d4aa0+3723d-smmu_no_cmdq_ent_jgg@nvidia.com/", "project": { "id": 21, "url": "http://patchwork.ozlabs.org/api/1.2/projects/21/?format=api", "name": "Linux Tegra Development", "link_name": "linux-tegra", "list_id": "linux-tegra.vger.kernel.org", "list_email": "linux-tegra@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<3-v1-b7dc0a0d4aa0+3723d-smmu_no_cmdq_ent_jgg@nvidia.com>", "list_archive_url": null, "date": "2026-05-01T14:29:12", "name": "[3/9] iommu/arm-smmu-v3: Use the HW arm_smmu_cmd in cmdq submission functions", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "e193cfa6e29592ad8627d723eb60f1de3b62ad44", "submitter": { "id": 79424, "url": "http://patchwork.ozlabs.org/api/1.2/people/79424/?format=api", "name": "Jason Gunthorpe", "email": "jgg@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-tegra/patch/3-v1-b7dc0a0d4aa0+3723d-smmu_no_cmdq_ent_jgg@nvidia.com/mbox/", "series": [ { "id": 502465, "url": "http://patchwork.ozlabs.org/api/1.2/series/502465/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/list/?series=502465", "date": "2026-05-01T14:29:09", "name": "Remove SMMUv3 struct arm_smmu_cmdq_ent", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/502465/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2231892/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2231892/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-tegra+bounces-14138-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-tegra@vger.kernel.org" ], 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dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com\n header.b=LYyIDXyj; arc=fail smtp.client-ip=52.101.52.21", "i=1; mx.microsoft.com 1; spf=pass\n smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com;\n dkim=pass header.d=nvidia.com; arc=none" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=q5+RRk8gmuwu1ShgI4kGOGgWDuE1ikupDWuNgYtX+XU=;\n b=LYyIDXyjWJCWU+iDIStI1YdD0WeBJY4gxtC5AqDyLCPQ63T33ZmqzfHSFpsljayDbeqIhcCCWjW878jHEHpTZA+cEAgA2YEELhfc4wMdsL55KbqRa1YLTqahNzgMs+OSggwA+tf6PpMlsH2kxzpLjxvaRFt5+j2msVpapcDYxR/kYkWeMqn9ectKcgEBZsKsksH42O2yIXHBRnEtQE8vw13ZQjJahLo/UtMxnAXnCN9TB5674DEMC9cbDYGBALQDF+PLffi8UrFDT8NNUmf9TJ/tWxBkIfeUMnNmDBaxkIUhiO4rhjcLzsqg1Xmrwccf66y3CU3ujzkCXt0nMZsrrA==", "From": "Jason Gunthorpe <jgg@nvidia.com>", "To": "iommu@lists.linux.dev,\n\tJonathan Hunter <jonathanh@nvidia.com>,\n\tJoerg Roedel <joro@8bytes.org>,\n\tlinux-arm-kernel@lists.infradead.org,\n\tlinux-tegra@vger.kernel.org,\n\tRobin Murphy <robin.murphy@arm.com>,\n\tThierry Reding <thierry.reding@kernel.org>,\n\tKrishna Reddy <vdumpa@nvidia.com>,\n\tWill Deacon <will@kernel.org>", "Cc": "David Matlack <dmatlack@google.com>,\n\tPasha Tatashin <pasha.tatashin@soleen.com>,\n\tpatches@lists.linux.dev,\n\tSamiullah Khawaja <skhawaja@google.com>,\n\tMostafa Saleh <smostafa@google.com>", "Subject": "[PATCH 3/9] iommu/arm-smmu-v3: Use the HW arm_smmu_cmd in cmdq\n submission functions", "Date": "Fri, 1 May 2026 11:29:12 -0300", "Message-ID": "<3-v1-b7dc0a0d4aa0+3723d-smmu_no_cmdq_ent_jgg@nvidia.com>", "In-Reply-To": "<0-v1-b7dc0a0d4aa0+3723d-smmu_no_cmdq_ent_jgg@nvidia.com>", "References": "", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-ClientProxiedBy": "BL1P221CA0031.NAMP221.PROD.OUTLOOK.COM\n (2603:10b6:208:5b5::10) To LV8PR12MB9620.namprd12.prod.outlook.com\n (2603:10b6:408:2a1::19)", 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"X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n a9393881-be6b-4a36-9bb6-08dea78e091d", "X-MS-Exchange-CrossTenant-AuthSource": "LV8PR12MB9620.namprd12.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Internal", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "01 May 2026 14:29:21.6304\n (UTC)", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-MailboxType": "HOSTED", "X-MS-Exchange-CrossTenant-UserPrincipalName": "\n YBQiI7D0Bx/lyjrHnA8hUc1Q0lgp5HGl55hfU7LK2DWT+NMSISvE2EMWG4Gp+VJU", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "SA1PR12MB8096" }, "content": "Continue removing struct arm_smmu_cmdq_ent in favour of the HW based\nstruct arm_smmu_cmd. Switch the lower level issue commands to work on\nthe native struct by lifting arm_smmu_cmdq_build_cmd() into all the\ncallers.\n\nFollowing patches will revise each of the arm_smmu_cmdq_build_cmd()\ncall sites to replace it with the HW struct.\n\nSigned-off-by: Jason Gunthorpe <jgg@nvidia.com>\n---\n drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 53 ++++++++++++---------\n 1 file changed, 30 insertions(+), 23 deletions(-)", "diff": "diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c\nindex 5cdeaec890592f..67d23e9c54804e 100644\n--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c\n+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c\n@@ -921,31 +921,23 @@ int arm_smmu_cmdq_issue_cmdlist(struct arm_smmu_device *smmu,\n }\n \n static int __arm_smmu_cmdq_issue_cmd(struct arm_smmu_device *smmu,\n-\t\t\t\t struct arm_smmu_cmdq_ent *ent,\n+\t\t\t\t struct arm_smmu_cmd *cmd,\n \t\t\t\t bool sync)\n {\n-\tstruct arm_smmu_cmd cmd;\n-\n-\tif (unlikely(arm_smmu_cmdq_build_cmd(cmd.data, ent))) {\n-\t\tdev_warn(smmu->dev, \"ignoring unknown CMDQ opcode 0x%x\\n\",\n-\t\t\t ent->opcode);\n-\t\treturn -EINVAL;\n-\t}\n-\n \treturn arm_smmu_cmdq_issue_cmdlist(\n-\t\tsmmu, arm_smmu_get_cmdq(smmu, &cmd), cmd.data, 1, sync);\n+\t\tsmmu, arm_smmu_get_cmdq(smmu, cmd), cmd->data, 1, sync);\n }\n \n static int arm_smmu_cmdq_issue_cmd(struct arm_smmu_device *smmu,\n-\t\t\t\t struct arm_smmu_cmdq_ent *ent)\n+\t\t\t\t struct arm_smmu_cmd *cmd)\n {\n-\treturn __arm_smmu_cmdq_issue_cmd(smmu, ent, false);\n+\treturn __arm_smmu_cmdq_issue_cmd(smmu, cmd, false);\n }\n \n static int arm_smmu_cmdq_issue_cmd_with_sync(struct arm_smmu_device *smmu,\n-\t\t\t\t\t struct arm_smmu_cmdq_ent *ent)\n+\t\t\t\t\t struct arm_smmu_cmd *cmd)\n {\n-\treturn __arm_smmu_cmdq_issue_cmd(smmu, ent, true);\n+\treturn __arm_smmu_cmdq_issue_cmd(smmu, cmd, true);\n }\n \n static void arm_smmu_cmdq_batch_init_cmd(struct arm_smmu_device *smmu,\n@@ -1013,6 +1005,7 @@ static void arm_smmu_page_response(struct device *dev, struct iopf_fault *unused\n \tstruct arm_smmu_cmdq_ent cmd = {0};\n \tstruct arm_smmu_master *master = dev_iommu_priv_get(dev);\n \tint sid = master->streams[0].id;\n+\tstruct arm_smmu_cmd hw_cmd;\n \n \tif (WARN_ON(!master->stall_enabled))\n \t\treturn;\n@@ -1032,7 +1025,9 @@ static void arm_smmu_page_response(struct device *dev, struct iopf_fault *unused\n \t\tbreak;\n \t}\n \n-\tarm_smmu_cmdq_issue_cmd(master->smmu, &cmd);\n+\tarm_smmu_cmdq_build_cmd(hw_cmd.data, &cmd);\n+\tarm_smmu_cmdq_issue_cmd(master->smmu, &hw_cmd);\n+\n \t/*\n \t * Don't send a SYNC, it doesn't do anything for RESUME or PRI_RESP.\n \t * RESUME consumption guarantees that the stalled transaction will be\n@@ -1861,14 +1856,16 @@ static void arm_smmu_ste_writer_sync_entry(struct arm_smmu_entry_writer *writer)\n {\n \tstruct arm_smmu_ste_writer *ste_writer =\n \t\tcontainer_of(writer, struct arm_smmu_ste_writer, writer);\n-\tstruct arm_smmu_cmdq_ent cmd = {\n+\tstruct arm_smmu_cmdq_ent ent = {\n \t\t.opcode\t= CMDQ_OP_CFGI_STE,\n \t\t.cfgi\t= {\n \t\t\t.sid\t= ste_writer->sid,\n \t\t\t.leaf\t= true,\n \t\t},\n \t};\n+\tstruct arm_smmu_cmd cmd;\n \n+\tarm_smmu_cmdq_build_cmd(cmd.data, &ent);\n \tarm_smmu_cmdq_issue_cmd_with_sync(writer->master->smmu, &cmd);\n }\n \n@@ -1896,11 +1893,13 @@ static void arm_smmu_write_ste(struct arm_smmu_master *master, u32 sid,\n \t/* It's likely that we'll want to use the new STE soon */\n \tif (!(smmu->options & ARM_SMMU_OPT_SKIP_PREFETCH)) {\n \t\tstruct arm_smmu_cmdq_ent\n-\t\t\tprefetch_cmd = { .opcode = CMDQ_OP_PREFETCH_CFG,\n+\t\t\tprefetch_ent = { .opcode = CMDQ_OP_PREFETCH_CFG,\n \t\t\t\t\t .prefetch = {\n \t\t\t\t\t\t .sid = sid,\n \t\t\t\t\t } };\n+\t\tstruct arm_smmu_cmd prefetch_cmd;\n \n+\t\tarm_smmu_cmdq_build_cmd(prefetch_cmd.data, &prefetch_ent);\n \t\tarm_smmu_cmdq_issue_cmd(smmu, &prefetch_cmd);\n \t}\n }\n@@ -2328,7 +2327,7 @@ static void arm_smmu_handle_ppr(struct arm_smmu_device *smmu, u64 *evt)\n \t\t evt[1] & PRIQ_1_ADDR_MASK);\n \n \tif (last) {\n-\t\tstruct arm_smmu_cmdq_ent cmd = {\n+\t\tstruct arm_smmu_cmdq_ent ent = {\n \t\t\t.opcode\t\t\t= CMDQ_OP_PRI_RESP,\n \t\t\t.substream_valid\t= ssv,\n \t\t\t.pri\t\t\t= {\n@@ -2338,7 +2337,9 @@ static void arm_smmu_handle_ppr(struct arm_smmu_device *smmu, u64 *evt)\n \t\t\t\t.resp\t= PRI_RESP_DENY,\n \t\t\t},\n \t\t};\n+\t\tstruct arm_smmu_cmd cmd;\n \n+\t\tarm_smmu_cmdq_build_cmd(cmd.data, &ent);\n \t\tarm_smmu_cmdq_issue_cmd(smmu, &cmd);\n \t}\n }\n@@ -3446,6 +3447,7 @@ arm_smmu_install_new_domain_invs(struct arm_smmu_attach_state *state)\n static void arm_smmu_inv_flush_iotlb_tag(struct arm_smmu_inv *inv)\n {\n \tstruct arm_smmu_cmdq_ent cmd = {};\n+\tstruct arm_smmu_cmd hw_cmd;\n \n \tswitch (inv->type) {\n \tcase INV_TYPE_S1_ASID:\n@@ -3460,7 +3462,8 @@ static void arm_smmu_inv_flush_iotlb_tag(struct arm_smmu_inv *inv)\n \t}\n \n \tcmd.opcode = inv->nsize_opcode;\n-\tarm_smmu_cmdq_issue_cmd_with_sync(inv->smmu, &cmd);\n+\tarm_smmu_cmdq_build_cmd(hw_cmd.data, &cmd);\n+\tarm_smmu_cmdq_issue_cmd_with_sync(inv->smmu, &hw_cmd);\n }\n \n /* Should be installed after arm_smmu_install_ste_for_dev() */\n@@ -4823,7 +4826,8 @@ static int arm_smmu_device_reset(struct arm_smmu_device *smmu)\n {\n \tint ret;\n \tu32 reg, enables;\n-\tstruct arm_smmu_cmdq_ent cmd;\n+\tstruct arm_smmu_cmdq_ent ent;\n+\tstruct arm_smmu_cmd cmd;\n \n \t/* Clear CR0 and sync (disables SMMU and queue processing) */\n \treg = readl_relaxed(smmu->base + ARM_SMMU_CR0);\n@@ -4870,16 +4874,19 @@ static int arm_smmu_device_reset(struct arm_smmu_device *smmu)\n \t}\n \n \t/* Invalidate any cached configuration */\n-\tcmd.opcode = CMDQ_OP_CFGI_ALL;\n+\tent.opcode = CMDQ_OP_CFGI_ALL;\n+\tarm_smmu_cmdq_build_cmd(cmd.data, &ent);\n \tarm_smmu_cmdq_issue_cmd_with_sync(smmu, &cmd);\n \n \t/* Invalidate any stale TLB entries */\n \tif (smmu->features & ARM_SMMU_FEAT_HYP) {\n-\t\tcmd.opcode = CMDQ_OP_TLBI_EL2_ALL;\n+\t\tent.opcode = CMDQ_OP_TLBI_EL2_ALL;\n+\t\tarm_smmu_cmdq_build_cmd(cmd.data, &ent);\n \t\tarm_smmu_cmdq_issue_cmd_with_sync(smmu, &cmd);\n \t}\n \n-\tcmd.opcode = CMDQ_OP_TLBI_NSNH_ALL;\n+\tent.opcode = CMDQ_OP_TLBI_NSNH_ALL;\n+\tarm_smmu_cmdq_build_cmd(cmd.data, &ent);\n \tarm_smmu_cmdq_issue_cmd_with_sync(smmu, &cmd);\n \n \t/* Event queue */\n", "prefixes": [ "3/9" ] }