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patch:
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GET /api/1.2/patches/2231891/?format=api
{ "id": 2231891, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2231891/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/patch/1-v1-b7dc0a0d4aa0+3723d-smmu_no_cmdq_ent_jgg@nvidia.com/", "project": { "id": 21, "url": "http://patchwork.ozlabs.org/api/1.2/projects/21/?format=api", "name": "Linux Tegra Development", "link_name": "linux-tegra", "list_id": "linux-tegra.vger.kernel.org", "list_email": "linux-tegra@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1-v1-b7dc0a0d4aa0+3723d-smmu_no_cmdq_ent_jgg@nvidia.com>", "list_archive_url": null, "date": "2026-05-01T14:29:10", "name": "[1/9] iommu/arm-smmu-v3: Add struct arm_smmu_cmd to represent the HW format command", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "2bc7259a75d34bd1a5334c9f45352d7fa3b5f3af", "submitter": { "id": 79424, "url": "http://patchwork.ozlabs.org/api/1.2/people/79424/?format=api", "name": "Jason Gunthorpe", "email": "jgg@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-tegra/patch/1-v1-b7dc0a0d4aa0+3723d-smmu_no_cmdq_ent_jgg@nvidia.com/mbox/", "series": [ { "id": 502465, "url": "http://patchwork.ozlabs.org/api/1.2/series/502465/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/list/?series=502465", "date": "2026-05-01T14:29:09", "name": "Remove SMMUv3 struct arm_smmu_cmdq_ent", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/502465/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2231891/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2231891/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-tegra+bounces-14137-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-tegra@vger.kernel.org" ], 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dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com\n header.b=qtQHefwU; arc=fail smtp.client-ip=52.101.52.21", "i=1; mx.microsoft.com 1; spf=pass\n smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com;\n dkim=pass header.d=nvidia.com; arc=none" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=aljdTmdMqBv3SwOrarPA4TMvl/LqgwdZX70virZqYQ0=;\n b=qtQHefwUcLNWElZaU0w7vogwMvyOUytTd3CF+zQdaDKw7OSPOjcDA4PYyKJYn+qNX0dwKfXpynd14qzvSKl4nyg2w/Z00Bf+/yM59u0ypayTqjrIWoI3KmHD2MQcqfGvIjP/7uGsaRs4MAkAhSU/fYiefgC7+S2DoFQiw2N9xx01evtaJXnStGzvG1eQux4qgRZj6L+/4gSmgIBZchrcFH2gYcArrRYB1FQz2ENXRMKbUeOIrL2FvtsV030T5OR47TW36LMS/TAari3VJcgKsOa+55uPzRni9xUADHSGeS5nbUrmVYy8/NSxWoBq60VbCOZm49X1MJ+9CEPdGt42+g==", "From": "Jason Gunthorpe <jgg@nvidia.com>", "To": "iommu@lists.linux.dev,\n\tJonathan Hunter <jonathanh@nvidia.com>,\n\tJoerg Roedel <joro@8bytes.org>,\n\tlinux-arm-kernel@lists.infradead.org,\n\tlinux-tegra@vger.kernel.org,\n\tRobin Murphy <robin.murphy@arm.com>,\n\tThierry Reding <thierry.reding@kernel.org>,\n\tKrishna Reddy <vdumpa@nvidia.com>,\n\tWill Deacon <will@kernel.org>", "Cc": "David Matlack <dmatlack@google.com>,\n\tPasha Tatashin <pasha.tatashin@soleen.com>,\n\tpatches@lists.linux.dev,\n\tSamiullah Khawaja <skhawaja@google.com>,\n\tMostafa Saleh <smostafa@google.com>", "Subject": "[PATCH 1/9] iommu/arm-smmu-v3: Add struct arm_smmu_cmd to represent\n the HW format command", "Date": "Fri, 1 May 2026 11:29:10 -0300", "Message-ID": "<1-v1-b7dc0a0d4aa0+3723d-smmu_no_cmdq_ent_jgg@nvidia.com>", "In-Reply-To": "<0-v1-b7dc0a0d4aa0+3723d-smmu_no_cmdq_ent_jgg@nvidia.com>", "References": "", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-ClientProxiedBy": "BL1P221CA0024.NAMP221.PROD.OUTLOOK.COM\n (2603:10b6:208:2c5::31) To LV8PR12MB9620.namprd12.prod.outlook.com\n (2603:10b6:408:2a1::19)", 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1YsNkkS/JAHPvpSzL4VVkzp1UjUyTF/RHifZMm1Wayt8MO+bcRoPfUC0xstO71Z2dk1fhy/+1pLmsgbXWa9IT2rT0qWucGJgHbjnBJrmgeBt4Fak7PndaYBeJu9/fH8jI2KYb/+flZUey9zKTYoswXCD1/LjYnqRBCiul60eU0hCfNFXH1yjm8FQkn7mSABMr72n+kdl8NAFhhGi++BOxA9UWPbHCqRgwVVObYssli+5H/wzMDP817/MpsJ/0jX60UZdKYfxGIQni24kdZpMlxNHUzHCuf77kFyCkjb/pRPBp8NPHsUBgAEIVsyZEeQ5IZ2g5B08zruykmli9jIW/BiMNjgnIfVVQ3SXd5f7vnHKj9wKtnRTg+AyVKZEuVvT3b1KuUGeKyBO3nt/xfB60diLgf1Q0o66ZvXQVvjZ4+6SL4RhJuVWfSTqveGLp232IaPMcyyYInQiKAKhmhbpcssBEwZPyh/JJlU+jNp5dEc+ryoRFVf+uy4O244t5O6L93S11k0+v84r0Il6z+pkQYEuSbb6XKxuP+k0VyJFHVxcHQiELshRZbVlaptoov/HOnAtks6hthx2xFhG2tuzQmOScRlesu5CEzkE3gh2g19XR7SCA75i6kSrIzPuxiyaa0osj9zkPwajfZ7W/YIxxLRf5TxBWwvu0ZVolJgLre/6hEcdh/uqvuPZ3mzjAcS3aflvn/GzSpG0YUGnZTwQ1QkM02Ng4zcR3cFR9zGPFCdcNMlgclJOiIVBPXWyqNA8xPYVpMy0ZOqokIpbW7iLY+8kJ+0NuMEkGiNvlk+5sY8OXoWrwvk9FH5ufQ/wgrn9HDZiXrKUGhe0zGKQG35JIWikcsA1o+cUfxs0t4OEcgBFix9rOm1k7Bl3FmQhPD60X5cLfrqgSCFGg+E0y8z4tmjeNSIG+tM+UqVYL+AvBTVHToplzP6tROHfsKVdu/kQhIs4IECBJeo5Kj9M6oSFgpKhR4LsvZwNDzLwOxV8i6l+2Nt/QV3oymZORfvK53z0jYVMxysoBhsNaqGiteJNow1AU9nN506OnFub9SrCGGwDTva2trRUnuj4NJ+9ZH9gS/+X7mWEpA1OtMl3g7hl3vxCOSf0LfsuppkoVIKMpMF1RWQiY7v/UxKsEjUhiKd32F7fsO4No+DdpqH1sgJNjleF/BLdvzn2KUn+Mm0CBQyijVsIfQE1LU2px5opcHIOHIYEvxv+v9LCt+Np3KnCSxLwRwgXGji6tH8NUb3dgRcfdrArUTazsLhS9MxloTjUOtWzyth7tRoOJ/zeJyTUAfS8W84/uPr3Z5O6P1rhRn62L6QLbuxgqTcCRNzckQbp6jeN34sPt3oNJQNqWHbDB1TGL2zSpoWIXaBYvI7BuSCRBq7pYMdYRM14zv/Lxv/DMPIfIF4tIwJp/UknluBtje81kSnurujLkvn1XA6Hg0RQZasTy5wLw1qaFsMfC0BYLK8SxPOfH1iVxQjAcLzdO0SLOwolzNZd5RsdE71f5R8QEwbf2yI8tgxhP2hqO3PTzxj4tNfBnHh8bhyRkl3RN/o2O+M7u5CQ4tcrcUolRwr8IrYpAKhKdL9nwZz/NVZxDzBI/ireRIFtT7pIk+LVRkXF9DKIobYnEYd+MlvO2YY1I0Y+j2gH/EZ1K42+hnPhm/LZoiuHOnqJLTKdo/LGYwrqOydWBqVsS7SkuMmRmrnNBPqmLs48ocZD4q18gLex", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 731384a9-9a99-4172-173f-08dea78e0860", "X-MS-Exchange-CrossTenant-AuthSource": "LV8PR12MB9620.namprd12.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Internal", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "01 May 2026 14:29:20.4872\n (UTC)", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-MailboxType": "HOSTED", "X-MS-Exchange-CrossTenant-UserPrincipalName": "\n UUmyuPTCKW501r5jmi1hfvXErH019qf2369QuXhNzwlec2Yd83sBjRpobQmS5AyG", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "SA1PR12MB8096" }, "content": "Like STE/CD, add a wrapper struct around the u64 array to represent the\nalready FIELD_PREP'd command data. Unlike the STE/CD this is a u64\nbecause the command submission path will have the swap to le64.\n\nThis makes the API clearer when a u64 is referring to a formatted\ncommand and makes the following changes easier to follow.\n\nMove the command constants out of the struct and into an enum alongside\nthe rest of the constants defining the HW format so the entire HW format\nis self contained and independent of struct arm_smmu_cmdq_ent.\n\nSigned-off-by: Jason Gunthorpe <jgg@nvidia.com>\n---\n drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 48 ++++++++++++---------\n 1 file changed, 28 insertions(+), 20 deletions(-)", "diff": "diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h\nindex ef42df4753ec4d..092179f689e9f1 100644\n--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h\n+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h\n@@ -390,6 +390,10 @@ static inline unsigned int arm_smmu_cdtab_l2_idx(unsigned int ssid)\n \n #define CMDQ_PROD_OWNED_FLAG\t\tQ_OVERFLOW_FLAG\n \n+struct arm_smmu_cmd {\n+\tu64 data[CMDQ_ENT_DWORDS];\n+};\n+\n /*\n * This is used to size the command queue and therefore must be at least\n * BITS_PER_LONG so that the valid_map works correctly (it relies on the\n@@ -426,6 +430,8 @@ static inline unsigned int arm_smmu_cdtab_l2_idx(unsigned int ssid)\n #define CMDQ_ATC_1_SIZE\t\t\tGENMASK_ULL(5, 0)\n #define CMDQ_ATC_1_ADDR_MASK\t\tGENMASK_ULL(63, 12)\n \n+#define ATC_INV_SIZE_ALL 52\n+\n #define CMDQ_PRI_0_SSID\t\t\tGENMASK_ULL(31, 12)\n #define CMDQ_PRI_0_SID\t\t\tGENMASK_ULL(63, 32)\n #define CMDQ_PRI_1_GRPID\t\tGENMASK_ULL(8, 0)\n@@ -447,6 +453,28 @@ static inline unsigned int arm_smmu_cdtab_l2_idx(unsigned int ssid)\n #define CMDQ_SYNC_0_MSIDATA\t\tGENMASK_ULL(63, 32)\n #define CMDQ_SYNC_1_MSIADDR_MASK\tGENMASK_ULL(51, 2)\n \n+enum arm_smmu_cmdq_opcode {\n+\tCMDQ_OP_PREFETCH_CFG = 0x1,\n+\tCMDQ_OP_CFGI_STE = 0x3,\n+\tCMDQ_OP_CFGI_ALL = 0x4,\n+\tCMDQ_OP_CFGI_CD = 0x5,\n+\tCMDQ_OP_CFGI_CD_ALL = 0x6,\n+\tCMDQ_OP_TLBI_NH_ALL = 0x10,\n+\tCMDQ_OP_TLBI_NH_ASID = 0x11,\n+\tCMDQ_OP_TLBI_NH_VA = 0x12,\n+\tCMDQ_OP_TLBI_NH_VAA = 0x13,\n+\tCMDQ_OP_TLBI_EL2_ALL = 0x20,\n+\tCMDQ_OP_TLBI_EL2_ASID = 0x21,\n+\tCMDQ_OP_TLBI_EL2_VA = 0x22,\n+\tCMDQ_OP_TLBI_S12_VMALL = 0x28,\n+\tCMDQ_OP_TLBI_S2_IPA = 0x2a,\n+\tCMDQ_OP_TLBI_NSNH_ALL = 0x30,\n+\tCMDQ_OP_ATC_INV = 0x40,\n+\tCMDQ_OP_PRI_RESP = 0x41,\n+\tCMDQ_OP_RESUME = 0x44,\n+\tCMDQ_OP_CMD_SYNC = 0x46,\n+};\n+\n /* Event queue */\n #define EVTQ_ENT_SZ_SHIFT\t\t5\n #define EVTQ_ENT_DWORDS\t\t\t((1 << EVTQ_ENT_SZ_SHIFT) >> 3)\n@@ -520,15 +548,10 @@ struct arm_smmu_cmdq_ent {\n \n \t/* Command-specific fields */\n \tunion {\n-\t\t#define CMDQ_OP_PREFETCH_CFG\t0x1\n \t\tstruct {\n \t\t\tu32\t\t\tsid;\n \t\t} prefetch;\n \n-\t\t#define CMDQ_OP_CFGI_STE\t0x3\n-\t\t#define CMDQ_OP_CFGI_ALL\t0x4\n-\t\t#define CMDQ_OP_CFGI_CD\t\t0x5\n-\t\t#define CMDQ_OP_CFGI_CD_ALL\t0x6\n \t\tstruct {\n \t\t\tu32\t\t\tsid;\n \t\t\tu32\t\t\tssid;\n@@ -538,16 +561,6 @@ struct arm_smmu_cmdq_ent {\n \t\t\t};\n \t\t} cfgi;\n \n-\t\t#define CMDQ_OP_TLBI_NH_ALL 0x10\n-\t\t#define CMDQ_OP_TLBI_NH_ASID\t0x11\n-\t\t#define CMDQ_OP_TLBI_NH_VA\t0x12\n-\t\t#define CMDQ_OP_TLBI_NH_VAA\t0x13\n-\t\t#define CMDQ_OP_TLBI_EL2_ALL\t0x20\n-\t\t#define CMDQ_OP_TLBI_EL2_ASID\t0x21\n-\t\t#define CMDQ_OP_TLBI_EL2_VA\t0x22\n-\t\t#define CMDQ_OP_TLBI_S12_VMALL\t0x28\n-\t\t#define CMDQ_OP_TLBI_S2_IPA\t0x2a\n-\t\t#define CMDQ_OP_TLBI_NSNH_ALL\t0x30\n \t\tstruct {\n \t\t\tu8\t\t\tnum;\n \t\t\tu8\t\t\tscale;\n@@ -559,8 +572,6 @@ struct arm_smmu_cmdq_ent {\n \t\t\tu64\t\t\taddr;\n \t\t} tlbi;\n \n-\t\t#define CMDQ_OP_ATC_INV\t\t0x40\n-\t\t#define ATC_INV_SIZE_ALL\t52\n \t\tstruct {\n \t\t\tu32\t\t\tsid;\n \t\t\tu32\t\t\tssid;\n@@ -569,7 +580,6 @@ struct arm_smmu_cmdq_ent {\n \t\t\tbool\t\t\tglobal;\n \t\t} atc;\n \n-\t\t#define CMDQ_OP_PRI_RESP\t0x41\n \t\tstruct {\n \t\t\tu32\t\t\tsid;\n \t\t\tu32\t\t\tssid;\n@@ -577,14 +587,12 @@ struct arm_smmu_cmdq_ent {\n \t\t\tenum pri_resp\t\tresp;\n \t\t} pri;\n \n-\t\t#define CMDQ_OP_RESUME\t\t0x44\n \t\tstruct {\n \t\t\tu32\t\t\tsid;\n \t\t\tu16\t\t\tstag;\n \t\t\tu8\t\t\tresp;\n \t\t} resume;\n \n-\t\t#define CMDQ_OP_CMD_SYNC\t0x46\n \t\tstruct {\n \t\t\tu64\t\t\tmsiaddr;\n \t\t} sync;\n", "prefixes": [ "1/9" ] }