Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/1.2/patches/2231886/?format=api
{ "id": 2231886, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2231886/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/patch/2-v1-b7dc0a0d4aa0+3723d-smmu_no_cmdq_ent_jgg@nvidia.com/", "project": { "id": 21, "url": "http://patchwork.ozlabs.org/api/1.2/projects/21/?format=api", "name": "Linux Tegra Development", "link_name": "linux-tegra", "list_id": "linux-tegra.vger.kernel.org", "list_email": "linux-tegra@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<2-v1-b7dc0a0d4aa0+3723d-smmu_no_cmdq_ent_jgg@nvidia.com>", "list_archive_url": null, "date": "2026-05-01T14:29:11", "name": "[2/9] iommu/arm-smmu-v3: Use the HW arm_smmu_cmd in cmdq selection functions", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "532b8cba142a6129a47aebce628524de68d182a1", "submitter": { "id": 79424, "url": "http://patchwork.ozlabs.org/api/1.2/people/79424/?format=api", "name": "Jason Gunthorpe", "email": "jgg@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-tegra/patch/2-v1-b7dc0a0d4aa0+3723d-smmu_no_cmdq_ent_jgg@nvidia.com/mbox/", "series": [ { "id": 502465, "url": "http://patchwork.ozlabs.org/api/1.2/series/502465/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/list/?series=502465", "date": "2026-05-01T14:29:09", "name": "Remove SMMUv3 struct arm_smmu_cmdq_ent", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/502465/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2231886/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2231886/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-tegra+bounces-14134-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-tegra@vger.kernel.org" ], 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dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com\n header.b=FyiVBIrS; arc=fail smtp.client-ip=52.101.52.21", "i=1; mx.microsoft.com 1; spf=pass\n smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com;\n dkim=pass header.d=nvidia.com; arc=none" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=n1uhfAmuA8YY+eLYAKMut3jF20w/vgKNBzm/D/EpeDU=;\n b=FyiVBIrSnpBq4OIUOqsWemzbaXIcr5e1JzLPsukc+IBM3zVX9iav7s9Zw4Z0V/2J5gHI8uKVkjIM8JuwAaJAcPbK4BU2DWtU5WOuqtduZlklNI1kqDnIQg/Fr7erkIePM6f7llppQ/nR053F+pwoPWYZfF0BlLjVavTxEBSVlO/+rmsm3hmayV5RPWRjGz7OYgkBv9S1vFVS3/rsyhd7PJUwMMgk5MdePBNgPdjkRA78pRhdpJOB6ANvYiq+ooJNC/YdWzy+ta3GL3cPHbI3JZ6daBx04jiiUVoSWcKNwTZCpWUHu+6zY+PItbMyHDzlcHPYKDGtgzX7tY0/89lWyw==", "From": "Jason Gunthorpe <jgg@nvidia.com>", "To": "iommu@lists.linux.dev,\n\tJonathan Hunter <jonathanh@nvidia.com>,\n\tJoerg Roedel <joro@8bytes.org>,\n\tlinux-arm-kernel@lists.infradead.org,\n\tlinux-tegra@vger.kernel.org,\n\tRobin Murphy <robin.murphy@arm.com>,\n\tThierry Reding <thierry.reding@kernel.org>,\n\tKrishna Reddy <vdumpa@nvidia.com>,\n\tWill Deacon <will@kernel.org>", "Cc": "David Matlack <dmatlack@google.com>,\n\tPasha Tatashin <pasha.tatashin@soleen.com>,\n\tpatches@lists.linux.dev,\n\tSamiullah Khawaja <skhawaja@google.com>,\n\tMostafa Saleh <smostafa@google.com>", "Subject": "[PATCH 2/9] iommu/arm-smmu-v3: Use the HW arm_smmu_cmd in cmdq\n selection functions", "Date": "Fri, 1 May 2026 11:29:11 -0300", "Message-ID": "<2-v1-b7dc0a0d4aa0+3723d-smmu_no_cmdq_ent_jgg@nvidia.com>", "In-Reply-To": "<0-v1-b7dc0a0d4aa0+3723d-smmu_no_cmdq_ent_jgg@nvidia.com>", "References": "", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-ClientProxiedBy": "BL1P221CA0004.NAMP221.PROD.OUTLOOK.COM\n (2603:10b6:208:2c5::15) To LV8PR12MB9620.namprd12.prod.outlook.com\n (2603:10b6:408:2a1::19)", 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VCxv9iCTEKmj492Klh5MF4xsvPt3yPQBM5hhFgyMKGxNmsi7wHFol1lnbpRV0JazwXXA2sPq5b/YimEDqXsZ7nkLCxz58ONb8sWXLMqavol8RFOORKAPRC2g76axBYKPABbZXLgQDqJ0fIvXiktb8N1zNlamAv9EkbZsQD2BBhNdWlroscLKCKzsS/Gcv5UElh8wXh3FijNpLeFitSR22O8IcSOkTN1tfTJqox6k6FQOESyEX9B7TH+Nph1+NPiAH1ylqhHEs/V8xmbCVHUq3BvXUKvSceisnNo14lWfkqxRA1W99jAK/h1iZwjDwWhWKenvs8QaL1tQGsV+Zrdm2CJjtk9vrULgXCuOvxtfof4brogZeHUT8jv3s9Wq6Bre5onLyRpkdynXKlSrK9X74WyoUlPeXCggl6Li0daebhy8dLC79rU9IWBikF0td4AWrmJbnhDMcrBCJI/fQIku7Vus45wrJ4CnlW/159+OcbOv/WhzqIzjXcIAnIBsRuhoJ3mOYSIs6QVLvhJz2vh9iboykw5ULK3fDsdpQFSXzvwX78k6RC/hg7cgkyW05JYq7KZF+tcslyUDG4vP9WipHiEV4act1hJibyE2plpnK6u0kNjRxhoXVDVlCRIx7Z09kVbd7Y5Pfo3H0ge2rGSNUZjO5dK1mRTS1VA8id+OA4hShEAfXCqyodRrxqdVvQrqWUHD04s1WojueGhR++m7mHnb1YyTrApLfcD0pcUCK/WdJ+MR9jl+G+iPlsadboPudIZOZ4LEuSD2iGCLCYNeu1Ll9DC0E+P2z9A0BEYmR+j1obZ9dFLrkKNwTzK0I8VT89bE7RZHjRNvoPTDZMnHD7saW1abIb9xpu+wK85P/1fw42uvcH5ht3xS11iNBD5T57f8d7lwNao6OKXUWZnjnhvM9UqRxBif9HB02aoIcrtwm0yoUii62Q9Ae/3mG1kJWAWlUeWx19xBJi2MlAoaZDyXaNxNaQ75rjZ7/BmLG4cR0aAcqIRIeqYftJGRC8OP4atR5QY9CkMm5vS3uvGA9suTaiNXXICg1jVUnBZKh2ZdgppS7Wyuq2hBBZwhHr0FhV2aeyS2w4dHoPMQ+oZETVe2LkFuJML9oI00Ah1HQ7L2xLd1EPgUDHLZc0O5/hUNmbsBwe4ISqUJ/Q2QcwcOLzUlwLhNc7f2AzitZE6eQuCKnyNuKpG/cRYnUWlSQBcDVVBvDAXPJesXv7jjvvfmEwbo24k2XPMozminZNtywVJ3Lis8YBXFT7kVVhws1nuyObhIhL7FYA7R5UZ9Eek68FOV3JdnlgWvfxMvjg6gns5xSVflpXDFHWEXfbeOyPGWUxlWNNRJigLHfiWTqSXZEiiqJ1rhWfJHVreIy8eG0ML18aPPm1fx/fGx08HAcTd2tBhhrLM+EnrfWtBJp7GqrQhiM4+hmmJOPl6hop2cBeMi53yPoQ3TJj1we3hDB/8OnrdxOeQAiobmFuEtzZMVuCy9HuerAicyd2xaHw1yxsPog5OzvvBBsgGQw3+A6FYV+asYbr64XdWHdyhy7pbE4SsqL2P9yVqNxMgRfUma9wh4zlpx673wPwSbufQPqPDdh1F4CcNMgoKk8FRqQ6P5vmdPuWYyZqOZ5aadPVls/LqRxFa51S5VXKWAJUagPCPbNpvUnsz1H0NVXACn2FYDo03Dy8mvC15ljsaZNjDnhPJc7rYeKldKDF+ZV53ckcSa", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 1312e880-e10a-46af-94b1-08dea78e0851", "X-MS-Exchange-CrossTenant-AuthSource": "LV8PR12MB9620.namprd12.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Internal", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "01 May 2026 14:29:20.3273\n (UTC)", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-MailboxType": "HOSTED", "X-MS-Exchange-CrossTenant-UserPrincipalName": "\n qtZBMOn7nGLGimjH0DGdQKdtbYtA1/upod8Y4IUzJn9LAplXSiasRHuovFww7jDy", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "SA1PR12MB8096" }, "content": "Start removing the use of struct arm_smmu_cmdq_ent, starting at the\nlower levels of the call chain. Change the functions that determine what\ncmdq to issue the batch to into using struct arm_smmu_cmd directly.\n\nSigned-off-by: Jason Gunthorpe <jgg@nvidia.com>\n---\n drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 47 ++++++++++++-------\n drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 8 ++--\n .../iommu/arm/arm-smmu-v3/tegra241-cmdqv.c | 8 ++--\n 3 files changed, 38 insertions(+), 25 deletions(-)", "diff": "diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c\nindex e8d7dbe495f030..5cdeaec890592f 100644\n--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c\n+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c\n@@ -371,12 +371,12 @@ static int arm_smmu_cmdq_build_cmd(u64 *cmd, struct arm_smmu_cmdq_ent *ent)\n }\n \n static struct arm_smmu_cmdq *arm_smmu_get_cmdq(struct arm_smmu_device *smmu,\n-\t\t\t\t\t struct arm_smmu_cmdq_ent *ent)\n+\t\t\t\t\t struct arm_smmu_cmd *cmd)\n {\n \tstruct arm_smmu_cmdq *cmdq = NULL;\n \n \tif (smmu->impl_ops && smmu->impl_ops->get_secondary_cmdq)\n-\t\tcmdq = smmu->impl_ops->get_secondary_cmdq(smmu, ent);\n+\t\tcmdq = smmu->impl_ops->get_secondary_cmdq(smmu, cmd);\n \n \treturn cmdq ?: &smmu->cmdq;\n }\n@@ -924,16 +924,16 @@ static int __arm_smmu_cmdq_issue_cmd(struct arm_smmu_device *smmu,\n \t\t\t\t struct arm_smmu_cmdq_ent *ent,\n \t\t\t\t bool sync)\n {\n-\tu64 cmd[CMDQ_ENT_DWORDS];\n+\tstruct arm_smmu_cmd cmd;\n \n-\tif (unlikely(arm_smmu_cmdq_build_cmd(cmd, ent))) {\n+\tif (unlikely(arm_smmu_cmdq_build_cmd(cmd.data, ent))) {\n \t\tdev_warn(smmu->dev, \"ignoring unknown CMDQ opcode 0x%x\\n\",\n \t\t\t ent->opcode);\n \t\treturn -EINVAL;\n \t}\n \n \treturn arm_smmu_cmdq_issue_cmdlist(\n-\t\tsmmu, arm_smmu_get_cmdq(smmu, ent), cmd, 1, sync);\n+\t\tsmmu, arm_smmu_get_cmdq(smmu, &cmd), cmd.data, 1, sync);\n }\n \n static int arm_smmu_cmdq_issue_cmd(struct arm_smmu_device *smmu,\n@@ -948,42 +948,55 @@ static int arm_smmu_cmdq_issue_cmd_with_sync(struct arm_smmu_device *smmu,\n \treturn __arm_smmu_cmdq_issue_cmd(smmu, ent, true);\n }\n \n+static void arm_smmu_cmdq_batch_init_cmd(struct arm_smmu_device *smmu,\n+\t\t\t\t\t struct arm_smmu_cmdq_batch *cmds,\n+\t\t\t\t\t struct arm_smmu_cmd *cmd)\n+{\n+\tcmds->num = 0;\n+\tcmds->cmdq = arm_smmu_get_cmdq(smmu, cmd);\n+}\n+\n static void arm_smmu_cmdq_batch_init(struct arm_smmu_device *smmu,\n \t\t\t\t struct arm_smmu_cmdq_batch *cmds,\n \t\t\t\t struct arm_smmu_cmdq_ent *ent)\n {\n-\tcmds->num = 0;\n-\tcmds->cmdq = arm_smmu_get_cmdq(smmu, ent);\n+\tstruct arm_smmu_cmd cmd;\n+\n+\tarm_smmu_cmdq_build_cmd(cmd.data, ent);\n+\tarm_smmu_cmdq_batch_init_cmd(smmu, cmds, &cmd);\n }\n \n static void arm_smmu_cmdq_batch_add(struct arm_smmu_device *smmu,\n \t\t\t\t struct arm_smmu_cmdq_batch *cmds,\n-\t\t\t\t struct arm_smmu_cmdq_ent *cmd)\n+\t\t\t\t struct arm_smmu_cmdq_ent *ent)\n {\n-\tbool unsupported_cmd = !arm_smmu_cmdq_supports_cmd(cmds->cmdq, cmd);\n \tbool force_sync = (cmds->num == CMDQ_BATCH_ENTRIES - 1) &&\n \t\t\t (smmu->options & ARM_SMMU_OPT_CMDQ_FORCE_SYNC);\n+\tstruct arm_smmu_cmd cmd;\n+\tbool unsupported_cmd;\n \tint index;\n \n+\tif (unlikely(arm_smmu_cmdq_build_cmd(cmd.data, ent))) {\n+\t\tdev_warn(smmu->dev, \"ignoring unknown CMDQ opcode 0x%x\\n\",\n+\t\t\t ent->opcode);\n+\t\treturn;\n+\t}\n+\n+\tunsupported_cmd = !arm_smmu_cmdq_supports_cmd(cmds->cmdq, &cmd);\n \tif (force_sync || unsupported_cmd) {\n \t\tarm_smmu_cmdq_issue_cmdlist(smmu, cmds->cmdq, cmds->cmds,\n \t\t\t\t\t cmds->num, true);\n-\t\tarm_smmu_cmdq_batch_init(smmu, cmds, cmd);\n+\t\tarm_smmu_cmdq_batch_init_cmd(smmu, cmds, &cmd);\n \t}\n \n \tif (cmds->num == CMDQ_BATCH_ENTRIES) {\n \t\tarm_smmu_cmdq_issue_cmdlist(smmu, cmds->cmdq, cmds->cmds,\n \t\t\t\t\t cmds->num, false);\n-\t\tarm_smmu_cmdq_batch_init(smmu, cmds, cmd);\n+\t\tarm_smmu_cmdq_batch_init_cmd(smmu, cmds, &cmd);\n \t}\n \n \tindex = cmds->num * CMDQ_ENT_DWORDS;\n-\tif (unlikely(arm_smmu_cmdq_build_cmd(&cmds->cmds[index], cmd))) {\n-\t\tdev_warn(smmu->dev, \"ignoring unknown CMDQ opcode 0x%x\\n\",\n-\t\t\t cmd->opcode);\n-\t\treturn;\n-\t}\n-\n+\tmemcpy(&cmds->cmds[index], cmd.data, sizeof(cmd.data));\n \tcmds->num++;\n }\n \ndiff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h\nindex 092179f689e9f1..6d73f6b63e64a9 100644\n--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h\n+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h\n@@ -641,13 +641,13 @@ struct arm_smmu_cmdq {\n \tatomic_long_t\t\t\t*valid_map;\n \tatomic_t\t\t\towner_prod;\n \tatomic_t\t\t\tlock;\n-\tbool\t\t\t\t(*supports_cmd)(struct arm_smmu_cmdq_ent *ent);\n+\tbool\t\t\t\t(*supports_cmd)(struct arm_smmu_cmd *cmd);\n };\n \n static inline bool arm_smmu_cmdq_supports_cmd(struct arm_smmu_cmdq *cmdq,\n-\t\t\t\t\t struct arm_smmu_cmdq_ent *ent)\n+\t\t\t\t\t struct arm_smmu_cmd *cmd)\n {\n-\treturn cmdq->supports_cmd ? cmdq->supports_cmd(ent) : true;\n+\treturn cmdq->supports_cmd ? cmdq->supports_cmd(cmd) : true;\n }\n \n struct arm_smmu_cmdq_batch {\n@@ -815,7 +815,7 @@ struct arm_smmu_impl_ops {\n \tvoid (*device_remove)(struct arm_smmu_device *smmu);\n \tint (*init_structures)(struct arm_smmu_device *smmu);\n \tstruct arm_smmu_cmdq *(*get_secondary_cmdq)(\n-\t\tstruct arm_smmu_device *smmu, struct arm_smmu_cmdq_ent *ent);\n+\t\tstruct arm_smmu_device *smmu, struct arm_smmu_cmd *cmd);\n \t/*\n \t * An implementation should define its own type other than the default\n \t * IOMMU_HW_INFO_TYPE_ARM_SMMUV3. And it must validate the input @type\ndiff --git a/drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c b/drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c\nindex 83f6e9f6c51d6b..b4d8c1f2fd3878 100644\n--- a/drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c\n+++ b/drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c\n@@ -367,9 +367,9 @@ static irqreturn_t tegra241_cmdqv_isr(int irq, void *devid)\n \n /* Command Queue Function */\n \n-static bool tegra241_guest_vcmdq_supports_cmd(struct arm_smmu_cmdq_ent *ent)\n+static bool tegra241_guest_vcmdq_supports_cmd(struct arm_smmu_cmd *cmd)\n {\n-\tswitch (ent->opcode) {\n+\tswitch (FIELD_GET(CMDQ_0_OP, cmd->data[0])) {\n \tcase CMDQ_OP_TLBI_NH_ASID:\n \tcase CMDQ_OP_TLBI_NH_VA:\n \tcase CMDQ_OP_ATC_INV:\n@@ -381,7 +381,7 @@ static bool tegra241_guest_vcmdq_supports_cmd(struct arm_smmu_cmdq_ent *ent)\n \n static struct arm_smmu_cmdq *\n tegra241_cmdqv_get_cmdq(struct arm_smmu_device *smmu,\n-\t\t\tstruct arm_smmu_cmdq_ent *ent)\n+\t\t\tstruct arm_smmu_cmd *cmd)\n {\n \tstruct tegra241_cmdqv *cmdqv =\n \t\tcontainer_of(smmu, struct tegra241_cmdqv, smmu);\n@@ -409,7 +409,7 @@ tegra241_cmdqv_get_cmdq(struct arm_smmu_device *smmu,\n \t\treturn NULL;\n \n \t/* Unsupported CMD goes for smmu->cmdq pathway */\n-\tif (!arm_smmu_cmdq_supports_cmd(&vcmdq->cmdq, ent))\n+\tif (!arm_smmu_cmdq_supports_cmd(&vcmdq->cmdq, cmd))\n \t\treturn NULL;\n \treturn &vcmdq->cmdq;\n }\n", "prefixes": [ "2/9" ] }