Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/1.2/patches/2231287/?format=api
{ "id": 2231287, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2231287/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20260430135838.3438728-2-andre.przywara@arm.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/1.2/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260430135838.3438728-2-andre.przywara@arm.com>", "list_archive_url": null, "date": "2026-04-30T13:58:37", "name": "[v2,1/2] sunxi: A523: Move NSI init routine into generic function", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "0c4b2222944f4601cd7a8747b70f81896c4bdad0", "submitter": { "id": 61837, "url": "http://patchwork.ozlabs.org/api/1.2/people/61837/?format=api", "name": "Andre Przywara", "email": "andre.przywara@arm.com" }, "delegate": { "id": 114289, "url": "http://patchwork.ozlabs.org/api/1.2/users/114289/?format=api", "username": "apritzel", "first_name": "Andre", "last_name": "Przywara", "email": "andre.przywara@arm.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20260430135838.3438728-2-andre.przywara@arm.com/mbox/", "series": [ { "id": 502307, "url": "http://patchwork.ozlabs.org/api/1.2/series/502307/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=502307", "date": "2026-04-30T13:58:36", "name": "sunxi: DRAM: rework NSI priority settings", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/502307/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2231287/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2231287/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n unprotected) header.d=arm.com header.i=@arm.com header.a=rsa-sha256\n header.s=foss header.b=mSmgcfT2;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=85.214.62.61; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org)", "phobos.denx.de;\n dmarc=fail (p=none dis=none) header.from=arm.com", "phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de", "phobos.denx.de;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n unprotected) header.d=arm.com header.i=@arm.com header.b=\"mSmgcfT2\";\n\tdkim-atps=neutral", "phobos.denx.de;\n dmarc=pass (p=none dis=none) header.from=arm.com", "phobos.denx.de;\n spf=pass smtp.mailfrom=andre.przywara@arm.com" ], "Received": [ "from phobos.denx.de (phobos.denx.de [85.214.62.61])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g5wkr1FWfz1yHZ\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 30 Apr 2026 23:59:00 +1000 (AEST)", "from h2850616.stratoserver.net (localhost [IPv6:::1])\n\tby phobos.denx.de (Postfix) with ESMTP id B628980433;\n\tThu, 30 Apr 2026 15:58:50 +0200 (CEST)", "by phobos.denx.de (Postfix, from userid 109)\n id B37C384099; Thu, 30 Apr 2026 15:58:48 +0200 (CEST)", "from foss.arm.com (foss.arm.com [217.140.110.172])\n by phobos.denx.de (Postfix) with ESMTP id 0C0718063E\n for <u-boot@lists.denx.de>; Thu, 30 Apr 2026 15:58:46 +0200 (CEST)", "from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14])\n by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id DD3CD2BC6;\n Thu, 30 Apr 2026 06:58:39 -0700 (PDT)", "from e142021.fritz.box (usa-sjc-mx-foss1.foss.arm.com\n [172.31.20.19])\n by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 420B73F7B4;\n Thu, 30 Apr 2026 06:58:44 -0700 (PDT)" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED,\n DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED,\n SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.2", "DKIM-Signature": "v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss;\n t=1777557525; bh=MutLqy9KZffmQ7ohGHiXKCRGLj2Fjx+hy8pXMXys4bs=;\n h=From:To:Cc:Subject:Date:In-Reply-To:References:From;\n b=mSmgcfT20ZIleBlrXS11zki6jkzXXqB89CO6qfp02QJ09G9a/b++lMKXC2Bf+9WpU\n XOaVNfFxq3u7jg+K2xpdfIvCKdWfg7GpQ9jmMxYuAZ0ae4eg94sIrc4OKVyPR2NvJj\n v0dc77gY4Z4iuljMLDZTsYs9J4cX9qk54eoG6mmw=", "From": "Andre Przywara <andre.przywara@arm.com>", "To": "Paul Kocialkowski <paulk@sys-base.io>,\n\tu-boot@lists.denx.de", "Cc": "Jernej Skrabec <jernej.skrabec@gmail.com>, Chen-Yu Tsai <wens@kernel.org>,\n linux-sunxi@lists.linux.dev", "Subject": "[PATCH v2 1/2] sunxi: A523: Move NSI init routine into generic\n function", "Date": "Thu, 30 Apr 2026 15:58:37 +0200", "Message-ID": "<20260430135838.3438728-2-andre.przywara@arm.com>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260430135838.3438728-1-andre.przywara@arm.com>", "References": "<20260430135838.3438728-1-andre.przywara@arm.com>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.39", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.103.8 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "In previous generations of Allwinner SoCs, the memory bus (MBUS) access\narbitration was configured as part of the DRAM top registers. This is no\nlonger the case with for instance the A133 or A523, which have a dedicated\nbase address for the bus arbiter that is now called NSI instead of MBUS.\n\nNSI appears to be a later iteration of MBUS design, with new dedicated\nregisters that resemble the previous MBUS ones. Despite NSI not being\ndocumented in the manual, the A133 BSP includes a nsi driver with some\ndescription of the registers. Like previous generations, it implements\nport arbitration priority for DRAM access and also supports an optional\nQoS mode based on bandwidth limits.\n\nIn preparation for re-using code for other SoCs, factor out the existing\nNSI init routine from the A523 DRAM code, which was a bit ad-hoc and A523\nspecific, into a separate function, and abstract the settings a bit.\nNo functional change.\n\nSigned-off-by: Andre Przywara <andre.przywara@arm.com>\nCo-develeoped-by: Paul Kocialkowski <paulk@sys-base.io>\nSuggested-by: Jernej Škrabec <jernej.skrabec@gmail.com>\nSponsored-by: MEC Electronics GmbH <https://www.mec.at/>\n---\n .../include/asm/arch-sunxi/cpu_sunxi_ncat2.h | 1 +\n .../include/asm/arch-sunxi/dram_sun55i_a523.h | 29 +++++++++++\n arch/arm/include/asm/arch-sunxi/sunxi_nsi.h | 25 ++++++++++\n arch/arm/mach-sunxi/Makefile | 2 +-\n arch/arm/mach-sunxi/dram_sun55i_a523.c | 49 +++++++++----------\n arch/arm/mach-sunxi/sunxi_nsi.c | 31 ++++++++++++\n 6 files changed, 110 insertions(+), 27 deletions(-)\n create mode 100644 arch/arm/include/asm/arch-sunxi/sunxi_nsi.h\n create mode 100644 arch/arm/mach-sunxi/sunxi_nsi.c", "diff": "diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sunxi_ncat2.h b/arch/arm/include/asm/arch-sunxi/cpu_sunxi_ncat2.h\nindex 7cee7efe8b4..fd7d9b22058 100644\n--- a/arch/arm/include/asm/arch-sunxi/cpu_sunxi_ncat2.h\n+++ b/arch/arm/include/asm/arch-sunxi/cpu_sunxi_ncat2.h\n@@ -9,6 +9,7 @@\n \n #define SUNXI_TZPC_BASE\t\t\t0x02000800\n #define SUNXI_CCM_BASE\t\t\t0x02001000\n+#define SUNXI_NSI_BASE\t\t\t0x02020000\n #define SUNXI_TIMER_BASE\t\t0x02050000\n \n #define SUNXI_TWI0_BASE\t\t\t0x02502000\ndiff --git a/arch/arm/include/asm/arch-sunxi/dram_sun55i_a523.h b/arch/arm/include/asm/arch-sunxi/dram_sun55i_a523.h\nindex 08bfe462856..462d4726a21 100644\n--- a/arch/arm/include/asm/arch-sunxi/dram_sun55i_a523.h\n+++ b/arch/arm/include/asm/arch-sunxi/dram_sun55i_a523.h\n@@ -20,6 +20,35 @@ enum sunxi_dram_type {\n #define MCTL_COM_UNK_008 0x008\n #define MCTL_COM_MAER0 0x020\n \n+enum sunxi_nsi_port {\n+\tSUNXI_NSI_PORT_GPU = 0,\n+\tSUNXI_NSI_PORT_GIC,\t= 1,\n+\tSUNXI_NSI_PORT_USB3,\t= 2,\n+\tSUNXI_NSI_PORT_PCIE,\t= 3,\n+\tSUNXI_NSI_PORT_CE,\t= 4,\n+\tSUNXI_NSI_PORT_NPU,\t= 5,\n+\tSUNXI_NSI_PORT_ISP,\t= 6,\n+\tSUNXI_NSI_PORT_DSP,\t= 7,\n+\tSUNXI_NSI_PORT_G2D,\t= 8,\n+\tSUNXI_NSI_PORT_DI,\t= 9,\n+\tSUNXI_NSI_PORT_IOMMU,\t= 10,\n+\tSUNXI_NSI_PORT_VE_R,\t= 11,\n+\tSUNXI_NSI_PORT_VE_RW,\t= 12,\n+\tSUNXI_NSI_PORT_DE,\t= 13,\n+\tSUNXI_NSI_PORT_CSI,\t= 14,\n+\tSUNXI_NSI_PORT_GMAC0,\t= 18,\n+\tSUNXI_NSI_PORT_GMAC1,\t= 19,\n+\tSUNXI_NSI_PORT_MMC0,\t= 20,\n+\tSUNXI_NSI_PORT_MMC1,\t= 21,\n+\tSUNXI_NSI_PORT_MMC2,\t= 22,\n+\tSUNXI_NSI_PORT_USB0,\t= 23,\n+\tSUNXI_NSI_PORT_USB1,\t= 24,\n+\tSUNXI_NSI_PORT_USB2,\t= 25,\n+\tSUNXI_NSI_PORT_NPD,\t= 26,\n+\tSUNXI_NSI_PORT_DMAC,\t= 27,\n+\tSUNXI_NSI_PORT_DMA,\t= 28,\n+};\n+\n /*\n * Controller registers seems to be the same or at least very similar\n * to those in H6.\ndiff --git a/arch/arm/include/asm/arch-sunxi/sunxi_nsi.h b/arch/arm/include/asm/arch-sunxi/sunxi_nsi.h\nnew file mode 100644\nindex 00000000000..7d41f9318b5\n--- /dev/null\n+++ b/arch/arm/include/asm/arch-sunxi/sunxi_nsi.h\n@@ -0,0 +1,25 @@\n+// SPDX-License-Identifier:\tGPL-2.0+\n+/*\n+ * A133/A523 NSI interconnect register and constant defines\n+ *\n+ * (C) Copyright 2026 Arm Ltd.\n+ */\n+\n+#ifndef SUNXI_NSI_H__\n+#define SUNXI_NSI_H__\n+\n+#define SUNXI_NSI_PRI_CFG_LOWEST\t0\n+#define SUNXI_NSI_PRI_CFG_LOW\t\t1\n+#define SUNXI_NSI_PRI_CFG_HIGH\t\t2\n+#define SUNXI_NSI_PRI_CFG_HIGHEST\t3\n+\n+#define SUNXI_NSI_IO_CFG_QOS_SEL_OUTPUT\t0\n+#define SUNXI_NSI_IO_CFG_QOS_SEL_INPUT\t1\n+\n+#define NSI_CONF(port, pri, qos_sel) \\\n+\t{ SUNXI_NSI_PORT_ ## port, SUNXI_NSI_PRI_CFG_ ## pri, \\\n+\t SUNXI_NSI_IO_CFG_QOS_SEL_ ## qos_sel }\n+\n+void nsi_configure_port(unsigned int port, u8 pri, u8 qos_sel);\n+\n+#endif /* SUNXI_NSI_H__ */\ndiff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile\nindex 0bee04d660f..3ef0113ea43 100644\n--- a/arch/arm/mach-sunxi/Makefile\n+++ b/arch/arm/mach-sunxi/Makefile\n@@ -50,6 +50,6 @@ obj-$(CONFIG_DRAM_SUN50I_H616)\t+= dram_sun50i_h616.o dram_dw_helpers.o\n obj-$(CONFIG_DRAM_SUN50I_H616)\t+= dram_timings/\n obj-$(CONFIG_DRAM_SUN50I_A133)\t+= dram_sun50i_a133.o\n obj-$(CONFIG_DRAM_SUN50I_A133)\t+= dram_timings/\n-obj-$(CONFIG_MACH_SUN55I_A523)\t+= dram_sun55i_a523.o dram_dw_helpers.o\n+obj-$(CONFIG_MACH_SUN55I_A523)\t+= dram_sun55i_a523.o dram_dw_helpers.o sunxi_nsi.o\n obj-$(CONFIG_DRAM_SUN55I_A523)\t+= dram_timings/\n endif\ndiff --git a/arch/arm/mach-sunxi/dram_sun55i_a523.c b/arch/arm/mach-sunxi/dram_sun55i_a523.c\nindex 1ffb62863e2..9fb054cea84 100644\n--- a/arch/arm/mach-sunxi/dram_sun55i_a523.c\n+++ b/arch/arm/mach-sunxi/dram_sun55i_a523.c\n@@ -15,6 +15,7 @@\n #include <asm/arch/dram_dw_helpers.h>\n #include <asm/arch/cpu.h>\n #include <asm/arch/prcm.h>\n+#include <asm/arch/sunxi_nsi.h>\n #include <linux/bitops.h>\n #include <linux/delay.h>\n \n@@ -1412,40 +1413,36 @@ static const struct dram_para para = {\n \t.tpr10 = CONFIG_DRAM_SUNXI_TPR10,\n };\n \n-static void sunxi_nsi_init(void)\n+static void nsi_set_master_priority(void)\n {\n-\t/* IOMMU prio 3 */\n-\twritel(0x1, 0x02021418);\n-\twritel(0xf, 0x02021414);\n-\t/* DE prio 2 */\n-\twritel(0x1, 0x02021a18);\n-\twritel(0xa, 0x02021a14);\n-\t/* VE R prio 2 */\n-\twritel(0x1, 0x02021618);\n-\twritel(0xa, 0x02021614);\n-\t/* VE RW prio 2 */\n-\twritel(0x1, 0x02021818);\n-\twritel(0xa, 0x02021814);\n-\t/* ISP prio 2 */\n-\twritel(0x1, 0x02020c18);\n-\twritel(0xa, 0x02020c14);\n-\t/* CSI prio 2 */\n-\twritel(0x1, 0x02021c18);\n-\twritel(0xa, 0x02021c14);\n-\t/* NPU prio 2 */\n-\twritel(0x1, 0x02020a18);\n-\twritel(0xa, 0x02020a14);\n+\tstruct {\n+\t\tunsigned int port;\n+\t\tu8 pri;\n+\t\tu8 qos_sel;\n+\t} ports[] = {\n+\t\tNSI_CONF(NPU,\tHIGH,\t\tINPUT),\n+\t\tNSI_CONF(ISP,\tHIGH,\t\tINPUT),\n+\t\tNSI_CONF(IOMMU,\tHIGHEST,\tINPUT),\n+\t\tNSI_CONF(VE_R,\tHIGH,\t\tINPUT),\n+\t\tNSI_CONF(VE_RW,\tHIGH,\t\tINPUT),\n+\t\tNSI_CONF(DE,\tHIGH,\t\tINPUT),\n+\t\tNSI_CONF(CSI,\tHIGH,\t\tINPUT),\n+\t};\n+\tunsigned int i;\n+\n+\tfor (i = 0; i < ARRAY_SIZE(ports); i++)\n+\t\tnsi_configure_port(ports[i].port, ports[i].pri,\n+\t\t\t\t ports[i].qos_sel);\n \n \t/* close ra0 autogating */\n-\twritel(0x0, 0x02023c00);\n+\twritel(0x0, 0x02023c00);\t/* port 30 */\n \t/* close ta autogating */\n-\twritel(0x0, 0x02023e00);\n+\twritel(0x0, 0x02023e00);\t/* port 31 */\n \t/* close pcie autogating */\n \twritel(0x0, 0x02020600);\n }\n \n static void init_something(void)\n-\n {\n \tu32 *ptr = (u32 *)0x02000804;\n \n@@ -1507,7 +1504,7 @@ unsigned long sunxi_dram_init(void)\n \n \tsize = mctl_calc_size(&config);\n \n-\tsunxi_nsi_init();\n+\tnsi_set_master_priority();\n \tinit_something();\n \n \treturn size;\ndiff --git a/arch/arm/mach-sunxi/sunxi_nsi.c b/arch/arm/mach-sunxi/sunxi_nsi.c\nnew file mode 100644\nindex 00000000000..3d7eb43df46\n--- /dev/null\n+++ b/arch/arm/mach-sunxi/sunxi_nsi.c\n@@ -0,0 +1,31 @@\n+#include <asm/io.h>\n+#include <asm/arch/cpu.h>\n+#include <asm/arch/sunxi_nsi.h>\n+\n+#define SUNXI_NSI_MODE_REG(i)\t\t((i) * 0x200 + 0x10)\n+#define SUNXI_NSI_PRI_CFG_REG(i)\t((i) * 0x200 + 0x14)\n+#define SUNXI_NSI_PRI_CFG_RD(v)\t\t(((v) & 0x3) << 2)\n+#define SUNXI_NSI_PRI_CFG_WR(v)\t\t((v) & 0x3)\n+#define SUNXI_NSI_IO_CFG_REG(i)\t\t((i) * 0x200 + 0x18)\n+#define SUNXI_NSI_ENABLE_REG(i)\t\t((i) * 0x200 + 0xc0)\n+\n+void nsi_configure_port(unsigned int port, u8 pri, u8 qos_sel)\n+{\n+\tvoid *base = (void *)SUNXI_NSI_BASE;\n+\tu32 pri_cfg;\n+\n+\t/* QoS with bandwidth limits is not supported, disable it. */\n+\twritel(0, base + SUNXI_NSI_MODE_REG(port));\n+\twritel(0, base + SUNXI_NSI_ENABLE_REG(port));\n+\n+\t/*\n+\t * QoS direction selection should not be in use, but set it nevertheless\n+\t * to match the BSP behavior (in case it has some other meaning).\n+\t */\n+\twritel(qos_sel, base + SUNXI_NSI_IO_CFG_REG(port));\n+\n+\t/* Port priority is always active. */\n+\tpri_cfg = SUNXI_NSI_PRI_CFG_RD(pri) | SUNXI_NSI_PRI_CFG_WR(pri);\n+\n+\twritel(pri_cfg, base + SUNXI_NSI_PRI_CFG_REG(port));\n+}\n", "prefixes": [ "v2", "1/2" ] }