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GET /api/1.2/patches/2230942/?format=api
{ "id": 2230942, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2230942/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20260430084414.1354490-16-richard.genoud@bootlin.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/1.2/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260430084414.1354490-16-richard.genoud@bootlin.com>", "list_archive_url": null, "date": "2026-04-30T08:44:08", "name": "[15/20] arm: mach-k3: j721s2: Enable LPM resume flow", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "30b952a5e41f3fe62a314107b7123adb932c9349", "submitter": { "id": 88519, "url": "http://patchwork.ozlabs.org/api/1.2/people/88519/?format=api", "name": "Richard Genoud (TI)", "email": "richard.genoud@bootlin.com" }, "delegate": { "id": 3651, "url": "http://patchwork.ozlabs.org/api/1.2/users/3651/?format=api", "username": "trini", "first_name": "Tom", "last_name": "Rini", "email": "trini@ti.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20260430084414.1354490-16-richard.genoud@bootlin.com/mbox/", "series": [ { "id": 502237, "url": "http://patchwork.ozlabs.org/api/1.2/series/502237/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=502237", "date": "2026-04-30T08:43:53", "name": "Introduce resume for J7xx SoCs", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/502237/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2230942/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2230942/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=bootlin.com header.i=@bootlin.com header.a=rsa-sha256\n header.s=dkim header.b=uySGbYKR;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=85.214.62.61; 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Thu, 30 Apr 2026 10:45:09 +0200 (CEST)", "from smtpout-02.galae.net (smtpout-02.galae.net [185.246.84.56])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits))\n (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id 24C4B846C6\n for <u-boot@lists.denx.de>; Thu, 30 Apr 2026 10:45:07 +0200 (CEST)", "from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233])\n by smtpout-02.galae.net (Postfix) with ESMTPS id CD6121A347D;\n Thu, 30 Apr 2026 08:45:06 +0000 (UTC)", "from mail.galae.net (mail.galae.net [212.83.136.155])\n by smtpout-01.galae.net (Postfix) with ESMTPS id 9981760495;\n Thu, 30 Apr 2026 08:45:06 +0000 (UTC)", "from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon)\n with ESMTPSA id 7DB161072B7B6;\n Thu, 30 Apr 2026 10:45:03 +0200 (CEST)" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED,\n DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED,\n SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.2", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim;\n t=1777538705; h=from:subject:date:message-id:to:cc:mime-version:\n content-transfer-encoding:in-reply-to:references;\n bh=2FNOOvp0P7BMFojNvkaeaWCPcuIEVFD7ts93E+5wKpg=;\n b=uySGbYKR+7W/lexQ4sJecqceRdeGCxDUxc6mnj81Dt4xGJ39nZD3LhuOXIeinxM0BqHM7i\n MEo8tQnh9xoiU8V+IF6AoI/MGnIikFAqmNXFbe6LJJHAa5Zn+RqLu2J2omCgVtbkMJa6zU\n LdVeOyArhXL/jGJCBG2AKjmUGx+X/b2eK38oPwMTRZOP521wpCXODGbySsdx+hE1lQzlBh\n 3ZhI4XkTWsntm62DxnyztpPLHz4zPYiBh7cRAZs7poQvRmUwN3MSlSOaEdzbnd6KjTCyur\n S3iOJhFBADW+zvNC8Fa99ThJruKDj1n/17IggPwSQpaHIzBkAP5kepm1f8+tLQ==", "From": "\"Richard Genoud (TI)\" <richard.genoud@bootlin.com>", "To": "Tom Rini <trini@konsulko.com>, Manorit Chawdhry <m-chawdhry@ti.com>,\n Apurva Nandan <a-nandan@ti.com>, \"Andrew F . Davis\" <afd@ti.com>,\n Vignesh Raghavendra <vigneshr@ti.com>, Bryan Brattlof <bb@ti.com>,\n Vaishnav Achath <vaishnav.a@ti.com>, Jayesh Choudhary <j-choudhary@ti.com>,\n Simon Glass <sjg@chromium.org>, Alper Nebi Yasak <alpernebiyasak@gmail.com>", "Cc": "Markus Schneider-Pargmann <msp@baylibre.com>,\n Udit Kumar <u-kumar1@ti.com>,\n Abhash Kumar <a-kumar2@ti.com>,\n Thomas Richard <thomas.richard@bootlin.com>,\n Gregory CLEMENT <gregory.clement@bootlin.com>,\n Thomas Petazzoni <thomas.petazzoni@bootlin.com>,\n Richard Genoud <richard.genoud@bootlin.com>, u-boot@lists.denx.de", "Subject": "[PATCH 15/20] arm: mach-k3: j721s2: Enable LPM resume flow", "Date": "Thu, 30 Apr 2026 10:44:08 +0200", "Message-ID": "<20260430084414.1354490-16-richard.genoud@bootlin.com>", "X-Mailer": "git-send-email 2.47.3", "In-Reply-To": "<20260430084414.1354490-1-richard.genoud@bootlin.com>", "References": "<20260430084414.1354490-1-richard.genoud@bootlin.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-Last-TLS-Session-Version": "TLSv1.3", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.39", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.103.8 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "From: \"Thomas Richard (TI)\" <thomas.richard@bootlin.com>\n\nAdd the board specific part of the exit retention sequence for k3-ddrss:\n- exit DDR from retention\n- de-assert the DDR_RET pin\n- restore DDR max frequency\n- exit DDR from low power\nThen generic resume path is run.\n\nSigned-off-by: Thomas Richard (TI) <thomas.richard@bootlin.com>\n---\n arch/arm/mach-k3/j721s2/j721s2_init.c | 73 +++++++++++++++++++++++++--\n 1 file changed, 69 insertions(+), 4 deletions(-)", "diff": "diff --git a/arch/arm/mach-k3/j721s2/j721s2_init.c b/arch/arm/mach-k3/j721s2/j721s2_init.c\nindex b5453d8895d4..0dcdc817e5a5 100644\n--- a/arch/arm/mach-k3/j721s2/j721s2_init.c\n+++ b/arch/arm/mach-k3/j721s2/j721s2_init.c\n@@ -16,12 +16,17 @@\n #include <dm/uclass-internal.h>\n #include <dm/pinctrl.h>\n #include <dm/root.h>\n+#include <mach/k3-ddr.h>\n #include <mmc.h>\n+#include <power/pmic.h>\n #include <remoteproc.h>\n \n #include \"../sysfw-loader.h\"\n+#include \"../lpm-common.h\"\n #include \"../common.h\"\n \n+#define MAX_DDR_CONTROLLERS\t2\n+\n /* NAVSS North Bridge (NB) */\n #define NAVSS0_NBSS_NB0_CFG_MMRS\t\t0x03702000\n #define NAVSS0_NBSS_NB1_CFG_MMRS\t\t0x03703000\n@@ -250,12 +255,42 @@ bool check_rom_loaded_sysfw(void)\n \treturn is_rom_loaded_sysfw(&bootdata);\n }\n \n+#define GPIO_OUT_1 0x3D\n+#define DDR_RET_VAL BIT(3)\n+#define PMIC_NSLEEP_REG 0x86\n+\n+static void k3_deassert_ddr_ret(void)\n+{\n+\tstruct udevice *pmic;\n+\tint regval;\n+\tint err;\n+\n+\terr = uclass_get_device_by_name(UCLASS_PMIC,\n+\t\t\t\t\t\"pmic@4c\", &pmic);\n+\tif (err) {\n+\t\tprintf(\"Getting PMIC@4c init failed: %d\\n\", err);\n+\t\treturn;\n+\t}\n+\t/* Set DDR_RET Signal Low on PMIC B */\n+\tregval = pmic_reg_read(pmic, GPIO_OUT_1) & ~DDR_RET_VAL;\n+\tregval &= ~(1 << (4 - 1));\n+\tpmic_reg_write(pmic, GPIO_OUT_1, regval);\n+}\n+\n+__weak bool j7xx_board_is_resuming(void)\n+{\n+\treturn false;\n+}\n+\n void k3_mem_init(void)\n {\n \tstruct udevice *dev;\n-\tint ret;\n+\tint ret, ctrl = 0;\n \n \tif (IS_ENABLED(CONFIG_K3_J721E_DDRSS)) {\n+\t\tstruct udevice *devs[MAX_DDR_CONTROLLERS];\n+\t\tstruct k3_ddrss_regs regs[MAX_DDR_CONTROLLERS];\n+\n \t\tret = uclass_get_device_by_name(UCLASS_MISC, \"msmc\", &dev);\n \t\tif (ret)\n \t\t\tpanic(\"Probe of msmc failed: %d\\n\", ret);\n@@ -263,10 +298,40 @@ void k3_mem_init(void)\n \t\tret = uclass_get_device(UCLASS_RAM, 0, &dev);\n \t\tif (ret)\n \t\t\tpanic(\"DRAM 0 init failed: %d\\n\", ret);\n+\t\tdevs[0] = dev;\n+\t\tctrl++;\n \n-\t\tret = uclass_next_device_err(&dev);\n-\t\tif (ret && ret != -ENODEV)\n-\t\t\tpanic(\"DRAM 1 init failed: %d\\n\", ret);\n+\t\twhile (ctrl < MAX_DDR_CONTROLLERS) {\n+\t\t\tret = uclass_next_device_err(&dev);\n+\t\t\tif (ret == -ENODEV)\n+\t\t\t\tbreak;\n+\n+\t\t\tif (ret)\n+\t\t\t\tpanic(\"DRAM %d init failed: %d\\n\", ctrl, ret);\n+\t\t\tdevs[ctrl] = dev;\n+\t\t\tctrl++;\n+\t\t}\n+\n+\t\tif (j7xx_board_is_resuming()) {\n+\t\t\t/* exit DDRs from retention */\n+\t\t\tfor (ctrl = 0; ctrl < MAX_DDR_CONTROLLERS; ctrl++)\n+\t\t\t\tk3_ddrss_lpddr4_exit_retention(devs[ctrl],\n+\t\t\t\t\t\t\t ®s[ctrl]);\n+\n+\t\t\t/* de-assert DDR_RET pin */\n+\t\t\tk3_deassert_ddr_ret();\n+\n+\t\t\t/* restore DDR max frequency */\n+\t\t\tfor (ctrl = 0; ctrl < MAX_DDR_CONTROLLERS; ctrl++)\n+\t\t\t\tk3_ddrss_lpddr4_change_freq(devs[ctrl]);\n+\n+\t\t\t/* exit DDR from low power */\n+\t\t\tfor (ctrl = 0; ctrl < MAX_DDR_CONTROLLERS; ctrl++)\n+\t\t\t\tk3_ddrss_lpddr4_exit_low_power(devs[ctrl],\n+\t\t\t\t\t\t\t ®s[ctrl]);\n+\n+\t\t\tdo_resume();\n+\t\t}\n \t}\n \tspl_enable_cache();\n }\n", "prefixes": [ "15/20" ] }