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GET /api/1.2/patches/2230939/?format=api
{ "id": 2230939, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2230939/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20260430084414.1354490-13-richard.genoud@bootlin.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/1.2/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260430084414.1354490-13-richard.genoud@bootlin.com>", "list_archive_url": null, "date": "2026-04-30T08:44:05", "name": "[12/20] arm: mach-k3: j721e: Enable LPM resume flow for J7200/J721e SOC", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "f4178527c07e7ea56f13fce57841e8da04093f86", "submitter": { "id": 88519, "url": "http://patchwork.ozlabs.org/api/1.2/people/88519/?format=api", "name": "Richard Genoud (TI)", "email": "richard.genoud@bootlin.com" }, "delegate": { "id": 3651, "url": "http://patchwork.ozlabs.org/api/1.2/users/3651/?format=api", "username": "trini", "first_name": "Tom", "last_name": "Rini", "email": "trini@ti.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20260430084414.1354490-13-richard.genoud@bootlin.com/mbox/", "series": [ { "id": 502237, "url": "http://patchwork.ozlabs.org/api/1.2/series/502237/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=502237", "date": "2026-04-30T08:43:53", "name": "Introduce resume for J7xx SoCs", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/502237/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2230939/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2230939/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=bootlin.com header.i=@bootlin.com header.a=rsa-sha256\n header.s=dkim header.b=FRiK6a+w;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=85.214.62.61; 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Thu, 30 Apr 2026 10:45:05 +0200 (CEST)", "from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits))\n (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id AB458846A0\n for <u-boot@lists.denx.de>; Thu, 30 Apr 2026 10:44:59 +0200 (CEST)", "from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233])\n by smtpout-04.galae.net (Postfix) with ESMTPS id D7243C5CD68;\n Thu, 30 Apr 2026 08:45:43 +0000 (UTC)", "from mail.galae.net (mail.galae.net [212.83.136.155])\n by smtpout-01.galae.net (Postfix) with ESMTPS id 5DEF060495;\n Thu, 30 Apr 2026 08:44:59 +0000 (UTC)", "from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon)\n with ESMTPSA id 2A0EF1072B7B6;\n Thu, 30 Apr 2026 10:44:54 +0200 (CEST)" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED,\n DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED,\n SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.2", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim;\n t=1777538697; h=from:subject:date:message-id:to:cc:mime-version:\n content-transfer-encoding:in-reply-to:references;\n bh=9uTktzKFFPq1syVHDDNGnJP1gU9CNedTGFJexEHG6HQ=;\n b=FRiK6a+wJl/djiGWMFOkzHanLnbYkt9XLd8v4ncjimHIA5PNzyzAutrKxm3ZEvzzTY1MC+\n O49+Xjlpz0a4OiXCdd85a+OlLTtP6eBHSlVLTusV2XxA27bCHUUS8QzyNGuzf8yy+YE6O/\n xn/ThBSPJwJLm3uaMhsrtBKSFTJ10N98pYfPDSQ5BztoxC24RF9nKlDf8cG+eBewXHy7rW\n XMcJkC9MvuL0zMhzxNrTEqljybxxwWXm1DHhLzwyR7UI092E8EfBrTMn0dY6LbvBu2kN6+\n D4Q/zYLrqM/fL0iiwaR7tEYDR/C/BOlh6bD7ESHts0nqw9riVZDZzvPoOOSiKA==", "From": "\"Richard Genoud (TI)\" <richard.genoud@bootlin.com>", "To": "Tom Rini <trini@konsulko.com>, Manorit Chawdhry <m-chawdhry@ti.com>,\n Apurva Nandan <a-nandan@ti.com>, \"Andrew F . Davis\" <afd@ti.com>,\n Vignesh Raghavendra <vigneshr@ti.com>, Bryan Brattlof <bb@ti.com>,\n Vaishnav Achath <vaishnav.a@ti.com>, Jayesh Choudhary <j-choudhary@ti.com>,\n Simon Glass <sjg@chromium.org>, Alper Nebi Yasak <alpernebiyasak@gmail.com>", "Cc": "Markus Schneider-Pargmann <msp@baylibre.com>,\n Udit Kumar <u-kumar1@ti.com>,\n Abhash Kumar <a-kumar2@ti.com>,\n Thomas Richard <thomas.richard@bootlin.com>,\n Gregory CLEMENT <gregory.clement@bootlin.com>,\n Thomas Petazzoni <thomas.petazzoni@bootlin.com>,\n Richard Genoud <richard.genoud@bootlin.com>, u-boot@lists.denx.de", "Subject": "[PATCH 12/20] arm: mach-k3: j721e: Enable LPM resume flow for\n J7200/J721e SOC", "Date": "Thu, 30 Apr 2026 10:44:05 +0200", "Message-ID": "<20260430084414.1354490-13-richard.genoud@bootlin.com>", "X-Mailer": "git-send-email 2.47.3", "In-Reply-To": "<20260430084414.1354490-1-richard.genoud@bootlin.com>", "References": "<20260430084414.1354490-1-richard.genoud@bootlin.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-Last-TLS-Session-Version": "TLSv1.3", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.39", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.103.8 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "From: \"Thomas Richard (TI)\" <thomas.richard@bootlin.com>\n\nAdd support for resuming from suspend in board_init_f.\nThe resume state of the SOC is identified and lpm resume\nsequence is followed accordingly.\n\nFirst, add the board specific part of the exit retention sequence for\nk3-ddrss following the DDR resume sequence:\n - exit DDR from retention\n - de-assert the DDR_RET pin\n - restore DDR max frequency\n - exit DDR from low power\n\nThen:\n - Extract context address from devicetree and send to TIFS.\n - Power on the rproc cluster.\n - Replay the certificates attached to saved images of ATF and OPTEE.\n - Resume sequence for context restore and rproc resume.\n - Image entry to DM firmware.\n(All those steps are done in do_resume())\n\nThe context address area is firewalled by TIFS to protect it from\nother hosts.\n\nCo-developed-by: Gregory CLEMENT (TI) <gregory.clement@bootlin.com>\nSigned-off-by: Gregory CLEMENT (TI) <gregory.clement@bootlin.com>\nSigned-off-by: Thomas Richard (TI) <thomas.richard@bootlin.com>\nCo-developed-by: Prasanth Babu Mantena <p-mantena@ti.com>\nSigned-off-by: Prasanth Babu Mantena <p-mantena@ti.com>\nCo-developed-by: Richard Genoud (TI) <richard.genoud@bootlin.com>\nSigned-off-by: Richard Genoud (TI) <richard.genoud@bootlin.com>\n---\n arch/arm/mach-k3/j721e/j721e_init.c | 64 +++++++++++++++++++++++++++++\n 1 file changed, 64 insertions(+)", "diff": "diff --git a/arch/arm/mach-k3/j721e/j721e_init.c b/arch/arm/mach-k3/j721e/j721e_init.c\nindex f9af0288cf66..a1f87e653299 100644\n--- a/arch/arm/mach-k3/j721e/j721e_init.c\n+++ b/arch/arm/mach-k3/j721e/j721e_init.c\n@@ -20,9 +20,12 @@\n #include <mmc.h>\n #include <remoteproc.h>\n #include <k3-avs.h>\n+#include <power/pmic.h>\n+#include <mach/k3-ddr.h>\n \n #include \"../sysfw-loader.h\"\n #include \"../common.h\"\n+#include \"../lpm-common.h\"\n \n /* NAVSS North Bridge (NB) registers */\n #define NAVSS0_NBSS_NB0_CFG_MMRS\t\t0x03802000\n@@ -294,10 +297,55 @@ void do_dt_magic(void)\n }\n #endif\n \n+#define GPIO_OUT_1 0x3D\n+#define DDR_RET_VAL BIT(1)\n+#define DDR_RET_CLK BIT(2)\n+#define PMIC_NSLEEP_REG 0x86\n+\n+static void __maybe_unused k3_deassert_DDR_RET(void)\n+{\n+\tstruct udevice *pmica;\n+\tstruct udevice *pmicb;\n+\tint regval;\n+\tint ret;\n+\n+\tret = uclass_get_device_by_name(UCLASS_PMIC,\n+\t\t\t\t\t\"pmic@48\", &pmica);\n+\tif (ret) {\n+\t\tprintf(\"Getting PMICA init failed: %d\\n\", ret);\n+\t\treturn;\n+\t}\n+\n+\tret = uclass_get_device_by_name(UCLASS_PMIC,\n+\t\t\t\t\t\"pmic@4c\", &pmicb);\n+\tif (ret) {\n+\t\tprintf(\"Getting PMICB init failed: %d\\n\", ret);\n+\t\treturn;\n+\t}\n+\t/* Set DDR_RET Signal Low on PMIC B */\n+\tregval = pmic_reg_read(pmicb, GPIO_OUT_1) & ~DDR_RET_VAL;\n+\n+\tpmic_reg_write(pmicb, GPIO_OUT_1, regval);\n+\n+\t/* Now toggle the CLK of the latch for DDR ret */\n+\tpmic_reg_write(pmicb, GPIO_OUT_1, regval | DDR_RET_CLK);\n+\tpmic_reg_write(pmicb, GPIO_OUT_1, regval & ~(DDR_RET_CLK));\n+\tpmic_reg_write(pmicb, GPIO_OUT_1, regval | DDR_RET_CLK);\n+\tpmic_reg_write(pmicb, GPIO_OUT_1, regval & ~(DDR_RET_CLK));\n+\n+\tpmic_reg_write(pmica, PMIC_NSLEEP_REG, 0x3);\n+}\n+\n+__weak bool j7xx_board_is_resuming(void)\n+{\n+\treturn false;\n+}\n+\n void board_init_f(ulong dummy)\n {\n \tint ret;\n #if defined(CONFIG_K3_J721E_DDRSS) || defined(CONFIG_K3_LOAD_SYSFW)\n+\tstruct k3_ddrss_regs regs;\n \tstruct udevice *dev;\n #endif\n \t/*\n@@ -410,6 +458,22 @@ void board_init_f(ulong dummy)\n \tret = uclass_get_device(UCLASS_RAM, 0, &dev);\n \tif (ret)\n \t\tpanic(\"DRAM init failed: %d\\n\", ret);\n+\n+\tif (j7xx_board_is_resuming()) {\n+\t\t/*\n+\t\t * The DDR resume sequence is:\n+\t\t * - exit DDR from retention\n+\t\t * - de-assert the DDR_RET pin\n+\t\t * - restore DDR max frequency\n+\t\t * - exit DDR from low power\n+\t\t */\n+\t\tk3_ddrss_lpddr4_exit_retention(dev, ®s);\n+\t\tk3_deassert_DDR_RET();\n+\t\tk3_ddrss_lpddr4_change_freq(dev);\n+\t\tk3_ddrss_lpddr4_exit_low_power(dev, ®s);\n+\n+\t\tdo_resume();\n+\t}\n #endif\n \tspl_enable_cache();\n \n", "prefixes": [ "12/20" ] }