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GET /api/1.2/patches/2227868/?format=api
{ "id": 2227868, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2227868/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260424201842.176953-3-junjie.cao@intel.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.2/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260424201842.176953-3-junjie.cao@intel.com>", "list_archive_url": null, "date": "2026-04-24T20:18:42", "name": "[v2,2/2] tests/qtest: add 8-byte MMIO access sweep for intel-iommu", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "9befa3fc0eeec88a18fbb708e356a0e4b8634c11", "submitter": { "id": 91537, "url": "http://patchwork.ozlabs.org/api/1.2/people/91537/?format=api", "name": "Junjie Cao", "email": "junjie.cao@intel.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260424201842.176953-3-junjie.cao@intel.com/mbox/", "series": [ { "id": 501352, "url": "http://patchwork.ozlabs.org/api/1.2/series/501352/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501352", "date": "2026-04-24T20:18:40", "name": "intel_iommu: fix guest-triggerable assert in MMIO handlers", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/501352/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2227868/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2227868/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256\n header.s=Intel header.b=azATtsdK;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g2BmB3vxBz1yDD\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 24 Apr 2026 22:17:14 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1wGFSc-0002eb-Sz; Fri, 24 Apr 2026 08:16:43 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <junjie.cao@intel.com>)\n id 1wGFS6-0002Wv-Nb\n for qemu-devel@nongnu.org; Fri, 24 Apr 2026 08:16:14 -0400", "from mgamail.intel.com ([198.175.65.18])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <junjie.cao@intel.com>)\n id 1wGFS4-0002Dv-Jt\n for qemu-devel@nongnu.org; Fri, 24 Apr 2026 08:16:10 -0400", "from fmviesa005.fm.intel.com ([10.60.135.145])\n by orvoesa110.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 24 Apr 2026 05:16:06 -0700", "from junjie-optiplex-micro-plus-7010.bj.intel.com ([10.238.152.98])\n by fmviesa005-auth.fm.intel.com with\n ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2026 05:16:04 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1777032968; x=1808568968;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=wItBfHW6v9wsyjtAKVgJYEePhRBXmoutUyn+sJKbZ/w=;\n b=azATtsdKuYiJZWivOECgvE7F4zRfkijCyTa2q+BThLfNQmAiSTr9AKe4\n BhKcretq0IWMoBuh32ET8a+XlAD0ENHfUHPlpk+JwxAFDdgRCkj+nIt/S\n 1gJAQ/Z5GknQcT3rt1lliZ+bGio46QDc5VyY0zFefcGdEaH49P1dg2zwk\n ZQROnbVugheAwBlX+/iMyHe2OyTe/AaOMPnVHkhLgGs4SlPdWncFTj308\n AKF7exLyULTXrQNYhk4/uECvABF6VkBTGEEL9KbvSOFTsLjLpGpruelcc\n j0P2ezVRz8E/pJIJvSnlGrjHY2Pg5if8T0DA8h1n19jX2tSAczQLC1oKI A==;", "X-CSE-ConnectionGUID": [ "Ah9P1AqlQEGSPWesXHzfoA==", "Vm0cL1mES/yLh9mK6j55gA==" ], "X-CSE-MsgGUID": [ "fvY4diYrRXyj7jgWum4xvQ==", "UBNpuumnSU+kBVEf/8Wc1Q==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6800,10657,11765\"; a=\"78029988\"", "E=Sophos;i=\"6.23,196,1770624000\"; d=\"scan'208\";a=\"78029988\"", "E=Sophos;i=\"6.23,196,1770624000\"; d=\"scan'208\";a=\"237935796\"" ], "X-ExtLoop1": "1", "From": "Junjie Cao <junjie.cao@intel.com>", "To": "qemu-devel@nongnu.org", "Cc": "junjie.cao@intel.com, mst@redhat.com, jasowang@redhat.com,\n yi.l.liu@intel.com, clement.mathieu--drif@bull.com, philmd@linaro.org,\n zhenzhong.duan@intel.com", "Subject": "[PATCH v2 2/2] tests/qtest: add 8-byte MMIO access sweep for\n intel-iommu", "Date": "Sat, 25 Apr 2026 04:18:42 +0800", "Message-ID": "<20260424201842.176953-3-junjie.cao@intel.com>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260424201842.176953-1-junjie.cao@intel.com>", "References": "<20260424201842.176953-1-junjie.cao@intel.com>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=198.175.65.18;\n envelope-from=junjie.cao@intel.com;\n helo=mgamail.intel.com", "X-Spam_score_int": "-24", "X-Spam_score": "-2.5", "X-Spam_bar": "--", "X-Spam_report": "(-2.5 / 5.0 requ) BAYES_00=-1.9, DATE_IN_FUTURE_06_12=1.947,\n DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1,\n DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Sweep every 4-byte-aligned offset in the VT-d MMIO register space\nwith 8-byte reads and writes to verify that no register handler\naborts on an oversized access.\n\nReviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>\nSigned-off-by: Junjie Cao <junjie.cao@intel.com>\n---\n tests/qtest/intel-iommu-test.c | 30 ++++++++++++++++++++++++++++++\n 1 file changed, 30 insertions(+)", "diff": "diff --git a/tests/qtest/intel-iommu-test.c b/tests/qtest/intel-iommu-test.c\nindex e5cc6acaf0..b1763ed294 100644\n--- a/tests/qtest/intel-iommu-test.c\n+++ b/tests/qtest/intel-iommu-test.c\n@@ -17,11 +17,39 @@\n #define ECAP_STAGE_1_FIXED1 (VTD_ECAP_QI | VTD_ECAP_IR | VTD_ECAP_IRO | \\\n VTD_ECAP_MHMV | VTD_ECAP_SMTS | VTD_ECAP_FSTS)\n \n+static inline uint32_t vtd_reg_readl(QTestState *s, uint64_t offset)\n+{\n+ return qtest_readl(s, Q35_HOST_BRIDGE_IOMMU_ADDR + offset);\n+}\n+\n static inline uint64_t vtd_reg_readq(QTestState *s, uint64_t offset)\n {\n return qtest_readq(s, Q35_HOST_BRIDGE_IOMMU_ADDR + offset);\n }\n \n+static inline void vtd_reg_writeq(QTestState *s, uint64_t offset,\n+ uint64_t value)\n+{\n+ qtest_writeq(s, Q35_HOST_BRIDGE_IOMMU_ADDR + offset, value);\n+}\n+\n+static void test_intel_iommu_8byte_access(void)\n+{\n+ QTestState *s;\n+ uint64_t off;\n+\n+ s = qtest_init(\"-M q35 -device intel-iommu\");\n+\n+ for (off = 0; off < DMAR_REG_SIZE; off += 4) {\n+ vtd_reg_readq(s, off);\n+ vtd_reg_writeq(s, off, 0);\n+ }\n+\n+ g_assert_cmpuint(vtd_reg_readl(s, DMAR_VER_REG), !=, 0);\n+\n+ qtest_quit(s);\n+}\n+\n static void test_intel_iommu_stage_1(void)\n {\n uint8_t init_csr[DMAR_REG_SIZE]; /* register values */\n@@ -58,6 +86,8 @@ static void test_intel_iommu_stage_1(void)\n int main(int argc, char **argv)\n {\n g_test_init(&argc, &argv, NULL);\n+ qtest_add_func(\"/q35/intel-iommu/8byte-access\",\n+ test_intel_iommu_8byte_access);\n qtest_add_func(\"/q35/intel-iommu/stage-1\", test_intel_iommu_stage_1);\n \n return g_test_run();\n", "prefixes": [ "v2", "2/2" ] }