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GET /api/1.2/patches/2226266/?format=api
{ "id": 2226266, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2226266/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/patch/bmm.hhubd62wbc.gcc.gcc-TEST.pinskia.20.1.8@forge-stage.sourceware.org/", "project": { "id": 17, "url": "http://patchwork.ozlabs.org/api/1.2/projects/17/?format=api", "name": "GNU Compiler Collection", "link_name": "gcc", "list_id": "gcc-patches.gcc.gnu.org", "list_email": "gcc-patches@gcc.gnu.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<bmm.hhubd62wbc.gcc.gcc-TEST.pinskia.20.1.8@forge-stage.sourceware.org>", "list_archive_url": null, "date": "2026-04-22T10:29:53", "name": "[v1,08/11] Fix", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "310aec32b80928cf16dff21eebacf0b04cb924fd", "submitter": { "id": 93219, "url": "http://patchwork.ozlabs.org/api/1.2/people/93219/?format=api", "name": "Andrew Pinski via Sourceware Forge", "email": "forge-bot+pinskia@forge-stage.sourceware.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/gcc/patch/bmm.hhubd62wbc.gcc.gcc-TEST.pinskia.20.1.8@forge-stage.sourceware.org/mbox/", "series": [ { "id": 500972, "url": "http://patchwork.ozlabs.org/api/1.2/series/500972/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/list/?series=500972", "date": "2026-04-22T10:29:49", "name": "WIP: v2hiv4qi", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/500972/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2226266/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2226266/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Delivered-To": [ "patchwork-incoming@legolas.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Authentication-Results": [ "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=2620:52:6:3111::32; helo=vm01.sourceware.org;\n envelope-from=gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org;\n receiver=patchwork.ozlabs.org)", "sourceware.org; dmarc=none (p=none dis=none)\n header.from=forge-stage.sourceware.org", "sourceware.org;\n spf=pass smtp.mailfrom=forge-stage.sourceware.org", "server2.sourceware.org;\n arc=none smtp.remote-ip=38.145.34.39" ], "Received": [ "from vm01.sourceware.org (vm01.sourceware.org\n [IPv6:2620:52:6:3111::32])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g0x1T432Wz1yD5\n\tfor <incoming@patchwork.ozlabs.org>; Wed, 22 Apr 2026 20:54:21 +1000 (AEST)", "from vm01.sourceware.org (localhost [127.0.0.1])\n\tby sourceware.org (Postfix) with ESMTP id EC9B0407C154\n\tfor <incoming@patchwork.ozlabs.org>; Wed, 22 Apr 2026 10:54:18 +0000 (GMT)", "from forge-stage.sourceware.org (vm08.sourceware.org [38.145.34.39])\n by sourceware.org (Postfix) with ESMTPS id 563AD48FD86E\n for <gcc-patches@gcc.gnu.org>; Wed, 22 Apr 2026 10:31:09 +0000 (GMT)", "from forge-stage.sourceware.org (localhost [IPv6:::1])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n key-exchange x25519 server-signature ECDSA (prime256v1) server-digest SHA256)\n (No client certificate requested)\n by forge-stage.sourceware.org (Postfix) with ESMTPS id 76F504260B\n for <gcc-patches@gcc.gnu.org>; Wed, 22 Apr 2026 10:31:06 +0000 (UTC)" ], "DKIM-Filter": [ "OpenDKIM Filter v2.11.0 sourceware.org EC9B0407C154", "OpenDKIM Filter v2.11.0 sourceware.org 563AD48FD86E" ], "DMARC-Filter": "OpenDMARC Filter v1.4.2 sourceware.org 563AD48FD86E", "ARC-Filter": "OpenARC Filter v1.0.0 sourceware.org 563AD48FD86E", "ARC-Seal": "i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1776853869; cv=none;\n b=Fi1I5avafl7nX/YhgDT7p0rN3PVUUecnMG3uhedu13dJDWLreHgPKONewdmPVukZ9j0y05n83sWjPkH21sKibROOLgCgpIjckmaGpcG6lY3MBIhx/w99V/NDMVhRabmuBv6h+0I3dy27hYDpFkEZVChjtJHKD+Q416sx/FH7ZzU=", "ARC-Message-Signature": "i=1; a=rsa-sha256; d=sourceware.org; s=key;\n t=1776853869; c=relaxed/simple;\n bh=xPs5u7Vad9rYsCf19szju9YfQDBdAvNZ6mGsWdMZ+1E=;\n h=From:Date:Subject:To:Message-ID;\n b=cbJAG4s+9kwq5aT60i2gXQQn9tmQOcGPsVWny/fu90dqAwFkc9ArZOLSbsBFLlTnG87CiNDev6Ol9p1Jov1NKDbbdarluS49MrV5uDa24NEoID0iZDzKlyTYyBaR5zj0oiO/pDKWcHlol2kwVBRdMwNsXhuhhECzbkqFLEknK5I=", "ARC-Authentication-Results": "i=1; server2.sourceware.org", "From": "Andrew Pinski via Sourceware Forge\n <forge-bot+pinskia@forge-stage.sourceware.org>", "Date": "Wed, 22 Apr 2026 10:29:53 +0000", "Subject": "[PATCH v1 08/11] Fix", "To": "gcc-patches mailing list <gcc-patches@gcc.gnu.org>", "Message-ID": "\n <bmm.hhubd62wbc.gcc.gcc-TEST.pinskia.20.1.8@forge-stage.sourceware.org>", "X-Mailer": "batrachomyomachia", "X-Pull-Request-Organization": "gcc", "X-Pull-Request-Repository": "gcc-TEST", "X-Pull-Request": "https://forge.sourceware.org/gcc/gcc-TEST/pulls/20", "References": "\n <bmm.hhubd62wbc.gcc.gcc-TEST.pinskia.20.1.0@forge-stage.sourceware.org>", "In-Reply-To": "\n <bmm.hhubd62wbc.gcc.gcc-TEST.pinskia.20.1.0@forge-stage.sourceware.org>", "X-Patch-URL": "\n https://forge.sourceware.org/pinskia/gcc-TEST/commit/e0fcf0c81d4ae9d6c9ce2c229b9a3a4d2dc789d3", "X-BeenThere": "gcc-patches@gcc.gnu.org", "X-Mailman-Version": "2.1.30", "Precedence": "list", "List-Id": "Gcc-patches mailing list <gcc-patches.gcc.gnu.org>", "List-Unsubscribe": "<https://gcc.gnu.org/mailman/options/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=unsubscribe>", "List-Archive": "<https://gcc.gnu.org/pipermail/gcc-patches/>", "List-Post": "<mailto:gcc-patches@gcc.gnu.org>", "List-Help": "<mailto:gcc-patches-request@gcc.gnu.org?subject=help>", "List-Subscribe": "<https://gcc.gnu.org/mailman/listinfo/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=subscribe>", "Reply-To": "gcc-patches mailing list <gcc-patches@gcc.gnu.org>,\n pinskia@gcc.gnu.org", "Errors-To": "gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org" }, "content": "From: Andrew Pinski <quic_apinski@quicinc.com>\n\nSigned-off-by: Andrew Pinski <quic_apinski@quicinc.com>\n---\n gcc/config/aarch64/aarch64-simd.md | 4 ++--\n gcc/config/aarch64/aarch64-sve.md | 8 ++++----\n gcc/config/aarch64/iterators.md | 10 +++++++---\n 3 files changed, 13 insertions(+), 9 deletions(-)", "diff": "diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md\nindex 1cee004664ca..22763d683b61 100644\n--- a/gcc/config/aarch64/aarch64-simd.md\n+++ b/gcc/config/aarch64/aarch64-simd.md\n@@ -323,7 +323,7 @@\n \n (define_insn \"iorn<mode>3<vczle><vczbe>\"\n [(set (match_operand:VDQS_I 0 \"register_operand\" \"=w\")\n- (ior:VDQ_I (not:VDQS_I (match_operand:VDQ_I 2 \"register_operand\" \"w\"))\n+ (ior:VDQS_I (not:VDQS_I (match_operand:VDQS_I 2 \"register_operand\" \"w\"))\n \t\t(match_operand:VDQS_I 1 \"register_operand\" \"w\")))]\n \"TARGET_SIMD\"\n \"orn\\t%0.<Vbtype>, %1.<Vbtype>, %2.<Vbtype>\"\n@@ -332,7 +332,7 @@\n \n (define_insn \"andn<mode>3<vczle><vczbe>\"\n [(set (match_operand:VDQS_I 0 \"register_operand\" \"=w\")\n- (and:VDQ_I (not:VDQS_I (match_operand:VDQ_I 2 \"register_operand\" \"w\"))\n+ (and:VDQS_I (not:VDQS_I (match_operand:VDQS_I 2 \"register_operand\" \"w\"))\n \t\t(match_operand:VDQS_I 1 \"register_operand\" \"w\")))]\n \"TARGET_SIMD\"\n \"bic\\t%0.<Vbtype>, %1.<Vbtype>, %2.<Vbtype>\"\ndiff --git a/gcc/config/aarch64/aarch64-sve.md b/gcc/config/aarch64/aarch64-sve.md\nindex 06bd3e4bb2c0..d2afb59e40ca 100644\n--- a/gcc/config/aarch64/aarch64-sve.md\n+++ b/gcc/config/aarch64/aarch64-sve.md\n@@ -3121,11 +3121,11 @@\n \n ;; Integer unary arithmetic predicated with a PTRUE.\n (define_insn \"@aarch64_pred_<optab><mode>\"\n- [(set (match_operand:SVE_VDQ_I 0 \"register_operand\")\n-\t(unspec:SVE_VDQ_I\n+ [(set (match_operand:SVE_VDQS_I 0 \"register_operand\")\n+\t(unspec:SVE_VDQS_I\n \t [(match_operand:<VPRED> 1 \"register_operand\")\n-\t (SVE_INT_UNARY:SVE_VDQ_I\n-\t (match_operand:SVE_VDQ_I 2 \"register_operand\"))]\n+\t (SVE_INT_UNARY:SVE_VDQS_I\n+\t (match_operand:SVE_VDQS_I 2 \"register_operand\"))]\n \t UNSPEC_PRED_X))]\n \"TARGET_SVE\"\n {@ [ cons: =0 , 1 , 2 ; attrs: movprfx ]\ndiff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md\nindex c042da62a870..5e8d42ca4f1d 100644\n--- a/gcc/config/aarch64/iterators.md\n+++ b/gcc/config/aarch64/iterators.md\n@@ -87,7 +87,7 @@\n (define_mode_iterator VDQ_I [V8QI V16QI V4HI V8HI V2SI V4SI V2DI])\n \n ;; Integer Advanced SIMD modes plus 32bit modes\n-(define_mode_iterator VDQS_I [V4QI V2HI V8QI V16QI V4HI V8HI V2SI V4SI V2DI])\n+(define_mode_iterator VDQS_I [V4QI V2HI VDQ_I])\n \n ;; Advanced SIMD and scalar, 64 & 128-bit container, all integer modes.\n (define_mode_iterator VSDQ_I [V8QI V16QI V4HI V8HI V2SI V4SI V2DI QI HI SI DI])\n@@ -97,7 +97,7 @@\n (define_mode_iterator VSDQ_I_DI [V8QI V16QI V4HI V8HI V2SI V4SI V2DI DI])\n \n ;; Same as above plus the 32bit modes\n-(define_mode_iterator VSDQS_I_DI [V4QI V2HI V8QI V16QI V4HI V8HI V2SI V4SI V2DI DI])\n+(define_mode_iterator VSDQS_I_DI [V4QI V2HI VSDQ_I_DI])\n \n ;; Double vector modes.\n (define_mode_iterator VD [V8QI V4HI V4HF V2SI V2SF V4BF])\n@@ -127,7 +127,7 @@\n (define_mode_iterator VDQ_BHSI [V8QI V16QI V4HI V8HI V2SI V4SI])\n \n ;; 128, 64, and 32-bit container; 8, 16, 32-bit vector integer modes\n-(define_mode_iterator VDQS_BHSI [V4QI V2HI V8QI V16QI V4HI V8HI V2SI V4SI])\n+(define_mode_iterator VDQS_BHSI [V4QI V2HI VDQ_BHSI])\n \n ;; Quad vector modes.\n (define_mode_iterator VQ [V16QI V8HI V4SI V2DI V8HF V4SF V2DF V8BF])\n@@ -606,6 +606,9 @@\n ;; All SVE and Advanced SIMD integer vector modes.\n (define_mode_iterator SVE_VDQ_I [SVE_I VDQ_I V1DI])\n \n+;; All SVE and Advanced SIMD integer vector modes.\n+(define_mode_iterator SVE_VDQS_I [SVE_I VDQS_I])\n+\n ;; SVE integer vector modes whose elements are 16 bits or wider.\n (define_mode_iterator SVE_HSDI [VNx8HI VNx4HI VNx2HI\n \t\t\t\tVNx4SI VNx2SI\n@@ -2361,6 +2364,7 @@\n \t\t\t (VNx32BF \"VNx8BI\")\n \t\t\t (VNx16SI \"VNx4BI\") (VNx16SF \"VNx4BI\")\n \t\t\t (VNx8DI \"VNx2BI\") (VNx8DF \"VNx2BI\")\n+\t\t\t (V4QI \"VNx4BI\") (V2HI \"VNx2BI\")\n \t\t\t (V8QI \"VNx8BI\") (V16QI \"VNx16BI\")\n \t\t\t (V4HI \"VNx4BI\") (V8HI \"VNx8BI\") (V2SI \"VNx2BI\")\n \t\t\t (V4SI \"VNx4BI\") (V2DI \"VNx2BI\") (V1DI \"VNx2BI\")])\n", "prefixes": [ "v1", "08/11" ] }