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GET /api/1.2/patches/2226138/?format=api
{ "id": 2226138, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2226138/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260422101043.1234229-3-alex.bennee@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.2/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260422101043.1234229-3-alex.bennee@linaro.org>", "list_archive_url": null, "date": "2026-04-22T10:10:13", "name": "[v2,02/31] target/arm: migrate system/cp trap syndromes to registerfields", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "92f63a4c513623fd558f583e71201abedb65dd8a", "submitter": { "id": 39532, "url": "http://patchwork.ozlabs.org/api/1.2/people/39532/?format=api", "name": "Alex Bennée", "email": "alex.bennee@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260422101043.1234229-3-alex.bennee@linaro.org/mbox/", "series": [ { "id": 500957, "url": "http://patchwork.ozlabs.org/api/1.2/series/500957/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500957", "date": "2026-04-22T10:10:11", "name": "target/arm: fully model WFxT instructions for A-profile", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/500957/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2226138/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2226138/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=vEdhRZli;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=UTF-8", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2a00:1450:4864:20::32d;\n envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x32d.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Migrate syn_aa64_sysregtrap and co-processor register trap syndromes\nto the registerfields API. The co-processor syndromes are split\nbetween single and duel register moves.\n\nReviewed-by: Richard Henderson <richard.henderson@linaro.org>\nSigned-off-by: Alex Bennée <alex.bennee@linaro.org>\n\n---\nv2\n - use !is_16bit directly\n---\n target/arm/syndrome.h | 124 ++++++++++++++++++++++++++++++++++--------\n 1 file changed, 102 insertions(+), 22 deletions(-)", "diff": "diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h\nindex 517fb2368bc..29462aa103c 100644\n--- a/target/arm/syndrome.h\n+++ b/target/arm/syndrome.h\n@@ -78,7 +78,7 @@ enum arm_exception_class {\n \n /* Generic syndrome encoding layout for HSR and lower 32 bits of ESR_EL2 */\n FIELD(SYNDROME, EC, 26, 6)\n-FIELD(SYNDROME, IL, 25, 1)\n+FIELD(SYNDROME, IL, 25, 1) /* IL=1 for 32 bit instructions */\n FIELD(SYNDROME, ISS, 0, 25)\n \n typedef enum {\n@@ -172,7 +172,7 @@ static inline uint32_t syn_aa64_smc(uint32_t imm16)\n static inline uint32_t syn_aa32_svc(uint32_t imm16, bool is_16bit)\n {\n uint32_t res = syn_set_ec(0, EC_AA32_SVC);\n- res = FIELD_DP32(res, SYNDROME, IL, is_16bit ? 0 : 1);\n+ res = FIELD_DP32(res, SYNDROME, IL, !is_16bit);\n res = FIELD_DP32(res, ISS_IMM16, IMM16, imm16);\n return res;\n }\n@@ -203,58 +203,138 @@ static inline uint32_t syn_aa64_bkpt(uint32_t imm16)\n static inline uint32_t syn_aa32_bkpt(uint32_t imm16, bool is_16bit)\n {\n uint32_t res = syn_set_ec(0, EC_AA32_BKPT);\n- res = FIELD_DP32(res, SYNDROME, IL, is_16bit ? 0 : 1);\n+ res = FIELD_DP32(res, SYNDROME, IL, !is_16bit);\n res = FIELD_DP32(res, ISS_IMM16, IMM16, imm16);\n return res;\n }\n \n+/*\n+ * ISS encoding for an exception from MSR, MRS, or System instruction\n+ * in AArch64 state.\n+ */\n+FIELD(SYSREG_ISS, ISREAD, 0, 1) /* Direction, 1 is read */\n+FIELD(SYSREG_ISS, CRM, 1, 4)\n+FIELD(SYSREG_ISS, RT, 5, 5)\n+FIELD(SYSREG_ISS, CRN, 10, 4)\n+FIELD(SYSREG_ISS, OP1, 14, 3)\n+FIELD(SYSREG_ISS, OP2, 17, 3)\n+FIELD(SYSREG_ISS, OP0, 20, 2)\n+\n static inline uint32_t syn_aa64_sysregtrap(int op0, int op1, int op2,\n int crn, int crm, int rt,\n int isread)\n {\n- return (EC_SYSTEMREGISTERTRAP << ARM_EL_EC_SHIFT) | ARM_EL_IL\n- | (op0 << 20) | (op2 << 17) | (op1 << 14) | (crn << 10) | (rt << 5)\n- | (crm << 1) | isread;\n+ uint32_t res = syn_set_ec(0, EC_SYSTEMREGISTERTRAP);\n+ res = FIELD_DP32(res, SYNDROME, IL, 1);\n+\n+ res = FIELD_DP32(res, SYSREG_ISS, OP0, op0);\n+ res = FIELD_DP32(res, SYSREG_ISS, OP2, op2);\n+ res = FIELD_DP32(res, SYSREG_ISS, OP1, op1);\n+ res = FIELD_DP32(res, SYSREG_ISS, CRN, crn);\n+ res = FIELD_DP32(res, SYSREG_ISS, RT, rt);\n+ res = FIELD_DP32(res, SYSREG_ISS, CRM, crm);\n+ res = FIELD_DP32(res, SYSREG_ISS, ISREAD, isread);\n+\n+ return res;\n }\n \n+/*\n+ * ISS encoding for an exception from an MCR or MRC access\n+ * (move to/from co-processor)\n+ */\n+FIELD(COPROC_ISS, ISREAD, 0, 1)\n+FIELD(COPROC_ISS, CRM, 1, 4)\n+FIELD(COPROC_ISS, RT, 5, 5)\n+FIELD(COPROC_ISS, CRN, 10, 4)\n+FIELD(COPROC_ISS, OP1, 14, 3)\n+FIELD(COPROC_ISS, OP2, 17, 3)\n+FIELD(COPROC_ISS, COND, 20, 4)\n+FIELD(COPROC_ISS, CV, 24, 1)\n+\n static inline uint32_t syn_cp14_rt_trap(int cv, int cond, int opc1, int opc2,\n int crn, int crm, int rt, int isread,\n bool is_16bit)\n {\n- return (EC_CP14RTTRAP << ARM_EL_EC_SHIFT)\n- | (is_16bit ? 0 : ARM_EL_IL)\n- | (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14)\n- | (crn << 10) | (rt << 5) | (crm << 1) | isread;\n+ uint32_t res = syn_set_ec(0, EC_CP14RTTRAP);\n+ res = FIELD_DP32(res, SYNDROME, IL, !is_16bit);\n+\n+ res = FIELD_DP32(res, COPROC_ISS, CV, cv);\n+ res = FIELD_DP32(res, COPROC_ISS, COND, cond);\n+ res = FIELD_DP32(res, COPROC_ISS, OP2, opc2);\n+ res = FIELD_DP32(res, COPROC_ISS, OP1, opc1);\n+ res = FIELD_DP32(res, COPROC_ISS, CRN, crn);\n+ res = FIELD_DP32(res, COPROC_ISS, RT, rt);\n+ res = FIELD_DP32(res, COPROC_ISS, CRM, crm);\n+ res = FIELD_DP32(res, COPROC_ISS, ISREAD, isread);\n+\n+ return res;\n }\n \n static inline uint32_t syn_cp15_rt_trap(int cv, int cond, int opc1, int opc2,\n int crn, int crm, int rt, int isread,\n bool is_16bit)\n {\n- return (EC_CP15RTTRAP << ARM_EL_EC_SHIFT)\n- | (is_16bit ? 0 : ARM_EL_IL)\n- | (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14)\n- | (crn << 10) | (rt << 5) | (crm << 1) | isread;\n+ uint32_t res = syn_set_ec(0, EC_CP15RTTRAP);\n+ res = FIELD_DP32(res, SYNDROME, IL, !is_16bit);\n+\n+ res = FIELD_DP32(res, COPROC_ISS, CV, cv);\n+ res = FIELD_DP32(res, COPROC_ISS, COND, cond);\n+ res = FIELD_DP32(res, COPROC_ISS, OP2, opc2);\n+ res = FIELD_DP32(res, COPROC_ISS, OP1, opc1);\n+ res = FIELD_DP32(res, COPROC_ISS, CRN, crn);\n+ res = FIELD_DP32(res, COPROC_ISS, RT, rt);\n+ res = FIELD_DP32(res, COPROC_ISS, CRM, crm);\n+ res = FIELD_DP32(res, COPROC_ISS, ISREAD, isread);\n+\n+ return res;\n }\n \n+/*\n+ * ISS encoding for an exception from an MCRR or MRRC access\n+ * (move to/from co-processor with 2 regs)\n+ */\n+FIELD(COPROC_R2_ISS, ISREAD, 0, 1)\n+FIELD(COPROC_R2_ISS, CRM, 1, 4)\n+FIELD(COPROC_R2_ISS, RT, 5, 5)\n+FIELD(COPROC_R2_ISS, RT2, 10, 5)\n+FIELD(COPROC_R2_ISS, OP1, 16, 4)\n+FIELD(COPROC_R2_ISS, COND, 20, 4)\n+FIELD(COPROC_R2_ISS, CV, 24, 1)\n+\n static inline uint32_t syn_cp14_rrt_trap(int cv, int cond, int opc1, int crm,\n int rt, int rt2, int isread,\n bool is_16bit)\n {\n- return (EC_CP14RRTTRAP << ARM_EL_EC_SHIFT)\n- | (is_16bit ? 0 : ARM_EL_IL)\n- | (cv << 24) | (cond << 20) | (opc1 << 16)\n- | (rt2 << 10) | (rt << 5) | (crm << 1) | isread;\n+ uint32_t res = syn_set_ec(0, EC_CP14RRTTRAP);\n+ res = FIELD_DP32(res, SYNDROME, IL, !is_16bit);\n+\n+ res = FIELD_DP32(res, COPROC_R2_ISS, CV, cv);\n+ res = FIELD_DP32(res, COPROC_R2_ISS, COND, cond);\n+ res = FIELD_DP32(res, COPROC_R2_ISS, OP1, opc1);\n+ res = FIELD_DP32(res, COPROC_R2_ISS, RT2, rt2);\n+ res = FIELD_DP32(res, COPROC_R2_ISS, RT, rt);\n+ res = FIELD_DP32(res, COPROC_R2_ISS, CRM, crm);\n+ res = FIELD_DP32(res, COPROC_R2_ISS, ISREAD, isread);\n+\n+ return res;\n }\n \n static inline uint32_t syn_cp15_rrt_trap(int cv, int cond, int opc1, int crm,\n int rt, int rt2, int isread,\n bool is_16bit)\n {\n- return (EC_CP15RRTTRAP << ARM_EL_EC_SHIFT)\n- | (is_16bit ? 0 : ARM_EL_IL)\n- | (cv << 24) | (cond << 20) | (opc1 << 16)\n- | (rt2 << 10) | (rt << 5) | (crm << 1) | isread;\n+ uint32_t res = syn_set_ec(0, EC_CP15RRTTRAP);\n+ res = FIELD_DP32(res, SYNDROME, IL, !is_16bit);\n+\n+ res = FIELD_DP32(res, COPROC_R2_ISS, CV, cv);\n+ res = FIELD_DP32(res, COPROC_R2_ISS, COND, cond);\n+ res = FIELD_DP32(res, COPROC_R2_ISS, OP1, opc1);\n+ res = FIELD_DP32(res, COPROC_R2_ISS, RT2, rt2);\n+ res = FIELD_DP32(res, COPROC_R2_ISS, RT, rt);\n+ res = FIELD_DP32(res, COPROC_R2_ISS, CRM, crm);\n+ res = FIELD_DP32(res, COPROC_R2_ISS, ISREAD, isread);\n+\n+ return res;\n }\n \n static inline uint32_t syn_fp_access_trap(int cv, int cond, bool is_16bit,\n", "prefixes": [ "v2", "02/31" ] }