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GET /api/1.2/patches/2226133/?format=api
{ "id": 2226133, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2226133/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260422101043.1234229-2-alex.bennee@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.2/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260422101043.1234229-2-alex.bennee@linaro.org>", "list_archive_url": null, "date": "2026-04-22T10:10:12", "name": "[v2,01/31] target/arm: migrate basic syndrome helpers to registerfields", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "f9342eadedf3a8f3edc93775d672250847f361b0", "submitter": { "id": 39532, "url": "http://patchwork.ozlabs.org/api/1.2/people/39532/?format=api", "name": "Alex Bennée", "email": "alex.bennee@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260422101043.1234229-2-alex.bennee@linaro.org/mbox/", "series": [ { "id": 500957, "url": "http://patchwork.ozlabs.org/api/1.2/series/500957/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500957", "date": "2026-04-22T10:10:11", "name": "target/arm: fully model WFxT instructions for A-profile", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/500957/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2226133/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2226133/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=Qp3iL1rB;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=UTF-8", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2a00:1450:4864:20::330;\n envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x330.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "We have a registerfields interface which we can use for defining\nfields alongside helpers to access them. Define the basic syndrome\nlayout and convert the helpers that take the imm16 data directly.\n\nReviewed-by: Richard Henderson <richard.henderson@linaro.org>\nSigned-off-by: Alex Bennée <alex.bennee@linaro.org>\n---\n target/arm/syndrome.h | 75 ++++++++++++++++++++++++++++++++-----------\n 1 file changed, 57 insertions(+), 18 deletions(-)", "diff": "diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h\nindex bff61f052cc..517fb2368bc 100644\n--- a/target/arm/syndrome.h\n+++ b/target/arm/syndrome.h\n@@ -25,7 +25,7 @@\n #ifndef TARGET_ARM_SYNDROME_H\n #define TARGET_ARM_SYNDROME_H\n \n-#include \"qemu/bitops.h\"\n+#include \"hw/core/registerfields.h\"\n \n /* Valid Syndrome Register EC field values */\n enum arm_exception_class {\n@@ -76,6 +76,11 @@ enum arm_exception_class {\n EC_AA64_BKPT = 0x3c,\n };\n \n+/* Generic syndrome encoding layout for HSR and lower 32 bits of ESR_EL2 */\n+FIELD(SYNDROME, EC, 26, 6)\n+FIELD(SYNDROME, IL, 25, 1)\n+FIELD(SYNDROME, ISS, 0, 25)\n+\n typedef enum {\n SME_ET_AccessTrap,\n SME_ET_Streaming,\n@@ -113,12 +118,12 @@ typedef enum {\n \n static inline uint32_t syn_get_ec(uint32_t syn)\n {\n- return syn >> ARM_EL_EC_SHIFT;\n+ return FIELD_EX32(syn, SYNDROME, EC);\n }\n \n static inline uint32_t syn_set_ec(uint32_t syn, uint32_t ec)\n {\n- return deposit32(syn, ARM_EL_EC_SHIFT, ARM_EL_EC_LENGTH, ec);\n+ return FIELD_DP32(syn, SYNDROME, EC, ec);\n }\n \n /*\n@@ -133,49 +138,74 @@ static inline uint32_t syn_set_ec(uint32_t syn, uint32_t ec)\n */\n static inline uint32_t syn_uncategorized(void)\n {\n- return (EC_UNCATEGORIZED << ARM_EL_EC_SHIFT) | ARM_EL_IL;\n+ uint32_t res = syn_set_ec(0, EC_UNCATEGORIZED);\n+ res = FIELD_DP32(res, SYNDROME, IL, 1);\n+ return res;\n }\n \n+FIELD(ISS_IMM16, IMM16, 0, 16)\n+\n static inline uint32_t syn_aa64_svc(uint32_t imm16)\n {\n- return (EC_AA64_SVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff);\n+ uint32_t res = syn_set_ec(0, EC_AA64_SVC);\n+ res = FIELD_DP32(res, SYNDROME, IL, 1);\n+ res = FIELD_DP32(res, ISS_IMM16, IMM16, imm16);\n+ return res;\n }\n \n static inline uint32_t syn_aa64_hvc(uint32_t imm16)\n {\n- return (EC_AA64_HVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff);\n+ uint32_t res = syn_set_ec(0, EC_AA64_HVC);\n+ res = FIELD_DP32(res, SYNDROME, IL, 1);\n+ res = FIELD_DP32(res, ISS_IMM16, IMM16, imm16);\n+ return res;\n }\n \n static inline uint32_t syn_aa64_smc(uint32_t imm16)\n {\n- return (EC_AA64_SMC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff);\n+ uint32_t res = syn_set_ec(0, EC_AA64_SMC);\n+ res = FIELD_DP32(res, SYNDROME, IL, 1);\n+ res = FIELD_DP32(res, ISS_IMM16, IMM16, imm16);\n+ return res;\n }\n \n static inline uint32_t syn_aa32_svc(uint32_t imm16, bool is_16bit)\n {\n- return (EC_AA32_SVC << ARM_EL_EC_SHIFT) | (imm16 & 0xffff)\n- | (is_16bit ? 0 : ARM_EL_IL);\n+ uint32_t res = syn_set_ec(0, EC_AA32_SVC);\n+ res = FIELD_DP32(res, SYNDROME, IL, is_16bit ? 0 : 1);\n+ res = FIELD_DP32(res, ISS_IMM16, IMM16, imm16);\n+ return res;\n }\n \n static inline uint32_t syn_aa32_hvc(uint32_t imm16)\n {\n- return (EC_AA32_HVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff);\n+ uint32_t res = syn_set_ec(0, EC_AA32_HVC);\n+ res = FIELD_DP32(res, SYNDROME, IL, 1);\n+ res = FIELD_DP32(res, ISS_IMM16, IMM16, imm16);\n+ return res;\n }\n \n static inline uint32_t syn_aa32_smc(void)\n {\n- return (EC_AA32_SMC << ARM_EL_EC_SHIFT) | ARM_EL_IL;\n+ uint32_t res = syn_set_ec(0, EC_AA32_SMC);\n+ res = FIELD_DP32(res, SYNDROME, IL, 1);\n+ return res;\n }\n \n static inline uint32_t syn_aa64_bkpt(uint32_t imm16)\n {\n- return (EC_AA64_BKPT << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff);\n+ uint32_t res = syn_set_ec(0, EC_AA64_BKPT);\n+ res = FIELD_DP32(res, SYNDROME, IL, 1);\n+ res = FIELD_DP32(res, ISS_IMM16, IMM16, imm16);\n+ return res;\n }\n \n static inline uint32_t syn_aa32_bkpt(uint32_t imm16, bool is_16bit)\n {\n- return (EC_AA32_BKPT << ARM_EL_EC_SHIFT) | (imm16 & 0xffff)\n- | (is_16bit ? 0 : ARM_EL_IL);\n+ uint32_t res = syn_set_ec(0, EC_AA32_BKPT);\n+ res = FIELD_DP32(res, SYNDROME, IL, is_16bit ? 0 : 1);\n+ res = FIELD_DP32(res, ISS_IMM16, IMM16, imm16);\n+ return res;\n }\n \n static inline uint32_t syn_aa64_sysregtrap(int op0, int op1, int op2,\n@@ -246,7 +276,9 @@ static inline uint32_t syn_simd_access_trap(int cv, int cond, bool is_16bit)\n \n static inline uint32_t syn_sve_access_trap(void)\n {\n- return (EC_SVEACCESSTRAP << ARM_EL_EC_SHIFT) | ARM_EL_IL;\n+ uint32_t res = syn_set_ec(0, EC_SVEACCESSTRAP);\n+ res = FIELD_DP32(res, SYNDROME, IL, 1);\n+ return res;\n }\n \n /*\n@@ -361,12 +393,16 @@ static inline uint32_t syn_wfx(int cv, int cond, int ti, bool is_16bit)\n \n static inline uint32_t syn_illegalstate(void)\n {\n- return (EC_ILLEGALSTATE << ARM_EL_EC_SHIFT) | ARM_EL_IL;\n+ uint32_t res = syn_set_ec(0, EC_ILLEGALSTATE);\n+ res = FIELD_DP32(res, SYNDROME, IL, 1);\n+ return res;\n }\n \n static inline uint32_t syn_pcalignment(void)\n {\n- return (EC_PCALIGNMENT << ARM_EL_EC_SHIFT) | ARM_EL_IL;\n+ uint32_t res = syn_set_ec(0, EC_PCALIGNMENT);\n+ res = FIELD_DP32(res, SYNDROME, IL, 1);\n+ return res;\n }\n \n static inline uint32_t syn_gcs_data_check(GCSInstructionType it, int rn)\n@@ -388,7 +424,10 @@ static inline uint32_t syn_gcs_gcsstr(int ra, int rn)\n \n static inline uint32_t syn_serror(uint32_t extra)\n {\n- return (EC_SERROR << ARM_EL_EC_SHIFT) | ARM_EL_IL | extra;\n+ uint32_t res = syn_set_ec(0, EC_SERROR);\n+ res = FIELD_DP32(res, SYNDROME, IL, 1);\n+ res = FIELD_DP32(res, SYNDROME, ISS, extra);\n+ return res;\n }\n \n static inline uint32_t syn_mop(bool is_set, bool is_setg, int options,\n", "prefixes": [ "v2", "01/31" ] }