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GET /api/1.2/patches/2225874/?format=api
{ "id": 2225874, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2225874/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260421-mips-octeon-missing-insns-v2-v2-12-a0791df188c9@gmail.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.2/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260421-mips-octeon-missing-insns-v2-v2-12-a0791df188c9@gmail.com>", "list_archive_url": null, "date": "2026-04-21T17:27:39", "name": "[v2,12/13] target/mips: add Octeon CHORD and LLM COP2 support", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "8ebb4cb5e7760a5dea36a88802e0127a715217be", "submitter": { "id": 66301, "url": "http://patchwork.ozlabs.org/api/1.2/people/66301/?format=api", "name": "James Hilliard", "email": "james.hilliard1@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260421-mips-octeon-missing-insns-v2-v2-12-a0791df188c9@gmail.com/mbox/", "series": [ { "id": 500858, "url": "http://patchwork.ozlabs.org/api/1.2/series/500858/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500858", "date": "2026-04-21T17:27:27", "name": "target/mips: add missing Octeon user-mode support", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/500858/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2225874/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2225874/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=n1tSLFzq;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=\"utf-8\"", "Content-Transfer-Encoding": "8bit", "Message-Id": "\n <20260421-mips-octeon-missing-insns-v2-v2-12-a0791df188c9@gmail.com>", "References": "\n <20260421-mips-octeon-missing-insns-v2-v2-0-a0791df188c9@gmail.com>", "In-Reply-To": "\n <20260421-mips-octeon-missing-insns-v2-v2-0-a0791df188c9@gmail.com>", "To": "qemu-devel@nongnu.org", "Cc": "Laurent Vivier <laurent@vivier.eu>,\n Pierrick Bouvier <pierrick.bouvier@linaro.org>, =?utf-8?q?Philippe_Mathieu?=\n\t=?utf-8?q?-Daud=C3=A9?= <philmd@linaro.org>,\n Aurelien Jarno <aurelien@aurel32.net>,\n Jiaxun Yang <jiaxun.yang@flygoat.com>,\n Aleksandar Rikalo <arikalo@gmail.com>, Huacai Chen <chenhuacai@kernel.org>,\n James Hilliard <james.hilliard1@gmail.com>", "X-Mailer": "b4 0.15.2", "Received-SPF": "pass client-ip=2001:4860:4864:20::29;\n envelope-from=james.hilliard1@gmail.com; helo=mail-oa1-x29.google.com", "X-Spam_score_int": "-17", "X-Spam_score": "-1.8", "X-Spam_bar": "-", "X-Spam_report": "(-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Add the Octeon CHORD hardware register access path and the LLM\nnarrow/wide read and write windows.\n\nModel both CHORD access forms, including the rdhwr $30 path and the\nlegacy dmfc2 alias, and implement sparse backing storage for the two LLM\nsets so user-mode code can save, restore, and probe the architectural\nstate.\n\nSigned-off-by: James Hilliard <james.hilliard1@gmail.com>\n---\nChanges v1 -> v2:\n - Use neutral selector-slot wording for the LLM/CHORD alias comment.\n - Add selector dispatch updates in octeon_translate.c after moving\n COP2 decode out of translate.c. (suggested by Philippe\n Mathieu-Daudé)\n---\n target/mips/cpu.c | 67 +++++++++++++++++++++++++++++++++++\n target/mips/cpu.h | 20 +++++++++++\n target/mips/helper.h | 1 +\n target/mips/internal.h | 3 ++\n target/mips/system/machine.c | 67 +++++++++++++++++++++++++++++++++++\n target/mips/tcg/octeon_crypto.c | 72 ++++++++++++++++++++++++++++++++++++++\n target/mips/tcg/octeon_translate.c | 13 +++++++\n target/mips/tcg/op_helper.c | 6 ++++\n target/mips/tcg/translate.c | 8 +++++\n 9 files changed, 257 insertions(+)", "diff": "diff --git a/target/mips/cpu.c b/target/mips/cpu.c\nindex ec70c10985..ebcb814360 100644\n--- a/target/mips/cpu.c\n+++ b/target/mips/cpu.c\n@@ -27,6 +27,7 @@\n #include \"internal.h\"\n #include \"kvm_mips.h\"\n #include \"qemu/module.h\"\n+#include \"qemu/qtree.h\"\n #include \"system/kvm.h\"\n #include \"system/qtest.h\"\n #include \"hw/core/qdev-properties.h\"\n@@ -183,6 +184,57 @@ static bool mips_cpu_has_work(CPUState *cs)\n \n #include \"cpu-defs.c.inc\"\n \n+static gint mips_octeon_u64_tree_compare(gconstpointer a, gconstpointer b,\n+ gpointer user_data)\n+{\n+ uint64_t av = *(const uint64_t *)a;\n+ uint64_t bv = *(const uint64_t *)b;\n+\n+ return (av > bv) - (av < bv);\n+}\n+\n+QTree *mips_octeon_llm_tree_new(void)\n+{\n+ return q_tree_new_full(mips_octeon_u64_tree_compare,\n+ NULL, g_free, g_free);\n+}\n+\n+uint64_t mips_octeon_llm_load(QTree *tree, uint64_t addr)\n+{\n+ uint64_t key = addr;\n+ uint64_t *value = tree ? q_tree_lookup(tree, &key) : NULL;\n+\n+ return value ? *value : 0;\n+}\n+\n+void mips_octeon_llm_store(QTree **treep, uint64_t addr, uint64_t value)\n+{\n+ uint64_t *key;\n+ uint64_t *stored;\n+\n+ if (!*treep) {\n+ *treep = mips_octeon_llm_tree_new();\n+ }\n+\n+ key = g_new(uint64_t, 1);\n+ stored = g_new(uint64_t, 1);\n+ *key = addr;\n+ *stored = value;\n+ q_tree_replace(*treep, key, stored);\n+}\n+\n+static void mips_octeon_destroy_llm_state(MIPSOcteonCryptoState *crypto)\n+{\n+ if (crypto->llm_narrow) {\n+ q_tree_destroy(crypto->llm_narrow);\n+ crypto->llm_narrow = NULL;\n+ }\n+ if (crypto->llm_wide) {\n+ q_tree_destroy(crypto->llm_wide);\n+ crypto->llm_wide = NULL;\n+ }\n+}\n+\n static void mips_cpu_reset_hold(Object *obj, ResetType type)\n {\n CPUState *cs = CPU(obj);\n@@ -194,6 +246,7 @@ static void mips_cpu_reset_hold(Object *obj, ResetType type)\n mcc->parent_phases.hold(obj, type);\n }\n \n+ mips_octeon_destroy_llm_state(&env->octeon_crypto);\n memset(env, 0, offsetof(CPUMIPSState, end_reset_fields));\n \n /* Reset registers to their default values */\n@@ -248,6 +301,9 @@ static void mips_cpu_reset_hold(Object *obj, ResetType type)\n env->active_fpu.fcr31 = env->cpu_model->CP1_fcr31;\n env->msair = env->cpu_model->MSAIR;\n env->insn_flags = env->cpu_model->insn_flags;\n+ if (env->insn_flags & INSN_OCTEON) {\n+ env->octeon_crypto.chord = 1;\n+ }\n \n #if defined(CONFIG_USER_ONLY)\n env->CP0_Status = (MIPS_HFLAG_UM << CP0St_KSU);\n@@ -264,6 +320,9 @@ static void mips_cpu_reset_hold(Object *obj, ResetType type)\n * hardware registers.\n */\n env->CP0_HWREna |= 0x0000000F;\n+ if (env->insn_flags & INSN_OCTEON) {\n+ env->CP0_HWREna |= 0x40000000u;\n+ }\n if (env->CP0_Config1 & (1 << CP0C1_FP)) {\n env->CP0_Status |= (1 << CP0St_CU1);\n }\n@@ -422,6 +481,13 @@ static void mips_cpu_reset_hold(Object *obj, ResetType type)\n #endif\n }\n \n+static void mips_cpu_finalize(Object *obj)\n+{\n+ MIPSCPU *cpu = MIPS_CPU(obj);\n+\n+ mips_octeon_destroy_llm_state(&cpu->env.octeon_crypto);\n+}\n+\n static void mips_cpu_disas_set_info(const CPUState *cs, disassemble_info *info)\n {\n const MIPSCPU *cpu = MIPS_CPU(cs);\n@@ -636,6 +702,7 @@ static const TypeInfo mips_cpu_type_info = {\n .instance_size = sizeof(MIPSCPU),\n .instance_align = __alignof(MIPSCPU),\n .instance_init = mips_cpu_initfn,\n+ .instance_finalize = mips_cpu_finalize,\n .abstract = true,\n .class_size = sizeof(MIPSCPUClass),\n .class_init = mips_cpu_class_init,\ndiff --git a/target/mips/cpu.h b/target/mips/cpu.h\nindex 8411ef7de4..e4ccb5e1c7 100644\n--- a/target/mips/cpu.h\n+++ b/target/mips/cpu.h\n@@ -11,6 +11,7 @@\n #include \"fpu/softfloat-types.h\"\n #include \"hw/core/clock.h\"\n #include \"mips-defs.h\"\n+#include \"qemu/qtree.h\"\n \n typedef struct CPUMIPSTLBContext CPUMIPSTLBContext;\n \n@@ -609,6 +610,21 @@ typedef enum MIPSOcteonCop2Sel {\n OCTEON_COP2_SEL_SMS4_ENC0 = OCTEON_COP2_SEL_AES_ENC0,\n OCTEON_COP2_SEL_SMS4_DEC_CBC0 = OCTEON_COP2_SEL_AES_DEC_CBC0,\n OCTEON_COP2_SEL_SMS4_DEC0 = OCTEON_COP2_SEL_AES_DEC0,\n+ /*\n+ * Selector 0x0400 is the narrow LLM read selector and is also used as a\n+ * DMFC2 alias for the CHORD POW tag-switch completion bit.\n+ */\n+ OCTEON_COP2_SEL_LLM_READ_ADDR0 = 0x0400,\n+ OCTEON_COP2_SEL_CHORD = OCTEON_COP2_SEL_LLM_READ_ADDR0,\n+ OCTEON_COP2_SEL_LLM_WRITE_ADDR_INTERNAL0 = 0x0401,\n+ OCTEON_COP2_SEL_LLM_DATA0 = 0x0402,\n+ OCTEON_COP2_SEL_LLM_READ64_ADDR0 = 0x0404,\n+ OCTEON_COP2_SEL_LLM_WRITE64_ADDR_INTERNAL0 = 0x0405,\n+ OCTEON_COP2_SEL_LLM_READ_ADDR1 = 0x0408,\n+ OCTEON_COP2_SEL_LLM_WRITE_ADDR_INTERNAL1 = 0x0409,\n+ OCTEON_COP2_SEL_LLM_DATA1 = 0x040a,\n+ OCTEON_COP2_SEL_LLM_READ64_ADDR1 = 0x040c,\n+ OCTEON_COP2_SEL_LLM_WRITE64_ADDR_INTERNAL1 = 0x040d,\n OCTEON_COP2_SEL_CRC_POLYNOMIAL = 0x0200,\n OCTEON_COP2_SEL_CRC_IV = 0x0201,\n OCTEON_COP2_SEL_CRC_LEN = 0x0202,\n@@ -746,6 +762,10 @@ typedef struct MIPSOcteonCryptoState {\n uint32_t zuc_lfsr[16];\n uint32_t zuc_window[3];\n uint32_t zuc_tresult;\n+ uint64_t llm_data[2];\n+ uint64_t chord;\n+ QTree *llm_narrow;\n+ QTree *llm_wide;\n } MIPSOcteonCryptoState;\n \n typedef struct CPUArchState {\ndiff --git a/target/mips/helper.h b/target/mips/helper.h\nindex 899120d0ca..dad91d7451 100644\n--- a/target/mips/helper.h\n+++ b/target/mips/helper.h\n@@ -200,6 +200,7 @@ DEF_HELPER_1(rdhwr_cc, tl, env)\n DEF_HELPER_1(rdhwr_ccres, tl, env)\n DEF_HELPER_1(rdhwr_performance, tl, env)\n DEF_HELPER_1(rdhwr_xnp, tl, env)\n+DEF_HELPER_1(rdhwr_chord, tl, env)\n DEF_HELPER_2(pmon, void, env, int)\n DEF_HELPER_1(wait, void, env)\n \ndiff --git a/target/mips/internal.h b/target/mips/internal.h\nindex 28eb28936b..b40e65864a 100644\n--- a/target/mips/internal.h\n+++ b/target/mips/internal.h\n@@ -93,6 +93,9 @@ extern const int mips_defs_number;\n \n int mips_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);\n int mips_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);\n+QTree *mips_octeon_llm_tree_new(void);\n+uint64_t mips_octeon_llm_load(QTree *tree, uint64_t addr);\n+void mips_octeon_llm_store(QTree **treep, uint64_t addr, uint64_t value);\n \n #define USEG_LIMIT ((target_ulong)(int32_t)0x7FFFFFFFUL)\n #define KSEG0_BASE ((target_ulong)(int32_t)0x80000000UL)\ndiff --git a/target/mips/system/machine.c b/target/mips/system/machine.c\nindex 1176d879eb..1ec94680af 100644\n--- a/target/mips/system/machine.c\n+++ b/target/mips/system/machine.c\n@@ -129,6 +129,69 @@ static const VMStateDescription vmstate_octeon_multiplier_tc = {\n }\n };\n \n+typedef struct OcteonLLMTreePutData {\n+ QEMUFile *f;\n+} OcteonLLMTreePutData;\n+\n+static gboolean put_octeon_llm_tree_entry(gpointer key, gpointer value,\n+ gpointer user_data)\n+{\n+ OcteonLLMTreePutData *data = user_data;\n+\n+ qemu_put_be64(data->f, *(uint64_t *)key);\n+ qemu_put_be64(data->f, *(uint64_t *)value);\n+ return false;\n+}\n+\n+static int put_octeon_llm_tree(QEMUFile *f, void *pv, size_t size,\n+ const VMStateField *field, JSONWriter *vmdesc)\n+{\n+ QTree *tree = *(QTree **)pv;\n+ OcteonLLMTreePutData data = { .f = f };\n+ uint32_t nnodes = tree ? q_tree_nnodes(tree) : 0;\n+\n+ qemu_put_be32(f, nnodes);\n+ if (tree) {\n+ q_tree_foreach(tree, put_octeon_llm_tree_entry, &data);\n+ }\n+\n+ return 0;\n+}\n+\n+static int get_octeon_llm_tree(QEMUFile *f, void *pv, size_t size,\n+ const VMStateField *field)\n+{\n+ QTree **treep = pv;\n+ uint32_t nnodes = qemu_get_be32(f);\n+\n+ if (*treep) {\n+ q_tree_destroy(*treep);\n+ }\n+ *treep = mips_octeon_llm_tree_new();\n+\n+ for (uint32_t i = 0; i < nnodes; i++) {\n+ uint64_t addr = qemu_get_be64(f);\n+ uint64_t value = qemu_get_be64(f);\n+\n+ mips_octeon_llm_store(treep, addr, value);\n+ }\n+\n+ return 0;\n+}\n+\n+static const VMStateInfo vmstate_info_octeon_llm_tree = {\n+ .name = \"octeon_llm_tree\",\n+ .get = get_octeon_llm_tree,\n+ .put = put_octeon_llm_tree,\n+};\n+\n+#define VMSTATE_OCTEON_LLM_TREE(_f, _s) { \\\n+ .name = stringify(_f), \\\n+ .version_id = 1, \\\n+ .info = &vmstate_info_octeon_llm_tree, \\\n+ .offset = vmstate_offset_pointer(_s, _f, QTree), \\\n+}\n+\n /* MVP state */\n \n static const VMStateDescription vmstate_mvp = {\n@@ -306,6 +369,10 @@ static const VMStateDescription mips_vmstate_octeon_crypto = {\n VMSTATE_UINT32_ARRAY(env.octeon_crypto.zuc_lfsr, MIPSCPU, 16),\n VMSTATE_UINT32_ARRAY(env.octeon_crypto.zuc_window, MIPSCPU, 3),\n VMSTATE_UINT32(env.octeon_crypto.zuc_tresult, MIPSCPU),\n+ VMSTATE_UINT64_ARRAY(env.octeon_crypto.llm_data, MIPSCPU, 2),\n+ VMSTATE_UINT64(env.octeon_crypto.chord, MIPSCPU),\n+ VMSTATE_OCTEON_LLM_TREE(env.octeon_crypto.llm_narrow, MIPSCPU),\n+ VMSTATE_OCTEON_LLM_TREE(env.octeon_crypto.llm_wide, MIPSCPU),\n VMSTATE_END_OF_LIST()\n }\n };\ndiff --git a/target/mips/tcg/octeon_crypto.c b/target/mips/tcg/octeon_crypto.c\nindex 9c5f19f41d..3369993fc9 100644\n--- a/target/mips/tcg/octeon_crypto.c\n+++ b/target/mips/tcg/octeon_crypto.c\n@@ -16,6 +16,42 @@\n #include \"qemu/bitops.h\"\n #include \"qemu/host-utils.h\"\n \n+#define OCTEON_LLM_NARROW_MASK ((1ULL << 36) - 1)\n+\n+static uint64_t octeon_llm_pack_narrow(uint64_t value)\n+{\n+ value &= OCTEON_LLM_NARROW_MASK;\n+ return value | ((uint64_t)(ctpop64(value) & 1) << 36);\n+}\n+\n+static void octeon_llm_read(MIPSOcteonCryptoState *crypto, unsigned int set,\n+ uint64_t addr, bool wide)\n+{\n+ uint64_t value;\n+\n+ if (wide) {\n+ value = mips_octeon_llm_load(crypto->llm_wide, addr);\n+ } else {\n+ value = octeon_llm_pack_narrow(\n+ mips_octeon_llm_load(crypto->llm_narrow, addr));\n+ }\n+\n+ crypto->llm_data[set] = value;\n+}\n+\n+static void octeon_llm_write(MIPSOcteonCryptoState *crypto, unsigned int set,\n+ uint64_t addr, bool wide)\n+{\n+ uint64_t value = crypto->llm_data[set];\n+\n+ if (wide) {\n+ mips_octeon_llm_store(&crypto->llm_wide, addr, value);\n+ } else {\n+ mips_octeon_llm_store(&crypto->llm_narrow, addr,\n+ value & OCTEON_LLM_NARROW_MASK);\n+ }\n+}\n+\n static inline void octeon_set_shared_mode(MIPSOcteonCryptoState *crypto,\n MIPSOcteonSharedMode mode)\n {\n@@ -2001,6 +2037,12 @@ uint64_t helper_octeon_cop2_dmfc2(CPUMIPSState *env, uint32_t sel)\n return crypto->crc_len;\n case OCTEON_COP2_SEL_CRC_IV_REFLECT:\n return octeon_crc_reflect32_by_byte(crypto->crc_iv);\n+ case OCTEON_COP2_SEL_CHORD:\n+ return crypto->chord;\n+ case OCTEON_COP2_SEL_LLM_DATA0:\n+ return crypto->llm_data[0];\n+ case OCTEON_COP2_SEL_LLM_DATA1:\n+ return crypto->llm_data[1];\n case OCTEON_COP2_SEL_HSH_DATW0:\n case OCTEON_COP2_SEL_HSH_DATW1:\n case OCTEON_COP2_SEL_HSH_DATW2:\n@@ -2157,6 +2199,36 @@ void helper_octeon_cop2_dmtc2(CPUMIPSState *env, uint64_t value,\n case OCTEON_COP2_SEL_AES_KEYLENGTH:\n crypto->aes_keylen = q;\n break;\n+ case OCTEON_COP2_SEL_LLM_READ_ADDR0:\n+ octeon_llm_read(crypto, 0, q, false);\n+ break;\n+ case OCTEON_COP2_SEL_LLM_WRITE_ADDR_INTERNAL0:\n+ octeon_llm_write(crypto, 0, q, false);\n+ break;\n+ case OCTEON_COP2_SEL_LLM_DATA0:\n+ crypto->llm_data[0] = q;\n+ break;\n+ case OCTEON_COP2_SEL_LLM_READ64_ADDR0:\n+ octeon_llm_read(crypto, 0, q, true);\n+ break;\n+ case OCTEON_COP2_SEL_LLM_WRITE64_ADDR_INTERNAL0:\n+ octeon_llm_write(crypto, 0, q, true);\n+ break;\n+ case OCTEON_COP2_SEL_LLM_READ_ADDR1:\n+ octeon_llm_read(crypto, 1, q, false);\n+ break;\n+ case OCTEON_COP2_SEL_LLM_WRITE_ADDR_INTERNAL1:\n+ octeon_llm_write(crypto, 1, q, false);\n+ break;\n+ case OCTEON_COP2_SEL_LLM_DATA1:\n+ crypto->llm_data[1] = q;\n+ break;\n+ case OCTEON_COP2_SEL_LLM_READ64_ADDR1:\n+ octeon_llm_read(crypto, 1, q, true);\n+ break;\n+ case OCTEON_COP2_SEL_LLM_WRITE64_ADDR_INTERNAL1:\n+ octeon_llm_write(crypto, 1, q, true);\n+ break;\n case OCTEON_COP2_SEL_CAMELLIA_FL:\n octeon_camellia_fl_layer(crypto, q, false);\n break;\ndiff --git a/target/mips/tcg/octeon_translate.c b/target/mips/tcg/octeon_translate.c\nindex 004b937412..d9c5d7ab83 100644\n--- a/target/mips/tcg/octeon_translate.c\n+++ b/target/mips/tcg/octeon_translate.c\n@@ -82,6 +82,9 @@ static bool octeon_cop2_is_supported_dmfc2(uint16_t sel)\n case OCTEON_COP2_SEL_GFM_RESINP0:\n case OCTEON_COP2_SEL_GFM_RESINP1:\n case OCTEON_COP2_SEL_GFM_POLY:\n+ case OCTEON_COP2_SEL_CHORD:\n+ case OCTEON_COP2_SEL_LLM_DATA0:\n+ case OCTEON_COP2_SEL_LLM_DATA1:\n return true;\n default:\n return false;\n@@ -117,6 +120,16 @@ static bool octeon_cop2_is_supported_dmtc2(uint16_t sel)\n case OCTEON_COP2_SEL_AES_KEYLENGTH:\n case OCTEON_COP2_SEL_CAMELLIA_FL:\n case OCTEON_COP2_SEL_CAMELLIA_FLINV:\n+ case OCTEON_COP2_SEL_LLM_READ_ADDR0:\n+ case OCTEON_COP2_SEL_LLM_WRITE_ADDR_INTERNAL0:\n+ case OCTEON_COP2_SEL_LLM_DATA0:\n+ case OCTEON_COP2_SEL_LLM_READ64_ADDR0:\n+ case OCTEON_COP2_SEL_LLM_WRITE64_ADDR_INTERNAL0:\n+ case OCTEON_COP2_SEL_LLM_READ_ADDR1:\n+ case OCTEON_COP2_SEL_LLM_WRITE_ADDR_INTERNAL1:\n+ case OCTEON_COP2_SEL_LLM_DATA1:\n+ case OCTEON_COP2_SEL_LLM_READ64_ADDR1:\n+ case OCTEON_COP2_SEL_LLM_WRITE64_ADDR_INTERNAL1:\n case OCTEON_COP2_SEL_CRC_WRITE_POLYNOMIAL:\n case OCTEON_COP2_SEL_CRC_IV:\n case OCTEON_COP2_SEL_CRC_WRITE_LEN:\ndiff --git a/target/mips/tcg/op_helper.c b/target/mips/tcg/op_helper.c\nindex 47b13a583c..d73ec80af0 100644\n--- a/target/mips/tcg/op_helper.c\n+++ b/target/mips/tcg/op_helper.c\n@@ -354,6 +354,12 @@ target_ulong helper_rdhwr_xnp(CPUMIPSState *env)\n return (env->CP0_Config5 >> CP0C5_XNP) & 1;\n }\n \n+target_ulong helper_rdhwr_chord(CPUMIPSState *env)\n+{\n+ check_hwrena(env, 30, GETPC());\n+ return env->octeon_crypto.chord;\n+}\n+\n void helper_pmon(CPUMIPSState *env, int function)\n {\n function /= 2;\ndiff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c\nindex ca9cee7ed6..183ae940ff 100644\n--- a/target/mips/tcg/translate.c\n+++ b/target/mips/tcg/translate.c\n@@ -10920,6 +10920,14 @@ void gen_rdhwr(DisasContext *ctx, int rt, int rd, int sel)\n }\n break;\n #endif\n+ case 30:\n+ if (!(ctx->insn_flags & INSN_OCTEON)) {\n+ gen_reserved_instruction(ctx);\n+ break;\n+ }\n+ gen_helper_rdhwr_chord(t0, tcg_env);\n+ gen_store_gpr(t0, rt);\n+ break;\n default: /* Invalid */\n MIPS_INVAL(\"rdhwr\");\n gen_reserved_instruction(ctx);\n", "prefixes": [ "v2", "12/13" ] }