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Update a patch.
GET /api/1.2/patches/2225788/?format=api
{ "id": 2225788, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2225788/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20260421-wdt-v1-3-0bd01ec6a7c4@nxp.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/1.2/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260421-wdt-v1-3-0bd01ec6a7c4@nxp.com>", "list_archive_url": null, "date": "2026-04-21T14:01:29", "name": "[v2,3/5] watchdog: ulp_wdog: Use driver model for reset_cpu()", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "d56f226885bac2fe82077e184439bdbd604ca049", "submitter": { "id": 80695, "url": "http://patchwork.ozlabs.org/api/1.2/people/80695/?format=api", "name": "Alice Guo (OSS)", "email": "alice.guo@oss.nxp.com" }, "delegate": { "id": 151988, "url": "http://patchwork.ozlabs.org/api/1.2/users/151988/?format=api", "username": "festevam", "first_name": "Fabio", "last_name": "Estevam", "email": "festevam@gmail.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20260421-wdt-v1-3-0bd01ec6a7c4@nxp.com/mbox/", "series": [ { "id": 500836, "url": "http://patchwork.ozlabs.org/api/1.2/series/500836/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=500836", "date": "2026-04-21T14:01:26", "name": "imx: Switch watchdog addressing from macros to devicetree", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/500836/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2225788/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2225788/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", 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"X-OriginatorOrg": "oss.nxp.com", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 066f7344-3edf-49ac-1eed-08de9fae3915", "X-MS-Exchange-CrossTenant-AuthSource": "PAXPR04MB9644.eurprd04.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Internal", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "21 Apr 2026 13:59:36.5394 (UTC)", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-CrossTenant-Id": "686ea1d3-bc2b-4c6f-a92c-d99c5c301635", "X-MS-Exchange-CrossTenant-MailboxType": "HOSTED", "X-MS-Exchange-CrossTenant-UserPrincipalName": "\n fYM99yZwIc8N7m/oQkhVon0KJ8nwQztMK+STptexY401Kssuslm9ROszL5oQMAZAlDOczuuYxPe3yb5rcESDwg==", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "GV1PR04MB10426", "X-Mailman-Approved-At": "Tue, 21 Apr 2026 17:12:16 +0200", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.39", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.103.8 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "From: Alice Guo <alice.guo@nxp.com>\n\nReplace hardcoded WDOG_BASE_ADDR with driver model based dynamic address\nlookup from device tree.\n\n- Remove hardcoded WDOG_BASE_ADDR from hw_watchdog_* functions\n- Reimplement reset_cpu() using UCLASS_WDT device iteration\n- Add ulp_wdt_expire_now() callback for standard WDT interface\n- Pass wdog register pointer to hw_watchdog_set_timeout()\n\nSigned-off-by: Alice Guo <alice.guo@nxp.com>\n---\n drivers/watchdog/ulp_wdog.c | 79 ++++++++++++++++-----------------------------\n 1 file changed, 28 insertions(+), 51 deletions(-)", "diff": "diff --git a/drivers/watchdog/ulp_wdog.c b/drivers/watchdog/ulp_wdog.c\nindex 83f19dc0e86..e3a89031c44 100644\n--- a/drivers/watchdog/ulp_wdog.c\n+++ b/drivers/watchdog/ulp_wdog.c\n@@ -7,6 +7,7 @@\n #include <asm/io.h>\n #include <asm/arch/imx-regs.h>\n #include <dm.h>\n+#include <linux/delay.h>\n #include <wdt.h>\n \n /*\n@@ -51,11 +52,9 @@ struct ulp_wdt_priv {\n #define CLK_RATE_1KHZ\t\t\t1000\n #define CLK_RATE_32KHZ\t\t\t125\n \n-void hw_watchdog_set_timeout(u16 val)\n+void hw_watchdog_set_timeout(struct wdog_regs *wdog, u16 val)\n {\n \t/* setting timeout value */\n-\tstruct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR;\n-\n \twritel(val, &wdog->toval);\n }\n \n@@ -89,7 +88,7 @@ void ulp_watchdog_init(struct wdog_regs *wdog, u16 timeout)\n \twhile (!(readl(&wdog->cs) & WDGCS_ULK))\n \t\t;\n \n-\thw_watchdog_set_timeout(timeout);\n+\thw_watchdog_set_timeout(wdog, timeout);\n \twritel(0, &wdog->win);\n \n \t/* setting 1-kHz clock source, enable counter running, and clear interrupt */\n@@ -107,57 +106,20 @@ void ulp_watchdog_init(struct wdog_regs *wdog, u16 timeout)\n \tulp_watchdog_reset(wdog);\n }\n \n-void hw_watchdog_reset(void)\n-{\n-\tstruct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR;\n-\n-\tulp_watchdog_reset(wdog);\n-}\n-\n-void hw_watchdog_init(void)\n-{\n-\tstruct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR;\n-\n-\tulp_watchdog_init(wdog, CONFIG_WATCHDOG_TIMEOUT_MSECS);\n-}\n-\n-#if !CONFIG_IS_ENABLED(SYSRESET)\n+#if !CONFIG_IS_ENABLED(SYSRESET) && CONFIG_IS_ENABLED(WDT)\n void reset_cpu(void)\n {\n-\tstruct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR;\n-\tu32 cmd32 = 0;\n-\n-\tif (readl(&wdog->cs) & WDGCS_CMD32EN) {\n-\t\twritel(UNLOCK_WORD, &wdog->cnt);\n-\t\tcmd32 = WDGCS_CMD32EN;\n-\t} else {\n-\t\tdmb();\n-\t\t__raw_writel(UNLOCK_WORD0, &wdog->cnt);\n-\t\t__raw_writel(UNLOCK_WORD1, &wdog->cnt);\n-\t\tdmb();\n-\t}\n+\tstruct udevice *wdt;\n \n-\t/* Wait WDOG Unlock */\n-\twhile (!(readl(&wdog->cs) & WDGCS_ULK))\n-\t\t;\n+\tfor (uclass_first_device(UCLASS_WDT, &wdt);\n+\t wdt;\n+\t uclass_next_device(&wdt)) {\n+\t\tif (!dev_read_enabled(wdt))\n+\t\t\tcontinue;\n \n-\thw_watchdog_set_timeout(5); /* 5ms timeout for general; 40ms timeout for imx93 */\n-\twritel(0, &wdog->win);\n-\n-\t/* enable counter running */\n-\tif (IS_ENABLED(CONFIG_ARCH_IMX9))\n-\t\twritel((cmd32 | WDGCS_WDGE | (WDG_LPO_CLK << 8) | WDOG_CS_PRES |\n-\t\t WDGCS_INT), &wdog->cs);\n-\telse\n-\t\twritel((cmd32 | WDGCS_WDGE | (WDG_LPO_CLK << 8)), &wdog->cs);\n-\n-\t/* Wait WDOG reconfiguration */\n-\twhile (!(readl(&wdog->cs) & WDGCS_RCS))\n-\t\t;\n-\n-\thw_watchdog_reset();\n-\n-\twhile (1);\n+\t\twdt_expire_now(wdt, 0);\n+\t\tbreak;\n+\t}\n }\n #endif\n \n@@ -184,6 +146,20 @@ static int ulp_wdt_reset(struct udevice *dev)\n \treturn 0;\n }\n \n+static int ulp_wdt_expire_now(struct udevice *dev, ulong flags)\n+{\n+\tint ret;\n+\n+\t/* 5ms timeout for all others; 40ms timeout for \"fsl,imx93-wdt\" */\n+\tret = ulp_wdt_start(dev, 5, flags);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tmdelay(50);\n+\n+\treturn 0;\n+}\n+\n static int ulp_wdt_probe(struct udevice *dev)\n {\n \tstruct ulp_wdt_priv *priv = dev_get_priv(dev);\n@@ -202,6 +178,7 @@ static int ulp_wdt_probe(struct udevice *dev)\n static const struct wdt_ops ulp_wdt_ops = {\n \t.start = ulp_wdt_start,\n \t.reset = ulp_wdt_reset,\n+\t.expire_now = ulp_wdt_expire_now,\n };\n \n static const struct udevice_id ulp_wdt_ids[] = {\n", "prefixes": [ "v2", "3/5" ] }