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GET /api/1.2/patches/2225691/?format=api
{ "id": 2225691, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2225691/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20260421-imx8mq-dm-pmic-v1-14-0e2b490542b1@nxp.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/1.2/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260421-imx8mq-dm-pmic-v1-14-0e2b490542b1@nxp.com>", "list_archive_url": null, "date": "2026-04-21T13:41:26", "name": "[14/15] imx8mq: kontron: migrate PITX-IMX8M to DM PMIC framework", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "07456865462ed04cd5357745af5e959c2aa01c41", "submitter": { "id": 80723, "url": "http://patchwork.ozlabs.org/api/1.2/people/80723/?format=api", "name": "Peng Fan", "email": "peng.fan@oss.nxp.com" }, "delegate": { "id": 151988, "url": "http://patchwork.ozlabs.org/api/1.2/users/151988/?format=api", "username": "festevam", "first_name": "Fabio", "last_name": "Estevam", "email": "festevam@gmail.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20260421-imx8mq-dm-pmic-v1-14-0e2b490542b1@nxp.com/mbox/", "series": [ { "id": 500790, "url": "http://patchwork.ozlabs.org/api/1.2/series/500790/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=500790", "date": "2026-04-21T13:41:12", "name": "i.MX8MQ: Convert to DM_PMIC for a few boards", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/500790/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2225691/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2225691/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=NXP1.onmicrosoft.com header.i=@NXP1.onmicrosoft.com\n header.a=rsa-sha256 header.s=selector1-NXP1-onmicrosoft-com\n header.b=gnb5VtT5;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; 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mx.microsoft.com 1; spf=pass\n smtp.mailfrom=oss.nxp.com; dmarc=pass action=none header.from=oss.nxp.com;\n dkim=pass header.d=oss.nxp.com; arc=none", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=NXP1.onmicrosoft.com;\n s=selector1-NXP1-onmicrosoft-com;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=RJYisP5ovy4oECp9Di5amLk/e3tPVxnNruAGOWyUg4I=;\n b=gnb5VtT5PDTJIFGEMh/ph/Xpk7gjJYvH6tf8TgS0PhzIWyE8J3IrkcrrSa1H5N0vW/lml3Ir32OHJDhoYEdpG7kOFCGu44JfIHVovYcIbQaTdgd3yWqU5X1aRlT1fIRQA3lfE0PovV8CbpTBYGJhAatolz+9JPH3zNON7QyOvN88rR0EbCpxncMFYRoSQ/xPO9ICMJViNpf3PPiMJ1l+KN24i/HH4z0ZBZF5Wlz0XcLg1cEzoMCUXn493tCUw2thDUV+96ggelyuwQ85R8NsFtwMGWcY/cf5agsYzlLOMruHySGkTH1VaglWQLmIhYHt2zKAqM/aWRXYu237oR8NHQ==", "From": "\"Peng Fan (OSS)\" <peng.fan@oss.nxp.com>", "Date": "Tue, 21 Apr 2026 21:41:26 +0800", "Subject": "[PATCH 14/15] imx8mq: kontron: migrate PITX-IMX8M to DM PMIC\n framework", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-Id": "<20260421-imx8mq-dm-pmic-v1-14-0e2b490542b1@nxp.com>", "References": "<20260421-imx8mq-dm-pmic-v1-0-0e2b490542b1@nxp.com>", "In-Reply-To": "<20260421-imx8mq-dm-pmic-v1-0-0e2b490542b1@nxp.com>", "To": "\"NXP i.MX U-Boot Team\" <uboot-imx@nxp.com>, u-boot@lists.denx.de,\n kernel@puri.sm", "Cc": "Stefano Babic <sbabic@nabladev.com>, Fabio Estevam <festevam@gmail.com>,\n Tom Rini <trini@konsulko.com>, Yannic Moog <y.moog@phytec.de>,\n Ye Li <ye.li@nxp.com>, Ilias Apalodimas <ilias.apalodimas@linaro.org>,\n Alice Guo <alice.guo@nxp.com>,\n Marek Vasut <marek.vasut+renesas@mailbox.org>,\n Marco Franchi <marcofrk@gmail.com>, Alifer Moraes <alifer.wsdm@gmail.com>,\n \"Lukas F. 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"=?utf-8?q?oadDTR48i1Dnx8mvkbozeNx/VOXr?=\n\t=?utf-8?q?1fzBhgjNFIqm3+j+Os/NbjnB2CKbzJk2zqLcY9y0qymjDCjnw29IvqABUbASSPV7d?=\n\t=?utf-8?q?dGxuxbso6iL4SFjF1k+cGrr4amR+rQbh3lQ9G/urpw+bfNc4nBjjGwq5qFEojTjAe?=\n\t=?utf-8?q?HJ4EI20pCF4mIc1o6Se2iX2llbr3FMrUerBbNIP5tCpYJuNFptnuuFkTjgL5iPGNq?=\n\t=?utf-8?q?GkuWNRYOoW00btXMRsqFRD+J81VJEGqbPZrHjlXrDT8O8d6SdzNthGAV9JWSX8pGo?=\n\t=?utf-8?q?/AFOylktRokAHYiJDLVwoR3bCO975gwEcl0ArpfVjWHivRmaRnwmKm0U/oude8Unf?=\n\t=?utf-8?q?JlieM7oLk7RRQxumLGj6kW3OvriUaU1e+tKdXSV6X/Br0HE7ShFv6VP4q+AoOXx7S?=\n\t=?utf-8?q?0bgTQB75DVYIOg8vso/z+2qAdKbQLKNtX7S5eW6mKKDgbFvKjOkTkJluAyW3fRiCE?=\n\t=?utf-8?q?XupOqfilBXkqIvL0jjS989YclbSdItqsKIpowqyXG6Cr8DEZL5TvFD2kMs/zcXn7u?=\n\t=?utf-8?q?toRI+ztfeJAwhyKmaY+oxcqZ7YP4UJxT49dEjoPCjLPVnwvs7P+hnfMbpWHgF81+A?=\n\t=?utf-8?q?u+PKNdwbQeixxICf/F4xvdBHo+C++zmOvjUTty6I7dTpZ1aJaCIe1jzBz8B2TywAk?=\n\t=?utf-8?q?aeQPE2oo7Z/4MJDMLRK92CHtNfhYv2xKYKIGXfQCMnsy/3yoWB7DXJr9XIXlf2W5/?=\n\t=?utf-8?q?Y45mz2yP747zpZdtZs6q+77tXm1i3v2b31aOXv3i/RHBdY+1UTl2atEXs5RuJlgny?=\n\t=?utf-8?q?RXsrfa2YGwKV5x1MywmVQqWl90CUgsQu6erX4YQjapLJ0Uk2YrPpZfxfIDJMxZFif?=\n\t=?utf-8?q?poeYOqoFQ3yFgZjXiC207SiqJoPQd5ZqxE7UEWbb536l6ux1Ka0ZxQhuWDQP1ykGz?=\n\t=?utf-8?q?imdYzrDigOKFDNgsf9tGW+MomvNfA7zgEKZJOyQdLq4BgSzOlzo0OrGG66xobggRQ?=\n\t=?utf-8?q?sLph7kpMegDcKK1j5RQ4q+WWDNajA6UoGe16NwfD5ahfMAFk9XFcmr3FtrKfMGmBS?=\n\t=?utf-8?q?lrujKzQCqpKVUBI5J0clNE7LSWeSgu8X6FasHzuKa0WHPuwrpGRgsqyPwPBtyT0bL?=\n\t=?utf-8?q?UffIVGk5Z7xKc4+N130F4XL5CENcE+n/ms77Hy8UAW0iYiJz4UCBCZKcUW4KpfHZg?=\n\t=?utf-8?q?8tECaeys9mmnD9r6NCuxK50xPIQZ8UzQ/Azw8DeUQ5exA1TGPcO/FAQt+4A9vfi3u?=\n\t=?utf-8?q?tsn0+h5eP2KxiI5Pzbao+3Wc5Lg7m3AJrgK1tVQq/Nov2H3SfEkk844J9TTFqpJ1j?=\n\t=?utf-8?q?KOsySG2NV1wo01GhEoJglU9wnrN5DAj1CmkFQZKE3ASzU4ktv1C+/cqd0U2YXg546?=\n\t=?utf-8?q?eyAxzqiwPUPeuwGxV8/JxUNH0de4sd1hRpbD73WJr8x48tKj2QP3ArWBE44mkHIfo?=\n\t=?utf-8?q?bzoBtloICf/J3X7SnJOmOclRamsAdZ8YXxnjugoOpJyBnW1U/wzy9gEoEMtxF4AVO?=\n\t=?utf-8?q?A8GQhqZGm+GC3nWAJcJrsKhf4PZALlTHmcJRrw2pDTfM++TWcTaYeZi20MJlxQUlU?=\n\t=?utf-8?q?GJ5CYnW621KPqw5ODykH8LngOrNwVdghw8U9usPUfuwXOUuhKxWUFeLARL266HaFx?=\n\t=?utf-8?q?rNDc6uY5iGq2jVsOvS76ZOSxI6I9DzMNEhBFOP2vOn6JVrNcFcTLRMwrQ3BSlbuJq?=\n\t=?utf-8?q?c0197KCQgw+T442wGJvMA31MLTVJQTFA=3D=3D?=", "X-OriginatorOrg": "oss.nxp.com", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 17a6262d-e24f-44eb-deeb-08de9fa13336", "X-MS-Exchange-CrossTenant-AuthSource": "PAXPR04MB8459.eurprd04.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Internal", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "21 Apr 2026 12:26:23.3108 (UTC)", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-CrossTenant-Id": "686ea1d3-bc2b-4c6f-a92c-d99c5c301635", "X-MS-Exchange-CrossTenant-MailboxType": "HOSTED", "X-MS-Exchange-CrossTenant-UserPrincipalName": "\n 2rf1VYAUGi2VQDt1fFaBhtAAes3IDbI58wyKRe6er1ZK5xE+YdAxnIPci4mEYsN32jqpZMj11m+8RFbQWj51AQ==", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "PAXPR04MB9349", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.39", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.103.8 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "From: Peng Fan <peng.fan@nxp.com>\n\nMigrate the Kontron PITX-IMX8M board from the legacy power framework\nto the DM PMIC infrastructure.\n\nThe SPL power initialization is converted to use DM_PMIC_PFUZE100,\ndropping all legacy I2C, GPIO, pinmux, and MMC setup code that is\nnow handled through the device tree and driver model instead.\n\nKey changes:\n- Switch PFUZE100 access to DM PMIC APIs\n- Enable SPL OF_CONTROL and mark required nodes with bootph*\n- Remove legacy I2C and power configuration\n- Enable SPL DM, pinctrl, regulator, and PMIC support\n- Adjust SPL stack placement for DM usage\n\nSigned-off-by: Peng Fan <peng.fan@nxp.com>\n---\n arch/arm/dts/imx8mq-kontron-pitx-imx8m-u-boot.dtsi | 64 +++++++\n board/kontron/pitx_imx8m/spl.c | 184 ++++-----------------\n configs/kontron_pitx_imx8m_defconfig | 16 +-\n 3 files changed, 100 insertions(+), 164 deletions(-)", "diff": "diff --git a/arch/arm/dts/imx8mq-kontron-pitx-imx8m-u-boot.dtsi b/arch/arm/dts/imx8mq-kontron-pitx-imx8m-u-boot.dtsi\nindex d361f3f5592..7ab7706d7a7 100644\n--- a/arch/arm/dts/imx8mq-kontron-pitx-imx8m-u-boot.dtsi\n+++ b/arch/arm/dts/imx8mq-kontron-pitx-imx8m-u-boot.dtsi\n@@ -2,26 +2,90 @@\n \n #include \"imx8mq-u-boot.dtsi\"\n \n+&aips1 {\n+\tbootph-all;\n+};\n+\n+&gpio2 {\n+\tbootph-pre-ram;\n+};\n+\n+&pinctrl_i2c1 {\n+\tbootph-all;\n+};\n+\n+&i2c1 {\n+\tbootph-all;\n+};\n+\n+&soc {\n+\tbootph-all;\n+\tbootph-pre-ram;\n+};\n+\n+&{/soc@0/bus@30800000/i2c@30a20000/pmic@8} {\n+\tbootph-all;\n+};\n+\n+&{/soc@0/bus@30800000/i2c@30a20000/pmic@8/regulators} {\n+\tbootph-all;\n+};\n+\n+&pinctrl_uart1 {\n+\tbootph-pre-ram;\n+};\n+\n+&uart1 {\n+\tbootph-pre-ram;\n+};\n+\n &usdhc1 {\n+\tbootph-pre-ram;\n \tmmc-hs400-1_8v;\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pinctrl_usdhc1>;\n+};\n+\n+&pinctrl_usdhc1 {\n+\tbootph-pre-ram;\n };\n \n &usdhc2 {\n+\tbootph-pre-ram;\n \tsd-uhs-sdr104;\n \tsd-uhs-ddr50;\n };\n \n+&pinctrl_usdhc2 {\n+\tbootph-pre-ram;\n+};\n+\n+&pinctrl_usdhc2_gpio {\n+\tbootph-pre-ram;\n+};\n+\n+&pinctrl_reg_usdhc2 {\n+\tbootph-pre-ram;\n+};\n+\n+®_usdhc2_vmmc {\n+\tbootph-pre-ram;\n+};\n+\n &uart1 {\n+\tbootph-pre-ram;\n \t/delete-property/ assigned-clocks;\n \t/delete-property/ assigned-clock-parents;\n };\n \n &uart2 {\n+\tbootph-pre-ram;\n \t/delete-property/ assigned-clocks;\n \t/delete-property/ assigned-clock-parents;\n };\n \n &uart3 {\n+\tbootph-pre-ram;\n \t/delete-property/ assigned-clocks;\n \t/delete-property/ assigned-clock-parents;\n };\ndiff --git a/board/kontron/pitx_imx8m/spl.c b/board/kontron/pitx_imx8m/spl.c\nindex b9e864d3f05..0396967fe36 100644\n--- a/board/kontron/pitx_imx8m/spl.c\n+++ b/board/kontron/pitx_imx8m/spl.c\n@@ -2,21 +2,14 @@\n \n #include <config.h>\n #include <errno.h>\n-#include <fsl_esdhc_imx.h>\n #include <hang.h>\n #include <init.h>\n #include <log.h>\n #include <spl.h>\n #include <asm/arch/ddr.h>\n-#include <asm/arch/imx8mq_pins.h>\n #include <asm/arch/sys_proto.h>\n #include <asm/arch/clock.h>\n-#include <asm/io.h>\n-#include <asm/mach-imx/iomux-v3.h>\n-#include <asm/mach-imx/gpio.h>\n-#include <asm/mach-imx/mxc_i2c.h>\n #include <asm/sections.h>\n-#include <linux/delay.h>\n #include <power/pmic.h>\n #include <power/pfuze100_pmic.h>\n \n@@ -50,120 +43,6 @@ static void spl_dram_init(void)\n \tddr_init(dram_timing);\n }\n \n-#define I2C_PAD_CTRL\t(PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)\n-#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)\n-static struct i2c_pads_info i2c_pad_info1 = {\n-\t.scl = {\n-\t\t.i2c_mode = IMX8MQ_PAD_I2C1_SCL__I2C1_SCL | PC,\n-\t\t.gpio_mode = IMX8MQ_PAD_I2C1_SCL__GPIO5_IO14 | PC,\n-\t\t.gp = IMX_GPIO_NR(5, 14),\n-\t},\n-\t.sda = {\n-\t\t.i2c_mode = IMX8MQ_PAD_I2C1_SDA__I2C1_SDA | PC,\n-\t\t.gpio_mode = IMX8MQ_PAD_I2C1_SDA__GPIO5_IO15 | PC,\n-\t\t.gp = IMX_GPIO_NR(5, 15),\n-\t},\n-};\n-\n-#if CONFIG_IS_ENABLED(MMC)\n-#define USDHC2_CD_GPIO\tIMX_GPIO_NR(2, 12)\n-#define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10)\n-#define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19)\n-\n-int board_mmc_getcd(struct mmc *mmc)\n-{\n-\tstruct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;\n-\n-\tswitch (cfg->esdhc_base) {\n-\tcase USDHC1_BASE_ADDR:\n-\t\t/* the eMMC does not have a CD pin */\n-\t\treturn 1;\n-\tcase USDHC2_BASE_ADDR:\n-\t\treturn !gpio_get_value(USDHC2_CD_GPIO);\n-\t}\n-\n-\treturn 0;\n-}\n-\n-#define USDHC_PAD_CTRL\t(PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \\\n-\t\t\t PAD_CTL_FSEL2)\n-#define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_DSE1)\n-\n-static iomux_v3_cfg_t const usdhc1_pads[] = {\n-\tIMX8MQ_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),\n-\tIMX8MQ_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),\n-\tIMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),\n-\tIMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),\n-\tIMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),\n-\tIMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),\n-\tIMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),\n-\tIMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),\n-\tIMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),\n-\tIMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),\n-\tIMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),\n-};\n-\n-static iomux_v3_cfg_t const usdhc2_pads[] = {\n-\tIMX8MQ_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */\n-\tIMX8MQ_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */\n-\tIMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */\n-\tIMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */\n-\tIMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0x16 */\n-\tIMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */\n-\tIMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),\n-\tIMX8MQ_PAD_SD2_RESET_B__GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),\n-};\n-\n-static struct fsl_esdhc_cfg usdhc_cfg[2] = {\n-\t{USDHC1_BASE_ADDR, 0, 8},\n-\t{USDHC2_BASE_ADDR, 0, 4},\n-};\n-\n-int board_mmc_init(struct bd_info *bis)\n-{\n-\tint i, ret;\n-\t/*\n-\t * According to the board_mmc_init() the following map is done:\n-\t * (U-Boot device node) (Physical Port)\n-\t * mmc0 USDHC1\n-\t * mmc1 USDHC2\n-\t */\n-\tfor (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) {\n-\t\tswitch (i) {\n-\t\tcase 0:\n-\t\t\tinit_clk_usdhc(0);\n-\t\t\tusdhc_cfg[0].sdhc_clk = mxc_get_clock(USDHC1_CLK_ROOT);\n-\t\t\timx_iomux_v3_setup_multiple_pads(usdhc1_pads,\n-\t\t\t\t\t\t\t ARRAY_SIZE(usdhc1_pads));\n-\t\t\tgpio_request(USDHC1_PWR_GPIO, \"usdhc1_reset\");\n-\t\t\tgpio_direction_output(USDHC1_PWR_GPIO, 0);\n-\t\t\tudelay(500);\n-\t\t\tgpio_direction_output(USDHC1_PWR_GPIO, 1);\n-\t\t\tbreak;\n-\t\tcase 1:\n-\t\t\tinit_clk_usdhc(1);\n-\t\t\tusdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT);\n-\t\t\timx_iomux_v3_setup_multiple_pads(usdhc2_pads,\n-\t\t\t\t\t\t\t ARRAY_SIZE(usdhc2_pads));\n-\t\t\tgpio_request(USDHC2_PWR_GPIO, \"usdhc2_reset\");\n-\t\t\tgpio_direction_output(USDHC2_PWR_GPIO, 0);\n-\t\t\tudelay(500);\n-\t\t\tgpio_direction_output(USDHC2_PWR_GPIO, 1);\n-\t\t\tbreak;\n-\t\tdefault:\n-\t\t\tprintf(\"Warning: you configured more USDHC controllers \"\n-\t\t\t\t\"(%d) than supported by the board\\n\", i + 1);\n-\t\t\treturn -EINVAL;\n-\t\t}\n-\n-\t\tret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);\n-\t\tif (ret)\n-\t\t\treturn ret;\n-\t}\n-\n-\treturn 0;\n-}\n-\n const char *spl_board_loader_name(u32 boot_device)\n {\n \tswitch (boot_device) {\n@@ -175,18 +54,14 @@ const char *spl_board_loader_name(u32 boot_device)\n \t\treturn NULL;\n \t}\n }\n-#endif\n-\n-#if CONFIG_IS_ENABLED(POWER_LEGACY)\n-#define I2C_PMIC\t0\n \n-static int pfuze_mode_init(struct pmic *p, u32 mode)\n+static int pfuze_mode_init(struct udevice *dev, u32 mode)\n {\n \tunsigned char offset, i, switch_num;\n \tu32 id;\n \tint ret;\n \n-\tpmic_reg_read(p, PFUZE100_DEVICEID, &id);\n+\tid = pmic_reg_read(dev, PFUZE100_DEVICEID);\n \tid = id & 0xf;\n \n \tif (id == 0) {\n@@ -200,14 +75,14 @@ static int pfuze_mode_init(struct pmic *p, u32 mode)\n \t\treturn -EINVAL;\n \t}\n \n-\tret = pmic_reg_write(p, PFUZE100_SW1ABMODE, mode);\n+\tret = pmic_reg_write(dev, PFUZE100_SW1ABMODE, mode);\n \tif (ret < 0) {\n \t\tprintf(\"Set SW1AB mode error!\\n\");\n \t\treturn ret;\n \t}\n \n \tfor (i = 0; i < switch_num - 1; i++) {\n-\t\tret = pmic_reg_write(p, offset + i * SWITCH_SIZE, mode);\n+\t\tret = pmic_reg_write(dev, offset + i * SWITCH_SIZE, mode);\n \t\tif (ret < 0) {\n \t\t\tprintf(\"Set switch 0x%x mode error!\\n\",\n \t\t\t offset + i * SWITCH_SIZE);\n@@ -220,44 +95,45 @@ static int pfuze_mode_init(struct pmic *p, u32 mode)\n \n int power_init_board(void)\n {\n-\tstruct pmic *p;\n+\tstruct udevice *dev;\n+\tint reg;\n \tint ret;\n-\tunsigned int reg;\n \n-\tret = power_pfuze100_init(I2C_PMIC);\n-\tif (ret)\n-\t\treturn -ENODEV;\n-\n-\tp = pmic_get(\"PFUZE100\");\n-\tret = pmic_probe(p);\n-\tif (ret)\n-\t\treturn -ENODEV;\n+\tret = pmic_get(\"pmic@8\", &dev);\n+\tif (ret == -ENODEV) {\n+\t\tputs(\"No pmic@8\\n\");\n+\t\treturn 0;\n+\t}\n+\tif (ret < 0)\n+\t\treturn ret;\n \n-\tpmic_reg_read(p, PFUZE100_SW3AVOL, ®);\n+\treg = pmic_reg_read(dev, PFUZE100_SW3AVOL);\n \tif ((reg & 0x3f) != 0x18) {\n \t\treg &= ~0x3f;\n \t\treg |= 0x18;\n-\t\tpmic_reg_write(p, PFUZE100_SW3AVOL, reg);\n+\t\tpmic_reg_write(dev, PFUZE100_SW3AVOL, reg);\n \t}\n \n-\tret = pfuze_mode_init(p, APS_PFM);\n+\tret = pfuze_mode_init(dev, APS_PFM);\n \tif (ret < 0)\n \t\treturn ret;\n \n \t/* set SW3A standby mode to off */\n-\tpmic_reg_read(p, PFUZE100_SW3AMODE, ®);\n+\treg = pmic_reg_read(dev, PFUZE100_SW3AMODE);\n \treg &= ~0xf;\n \treg |= APS_OFF;\n-\tpmic_reg_write(p, PFUZE100_SW3AMODE, reg);\n+\tpmic_reg_write(dev, PFUZE100_SW3AMODE, reg);\n \n \treturn 0;\n }\n-#endif\n \n void board_init_f(ulong dummy)\n {\n \tint ret;\n \n+\t/* Clear the BSS. */\n+\tmemset(__bss_start, 0, __bss_end - __bss_start);\n+\n \tarch_cpu_init();\n \n \tinit_uart_clk(2);\n@@ -266,26 +142,22 @@ void board_init_f(ulong dummy)\n \n \ttimer_init();\n \n-\tpreloader_console_init();\n-\n-\t/* Clear the BSS. */\n-\tmemset(__bss_start, 0, __bss_end - __bss_start);\n-\n-\tret = spl_init();\n+\tret = spl_early_init();\n \tif (ret) {\n-\t\tdebug(\"spl_init() failed: %d\\n\", ret);\n+\t\tdebug(\"spl_early_init() failed: %d\\n\", ret);\n \t\thang();\n \t}\n \n-\tenable_tzc380();\n+\tpreloader_console_init();\n \n-\tsetup_i2c(0, 100000, 0x7f, &i2c_pad_info1);\n+\tenable_tzc380();\n \n-#if CONFIG_IS_ENABLED(POWER_LEGACY)\n \tpower_init_board();\n-#endif\n \n \tspl_dram_init();\n \n+\tinit_clk_usdhc(0);\n+\tinit_clk_usdhc(1);\n+\n \tboard_init_r(NULL, 0);\n }\ndiff --git a/configs/kontron_pitx_imx8m_defconfig b/configs/kontron_pitx_imx8m_defconfig\nindex 4c0eb48216e..39aeb7bf01c 100644\n--- a/configs/kontron_pitx_imx8m_defconfig\n+++ b/configs/kontron_pitx_imx8m_defconfig\n@@ -7,9 +7,6 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y\n CONFIG_SPL_LIBGENERIC_SUPPORT=y\n CONFIG_ENV_SIZE=0x4000\n CONFIG_ENV_OFFSET=0x300000\n-CONFIG_SYS_I2C_MXC_I2C1=y\n-CONFIG_SYS_I2C_MXC_I2C2=y\n-CONFIG_SYS_I2C_MXC_I2C3=y\n CONFIG_DM_GPIO=y\n CONFIG_DEFAULT_DEVICE_TREE=\"imx8mq-kontron-pitx-imx8m\"\n CONFIG_TARGET_KONTRON_PITX_IMX8M=y\n@@ -18,7 +15,7 @@ CONFIG_SYS_MONITOR_LEN=524288\n CONFIG_SPL_MMC=y\n CONFIG_SPL_SERIAL=y\n CONFIG_SPL_DRIVERS_MISC=y\n-CONFIG_SPL_STACK=0x187ff0\n+CONFIG_SPL_STACK=0x920000\n CONFIG_SPL_TEXT_BASE=0x7E1000\n CONFIG_SPL_HAS_BSS_LINKER_SECTION=y\n CONFIG_SPL_BSS_START_ADDR=0x180000\n@@ -73,16 +70,17 @@ CONFIG_CMD_REGULATOR=y\n CONFIG_CMD_HASH=y\n CONFIG_CMD_EXT4_WRITE=y\n CONFIG_OF_CONTROL=y\n+CONFIG_SPL_OF_CONTROL=y\n CONFIG_ENV_OVERWRITE=y\n CONFIG_ENV_IS_IN_MMC=y\n CONFIG_ENV_RELOC_GD_ENV_ADDR=y\n CONFIG_USE_ETHPRIME=y\n CONFIG_ETHPRIME=\"FEC\"\n+CONFIG_SPL_DM=y\n CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000\n CONFIG_DFU_MMC=y\n CONFIG_MXC_GPIO=y\n CONFIG_DM_I2C=y\n-CONFIG_SPL_SYS_I2C_LEGACY=y\n CONFIG_SUPPORT_EMMC_BOOT=y\n CONFIG_FSL_USDHC=y\n CONFIG_PHYLIB=y\n@@ -94,15 +92,17 @@ CONFIG_MII=y\n CONFIG_PHY=y\n CONFIG_PHY_IMX8MQ_USB=y\n CONFIG_PINCTRL=y\n+CONFIG_SPL_PINCTRL=y\n CONFIG_PINCTRL_IMX8M=y\n-CONFIG_SPL_POWER_LEGACY=y\n CONFIG_POWER_DOMAIN=y\n CONFIG_IMX8M_POWER_DOMAIN=y\n-CONFIG_POWER_PFUZE100=y\n+CONFIG_DM_PMIC=y\n+CONFIG_DM_PMIC_PFUZE100=y\n+CONFIG_SPL_DM_PMIC_PFUZE100=y\n CONFIG_DM_REGULATOR=y\n CONFIG_DM_REGULATOR_FIXED=y\n CONFIG_DM_REGULATOR_GPIO=y\n-CONFIG_SPL_POWER_I2C=y\n+CONFIG_SPL_DM_REGULATOR_GPIO=y\n CONFIG_DM_RTC=y\n CONFIG_RTC_RV8803=y\n CONFIG_DM_SERIAL=y\n", "prefixes": [ "14/15" ] }