Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/1.2/patches/2225622/?format=api
{ "id": 2225622, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2225622/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260421093715.2995067-4-frank.chang@sifive.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.2/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260421093715.2995067-4-frank.chang@sifive.com>", "list_archive_url": null, "date": "2026-04-21T09:37:12", "name": "[v4,3/6] target/riscv: Fix pointer masking PMM field selection logic", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "89cfd2f2f1ef3d589e79f63c7cfb32b14b872f5d", "submitter": { "id": 79604, "url": "http://patchwork.ozlabs.org/api/1.2/people/79604/?format=api", "name": "Frank Chang", "email": "frank.chang@sifive.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260421093715.2995067-4-frank.chang@sifive.com/mbox/", "series": [ { "id": 500769, "url": "http://patchwork.ozlabs.org/api/1.2/series/500769/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500769", "date": "2026-04-21T09:37:09", "name": "Fix Zjpm implementation", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/500769/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2225622/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2225622/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=sifive.com header.i=@sifive.com header.a=rsa-sha256\n header.s=google header.b=gVbrOvas;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g0HNp6NDVz1yJG\n\tfor <incoming@patchwork.ozlabs.org>; Tue, 21 Apr 2026 19:38:50 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1wF7Y4-000097-J0; Tue, 21 Apr 2026 05:37:40 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <frank.chang@sifive.com>)\n id 1wF7Xx-000068-R1\n for qemu-devel@nongnu.org; Tue, 21 Apr 2026 05:37:34 -0400", "from mail-pf1-x433.google.com ([2607:f8b0:4864:20::433])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <frank.chang@sifive.com>)\n id 1wF7Xv-0007rn-PA\n for qemu-devel@nongnu.org; Tue, 21 Apr 2026 05:37:33 -0400", "by mail-pf1-x433.google.com with SMTP id\n d2e1a72fcca58-82f2766905fso1751598b3a.3\n for <qemu-devel@nongnu.org>; Tue, 21 Apr 2026 02:37:31 -0700 (PDT)", "from hsinchu16.internal.sifive.com ([210.176.154.34])\n by smtp.gmail.com with ESMTPSA id\n d2e1a72fcca58-82f8e981be6sm15904589b3a.9.2026.04.21.02.37.27\n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Tue, 21 Apr 2026 02:37:29 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=sifive.com; s=google; t=1776764250; x=1777369050; darn=nongnu.org;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:from:to:cc:subject:date\n :message-id:reply-to;\n bh=PyfgNwxD7uW39nGLmk9krGfH2I0Eiy0mWwuB3E99/8o=;\n b=gVbrOvasM8DnZBsGXzegdfdAIaePtk+I82/7UXZ0Ge7sj34Nl7q9LFeqWBjsJZYzdu\n uB20l7f8P4aVBCe/lZxNfx62JCjvMPY2k+Fyngsq/lsKOSYpywHo78wxMR/EAyzF6MnC\n 5BMA7ceLykKB8UI89F8P4TwecrQNY5Dlpr+1CTGSbIEvYuu+Gs7tpeD95CPCcGmT2Lpo\n Fr3ABuT+FjzzDEBI1sk6w7ewSEl9SgR/5bGRs0pQ9c443lQwo8UsVFym17alROtqfxgs\n zsBHv4TKk0KlxSU2pseSByk78q2BYAJSqC0Dq6uem4W/uc4QGkmeyPQd3hge/Lrh197o\n cXBg==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20251104; t=1776764250; x=1777369050;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from\n :to:cc:subject:date:message-id:reply-to;\n bh=PyfgNwxD7uW39nGLmk9krGfH2I0Eiy0mWwuB3E99/8o=;\n b=q7pXMNU6SXbGhaGs523GgHQuf0BeMTFCa2PcNsH/Iw0en15e4bvUObAUlcf3onTCwd\n TPwFVUo/CSYi7eWgB74t5rxcAjR95+bPC2UmG6LyT1oMOP3eitSViNfqRAyvqQD+ENKO\n B0wNtkJhghiYZEVOAXtPKtuSP36ptpZz+cr8Zvwkv9mE7OvnYViAOumNQR4LmZXq2jzE\n NTWnn1IakVXoxHQC1TFtIfKHPCNYuTW4/2bhI+iHwRwoI6F3KeLKc1r0ZrfcMqhDKp+B\n OAvjo1uIdlC4EvLbVgq+T7eS++8MqGlLiDn3LJoAKk4FNDwlyhN4Flh4ufaKnA1Wj76h\n OVIg==", "X-Gm-Message-State": "AOJu0YyD2YxB7H03tSycH6RYJtJeA1cgs2LX80SX8JVfDlydzhkXdT7O\n NzwGH38TWwmLcKRDHDW90ABXcsnU5fRJr7snfC9i95TVsTCFTGua6beEP3mEL0bEEqV9CbspzE8\n YBoJRbtKdGFUdh6Mc93vIbdvOue0Nj2BobCmLbItnVNCowtKDGPx6vfUS7m0jLFYauqr3Jvn5Ru\n 2vbMIOOTnN81wszAa9ZKW9K7A8WSTLxQoRM/CY3XvArm4TqZ8J", "X-Gm-Gg": "AeBDiet9q0eAmBGI2exWyf8J/+kGr+KVfLc7AswGz4bJlTdLDHY8l+kYEjDpFATQU5O\n nXC6t5tpfaoKFgEKs0AWFY+AJrBAucLn4j5shwTbibxBMZY02EKxz0LtTp1CjWn395WQsGea3Le\n VF9or42QMvinw22RoDaaWtladzzCnmWu11cjNY259Zt7uSzDvLMuueK6M2y/VpBTh70Z3JAooqf\n 2Gk2ZJcZoyVYucH9z3MzUmXHxfCaX6BRmFno3SdFI6qgEQ7DAikMBmTpsb98mT/ey6SQO1DQrkn\n lrBC0Ltn7WiNVvb73Ym4JS9FpMG81mKYkSmIDMuiHZeVyGOYEI1DjyQSe2wDKT09bESj58Jk2ix\n a/NQiTSWbvtllsaCerUChqLwj+YK9sfmBby8k2xsTfBjetBkYsmd6YS+KhKnvy1F43gt4Xitmws\n 8f0nusHEHIaodKIArDdmMVGWfsNmVxXLgkpdVHGmSHEWc14MHm0kKc6Vy1CBCi", "X-Received": "by 2002:a05:6a00:340a:b0:82c:ae0e:dea with SMTP id\n d2e1a72fcca58-82f8c8c39b8mr15692296b3a.32.1776764249647;\n Tue, 21 Apr 2026 02:37:29 -0700 (PDT)", "From": "frank.chang@sifive.com", "To": "qemu-devel@nongnu.org", "Cc": "Palmer Dabbelt <palmer@dabbelt.com>,\n Alistair Francis <alistair.francis@wdc.com>,\n Weiwei Li <liwei1518@gmail.com>,\n Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>,\n Liu Zhiwei <zhiwei_liu@linux.alibaba.com>,\n Chao Liu <chao.liu.zevorn@gmail.com>,\n qemu-riscv@nongnu.org (open list:RISC-V TCG CPUs),\n Frank Chang <frank.chang@sifive.com>,\n Daniel Henrique Barboza <dbarboza@ventanamicro.com>", "Subject": "[PATCH v4 3/6] target/riscv: Fix pointer masking PMM field selection\n logic", "Date": "Tue, 21 Apr 2026 17:37:12 +0800", "Message-ID": "<20260421093715.2995067-4-frank.chang@sifive.com>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260421093715.2995067-1-frank.chang@sifive.com>", "References": "<20260421093715.2995067-1-frank.chang@sifive.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2607:f8b0:4864:20::433;\n envelope-from=frank.chang@sifive.com; helo=mail-pf1-x433.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "From: Frank Chang <frank.chang@sifive.com>\n\nmstatus.MPV only records the previous virtualization state, and does not\naffect pointer masking according to the Zjpm specification.\n\nThis patch rewrites riscv_pm_get_pmm() to follow the architectural\ndefinition of Smmpm, Smnpm, and Ssnpm.\n\nThe resulting PMM selection logic for each mode is summarized below:\n\n * mstatus.MXR = 1: pointer masking disabled\n\n * Smmpm + Smnpm + Ssnpm:\n M-mode: mseccfg.PMM\n S-mode: menvcfg.PMM\n U-mode: senvcfg.PMM\n VS-mode: henvcfg.PMM\n VU-mode: senvcfg.PMM\n\n * Smmpm + Smnpm (RVS implemented):\n M-mode: mseccfg.PMM\n S-mode: menvcfg.PMM\n U/VS/VU: disabled (Ssnpm not present)\n\n * Smmpm + Smnpm (RVS not implemented):\n M-mode: mseccfg.PMM\n U-mode: menvcfg.PMM\n S/VS/VU: disabled (no S-mode)\n\n * Smmpm only:\n M-mode: mseccfg.PMM\n Other existing modes: pointer masking disabled\n\nSigned-off-by: Frank Chang <frank.chang@sifive.com>\nReviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>\n---\n target/riscv/cpu_helper.c | 51 +++++++++++++++++++++++++++++++++------\n 1 file changed, 44 insertions(+), 7 deletions(-)", "diff": "diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c\nindex 513bad21afa..bab4153e53b 100644\n--- a/target/riscv/cpu_helper.c\n+++ b/target/riscv/cpu_helper.c\n@@ -131,13 +131,47 @@ bool riscv_env_smode_dbltrp_enabled(CPURISCVState *env, bool virt)\n #endif\n }\n \n+/*\n+ * Returns the effective PMM field.\n+ *\n+ * @env: CPURISCVState\n+ *\n+ * The PMM field selection logic for each effective privilege mode\n+ * is as follows:\n+ *\n+ * - mstatus.MXR = 1: disabled\n+ *\n+ * - Smmpm + Smnpm + Ssnpm:\n+ * M-mode: mseccfg.PMM\n+ * S-mode: menvcfg.PMM\n+ * U-mode: senvcfg.PMM\n+ * VS-mode: henvcfg.PMM\n+ * VU-mode: senvcfg.PMM\n+ *\n+ * - Smmpm + Smnpm (RVS implemented):\n+ * M-mode: mseccfg.PMM\n+ * S-mode: menvcfg.PMM\n+ * U/VS/VU: disabled (Ssnpm not present)\n+ *\n+ * - Smmpm + Smnpm (RVS not implemented):\n+ * M-mode: mseccfg.PMM\n+ * U-mode: menvcfg.PMM\n+ * S/VS/VU: disabled (no S-mode)\n+ *\n+ * - Smmpm only:\n+ * M-mode: mseccfg.PMM\n+ * Other existing modes: disabled\n+ */\n RISCVPmPmm riscv_pm_get_pmm(CPURISCVState *env)\n {\n #ifndef CONFIG_USER_ONLY\n- int priv_mode = cpu_address_mode(env);\n+ int priv_mode;\n+ bool virt;\n+\n+ riscv_cpu_eff_priv(env, &priv_mode, &virt);\n \n- if (get_field(env->mstatus, MSTATUS_MPRV) &&\n- get_field(env->mstatus, MSTATUS_MXR)) {\n+ if ((priv_mode != PRV_M && get_field(env->mstatus, MSTATUS_MXR)) ||\n+ (virt && get_field(env->vsstatus, MSTATUS_MXR))) {\n return PMM_FIELD_DISABLED;\n }\n \n@@ -149,12 +183,14 @@ RISCVPmPmm riscv_pm_get_pmm(CPURISCVState *env)\n }\n break;\n case PRV_S:\n- if (riscv_cpu_cfg(env)->ext_smnpm) {\n- if (get_field(env->mstatus, MSTATUS_MPV)) {\n- return get_field(env->henvcfg, HENVCFG_PMM);\n- } else {\n+ if (!virt) {\n+ if (riscv_cpu_cfg(env)->ext_smnpm) {\n return get_field(env->menvcfg, MENVCFG_PMM);\n }\n+ } else {\n+ if (riscv_cpu_cfg(env)->ext_ssnpm) {\n+ return get_field(env->henvcfg, HENVCFG_PMM);\n+ }\n }\n break;\n case PRV_U:\n@@ -171,6 +207,7 @@ RISCVPmPmm riscv_pm_get_pmm(CPURISCVState *env)\n default:\n g_assert_not_reached();\n }\n+\n return PMM_FIELD_DISABLED;\n #else\n return PMM_FIELD_DISABLED;\n", "prefixes": [ "v4", "3/6" ] }