Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/1.2/patches/2225601/?format=api
{ "id": 2225601, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2225601/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/ec9c17433b715d3f6aefca0f4713b8cb59b9a76b.1776762022.git.vjardin@free.fr/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/1.2/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<ec9c17433b715d3f6aefca0f4713b8cb59b9a76b.1776762022.git.vjardin@free.fr>", "list_archive_url": null, "date": "2026-04-21T09:04:55", "name": "[v2,1/5] arm: mach-mvebu: armada8k: cpuinfo and SAR", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "73b631fff9089461409242ea5465b5a9c40b2cc4", "submitter": { "id": 89131, "url": "http://patchwork.ozlabs.org/api/1.2/people/89131/?format=api", "name": "Vincent Jardin", "email": "vjardin@free.fr" }, "delegate": { "id": 1696, "url": "http://patchwork.ozlabs.org/api/1.2/users/1696/?format=api", "username": "stroese", "first_name": "Stefan", "last_name": "Roese", "email": "sr@denx.de" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/ec9c17433b715d3f6aefca0f4713b8cb59b9a76b.1776762022.git.vjardin@free.fr/mbox/", "series": [ { "id": 500764, "url": "http://patchwork.ozlabs.org/api/1.2/series/500764/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=500764", "date": "2026-04-21T09:04:54", "name": "NBX10G: Marvell Armada 8040 Nodebox 10G board support", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/500764/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2225601/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2225601/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=free.fr header.i=@free.fr header.a=rsa-sha256\n header.s=smtp-20201208 header.b=O55S5f6Z;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org)", "phobos.denx.de;\n dmarc=pass (p=quarantine dis=none) header.from=free.fr", "phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de", "phobos.denx.de;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=free.fr header.i=@free.fr header.b=\"O55S5f6Z\";\n\tdkim-atps=neutral", "phobos.denx.de;\n dmarc=pass (p=quarantine dis=none) header.from=free.fr", "phobos.denx.de; spf=pass smtp.mailfrom=vjardin@free.fr" ], "Received": [ "from phobos.denx.de (phobos.denx.de\n [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g0GfD3Gwjz1yJG\n\tfor <incoming@patchwork.ozlabs.org>; Tue, 21 Apr 2026 19:05:24 +1000 (AEST)", "from h2850616.stratoserver.net (localhost [IPv6:::1])\n\tby phobos.denx.de (Postfix) with ESMTP id 7A2CF843FA;\n\tTue, 21 Apr 2026 11:05:19 +0200 (CEST)", "by phobos.denx.de (Postfix, from userid 109)\n id AD18B84390; Tue, 21 Apr 2026 11:05:18 +0200 (CEST)", "from smtp6-g21.free.fr (smtp6-g21.free.fr [212.27.42.6])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits))\n (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id 92193843FA\n for <u-boot@lists.denx.de>; Tue, 21 Apr 2026 11:05:16 +0200 (CEST)", "from y14 (unknown [IPv6:2a01:e0a:2af:22b0:6ee8:ae48:54aa:4eff])\n (Authenticated sender: vjardin@free.fr)\n by smtp6-g21.free.fr (Postfix) with ESMTPSA id D73A278051F;\n Tue, 21 Apr 2026 11:05:11 +0200 (CEST)" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED,\n DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,\n RCVD_IN_DNSWL_BLOCKED,RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,\n SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.2", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple; d=free.fr;\n s=smtp-20201208; t=1776762316;\n bh=tMXP17C05OvG5RgO5mS5m0ak4uy0vsSprQnH3bAFcSc=;\n h=From:To:Cc:Subject:Date:In-Reply-To:References:From;\n b=O55S5f6ZoBcMXwWNZZBe4TF778JaL5Jr+qHKpWuo+SV7XPIjO1QcKIKbHH/zDNbFs\n imt+jKILn7ql0RNNmdtBSvNhNDdwExPnvuFNANIATsVJxNwWXSsNtNlvNnyxyzAihF\n Md29yMdJUUs3FTHRbxSlr6pCT5+HRuQccSKe0iKAi1aSx03X2COLuT/enGELUO2Y93\n kshETFlTzmm2uWpMTD9Q3+1uTTm3/cuXCKd8ckg/UxUWB96SEdHt4yeKJlZk8UbnIC\n Scb5khKdoDolbIZfIJq/ko/9CF2nedkWktMRp26xG2c4ARcBr4E77bRWbwSBGyzc2J\n k0B0LfXAcjBqA==", "From": "Vincent Jardin <vjardin@free.fr>", "To": "u-boot@lists.denx.de", "Cc": "Stefan Roese <stefan.roese@mailbox.org>, Tom Rini <trini@konsulko.com>,\n Vincent Jardin <vjardin@free.fr>", "Subject": "[PATCH v2 1/5] arm: mach-mvebu: armada8k: cpuinfo and SAR", "Date": "Tue, 21 Apr 2026 11:04:55 +0200", "Message-ID": "\n <ec9c17433b715d3f6aefca0f4713b8cb59b9a76b.1776762022.git.vjardin@free.fr>", "X-Mailer": "git-send-email 2.53.0", "In-Reply-To": "<cover.1776762022.git.vjardin@free.fr>", "References": "<cover.1776762022.git.vjardin@free.fr>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.39", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.103.8 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "Add CPU information display for Armada 8040 platforms.\n\nThe soc_info.c reads the AP806 Sample-At-Reset (SAR) register to\ndetermine the PLL clock configuration and converts it to actual\nCPU, DDR, and Fabric frequencies using the PLL frequency table.\n\nSigned-off-by: Vincent Jardin <vjardin@free.fr>\nReviewed-by: Stefan Roese <stefan.roese@mailbox.org>\n---\n arch/arm/mach-mvebu/armada8k/Makefile | 2 +-\n arch/arm/mach-mvebu/armada8k/cpu.c | 12 ++\n arch/arm/mach-mvebu/armada8k/soc_info.c | 194 ++++++++++++++++++++++++\n arch/arm/mach-mvebu/armada8k/soc_info.h | 14 ++\n 4 files changed, 221 insertions(+), 1 deletion(-)\n create mode 100644 arch/arm/mach-mvebu/armada8k/soc_info.c\n create mode 100644 arch/arm/mach-mvebu/armada8k/soc_info.h", "diff": "diff --git a/arch/arm/mach-mvebu/armada8k/Makefile b/arch/arm/mach-mvebu/armada8k/Makefile\nindex 0a4756717a3..723239d9894 100644\n--- a/arch/arm/mach-mvebu/armada8k/Makefile\n+++ b/arch/arm/mach-mvebu/armada8k/Makefile\n@@ -2,4 +2,4 @@\n #\n # Copyright (C) 2016 Stefan Roese <sr@denx.de>\n \n-obj-y = cpu.o cache_llc.o dram.o\n+obj-y = cpu.o cache_llc.o dram.o soc_info.o\ndiff --git a/arch/arm/mach-mvebu/armada8k/cpu.c b/arch/arm/mach-mvebu/armada8k/cpu.c\nindex 3eb93c82387..220b32dd025 100644\n--- a/arch/arm/mach-mvebu/armada8k/cpu.c\n+++ b/arch/arm/mach-mvebu/armada8k/cpu.c\n@@ -15,6 +15,8 @@\n #include <asm/armv8/mmu.h>\n #include <mach/fw_info.h>\n \n+#include \"soc_info.h\"\n+\n /* Armada 7k/8k */\n #define MVEBU_RFU_BASE\t\t\t(MVEBU_REGISTER(0x6f0000))\n #define RFU_GLOBAL_SW_RST\t\t(MVEBU_RFU_BASE + 0x84)\n@@ -111,3 +113,13 @@ int mmc_get_env_dev(void)\n \n \treturn CONFIG_ENV_MMC_DEVICE_INDEX;\n }\n+\n+int print_cpuinfo(void)\n+{\n+\tif (!IS_ENABLED(CONFIG_DISPLAY_CPUINFO))\n+\t\treturn 0;\n+\n+\tsoc_print_clock_info();\n+\tsoc_print_soc_info();\n+\treturn 0;\n+}\ndiff --git a/arch/arm/mach-mvebu/armada8k/soc_info.c b/arch/arm/mach-mvebu/armada8k/soc_info.c\nnew file mode 100644\nindex 00000000000..18cc083c0db\n--- /dev/null\n+++ b/arch/arm/mach-mvebu/armada8k/soc_info.c\n@@ -0,0 +1,194 @@\n+// SPDX-License-Identifier: GPL-2.0+\n+/*\n+ * Copyright (C) 2015 Marvell International Ltd.\n+ *\n+ * Marvell Armada 8K SoC info: SAR, Clock frequencies, LLC status\n+ * Ported from Marvell U-Boot 2015.01 to mainline U-Boot.\n+ */\n+\n+#include <config.h>\n+#include <linux/types.h>\n+#include <linux/kernel.h>\n+#include <stdio.h>\n+#include <asm/io.h>\n+#include <asm/arch/soc.h>\n+\n+/* Clock frequency units */\n+#define KHz\t\t\t1000\n+#define MHz\t\t\t1000000\n+#define GHz\t\t\t1000000000\n+\n+/* AP806 SAR (Sample-At-Reset) register */\n+#define AP806_SAR_REG_BASE\t\t(SOC_REGS_PHY_BASE + 0x6F4400)\n+#define SAR_CLOCK_FREQ_MODE_OFFSET\t0\n+#define SAR_CLOCK_FREQ_MODE_MASK\t(0x1f << SAR_CLOCK_FREQ_MODE_OFFSET)\n+\n+/* LLC (Last Level Cache) registers */\n+#define LLC_BASE\t\t\t(SOC_REGS_PHY_BASE + 0x8000)\n+#define LLC_CTRL\t\t\t0x100\n+#define LLC_CTRL_EN\t\t\t0x1\n+#define LLC_EXCLUSIVE_EN\t\t0x100\n+\n+/* MSS clock is fixed at 200MHz on AP806 */\n+#define AP806_MSS_CLOCK\t\t\t(200 * MHz)\n+\n+/* Clock ID indices in PLL frequency table */\n+#define CPU_CLOCK_ID\t0\n+#define DDR_CLOCK_ID\t1\n+#define RING_CLOCK_ID\t2\n+\n+/* Clocking options (SAR field values) */\n+enum clocking_options {\n+\tCPU_2000_DDR_1200_RCLK_1200 = 0x0,\n+\tCPU_2000_DDR_1050_RCLK_1050 = 0x1,\n+\tCPU_1600_DDR_800_RCLK_800 = 0x4,\n+\tCPU_1800_DDR_1200_RCLK_1200 = 0x6,\n+\tCPU_1800_DDR_1050_RCLK_1050 = 0x7,\n+\tCPU_1600_DDR_900_RCLK_900 = 0x0b,\n+\tCPU_1600_DDR_1050_RCLK_1050 = 0x0d,\n+\tCPU_1600_DDR_900_RCLK_900_2 = 0x0e,\n+\tCPU_1000_DDR_650_RCLK_650 = 0x13,\n+\tCPU_1300_DDR_800_RCLK_800 = 0x14,\n+\tCPU_1300_DDR_650_RCLK_650 = 0x17,\n+\tCPU_1200_DDR_800_RCLK_800 = 0x19,\n+\tCPU_1400_DDR_800_RCLK_800 = 0x1a,\n+\tCPU_600_DDR_800_RCLK_800 = 0x1b,\n+\tCPU_800_DDR_800_RCLK_800 = 0x1c,\n+\tCPU_1000_DDR_800_RCLK_800 = 0x1d,\n+};\n+\n+/*\n+ * PLL frequency table: maps SAR clock mode to actual frequencies.\n+ * Format: { CPU_freq, DDR_freq, RING_freq, SAR_value }\n+ */\n+static const u32 pll_freq_tbl[16][4] = {\n+\t/* CPU */\t/* DDR */\t/* Ring */\n+\t{2000 * MHz,\t1200 * MHz,\t1200 * MHz,\tCPU_2000_DDR_1200_RCLK_1200},\n+\t{2000 * MHz,\t1050 * MHz,\t1050 * MHz,\tCPU_2000_DDR_1050_RCLK_1050},\n+\t{1800 * MHz,\t1200 * MHz,\t1200 * MHz,\tCPU_1800_DDR_1200_RCLK_1200},\n+\t{1800 * MHz,\t1050 * MHz,\t1050 * MHz,\tCPU_1800_DDR_1050_RCLK_1050},\n+\t{1600 * MHz,\t1050 * MHz,\t1050 * MHz,\tCPU_1600_DDR_1050_RCLK_1050},\n+\t{1600 * MHz,\t900 * MHz,\t900 * MHz,\tCPU_1600_DDR_900_RCLK_900_2},\n+\t{1300 * MHz,\t800 * MHz,\t800 * MHz,\tCPU_1300_DDR_800_RCLK_800},\n+\t{1300 * MHz,\t650 * MHz,\t650 * MHz,\tCPU_1300_DDR_650_RCLK_650},\n+\t{1600 * MHz,\t800 * MHz,\t800 * MHz,\tCPU_1600_DDR_800_RCLK_800},\n+\t{1600 * MHz,\t900 * MHz,\t900 * MHz,\tCPU_1600_DDR_900_RCLK_900},\n+\t{1000 * MHz,\t650 * MHz,\t650 * MHz,\tCPU_1000_DDR_650_RCLK_650},\n+\t{1200 * MHz,\t800 * MHz,\t800 * MHz,\tCPU_1200_DDR_800_RCLK_800},\n+\t{1400 * MHz,\t800 * MHz,\t800 * MHz,\tCPU_1400_DDR_800_RCLK_800},\n+\t{600 * MHz,\t800 * MHz,\t800 * MHz,\tCPU_600_DDR_800_RCLK_800},\n+\t{800 * MHz,\t800 * MHz,\t800 * MHz,\tCPU_800_DDR_800_RCLK_800},\n+\t{1000 * MHz,\t800 * MHz,\t800 * MHz,\tCPU_1000_DDR_800_RCLK_800}\n+};\n+\n+/*\n+ * Get the clock frequency mode index from SAR register.\n+ * Returns index into pll_freq_tbl, or -1 if not found.\n+ */\n+static int sar_get_clock_freq_mode(void)\n+{\n+\tu32 i;\n+\tu32 clock_freq;\n+\n+\tclock_freq = (readl(AP806_SAR_REG_BASE) & SAR_CLOCK_FREQ_MODE_MASK)\n+\t\t\t>> SAR_CLOCK_FREQ_MODE_OFFSET;\n+\n+\tfor (i = 0; i < ARRAY_SIZE(pll_freq_tbl); i++) {\n+\t\tif (pll_freq_tbl[i][3] == clock_freq)\n+\t\t\treturn i;\n+\t}\n+\n+\tpr_err(\"SAR: unsupported clock freq mode %d\\n\", clock_freq);\n+\treturn -1;\n+}\n+\n+/*\n+ * Get CPU clock frequency in Hz.\n+ */\n+static u32 soc_cpu_clk_get(void)\n+{\n+\tint mode = sar_get_clock_freq_mode();\n+\n+\tif (mode < 0)\n+\t\treturn 0;\n+\treturn pll_freq_tbl[mode][CPU_CLOCK_ID];\n+}\n+\n+/*\n+ * Get DDR clock frequency in Hz.\n+ */\n+static u32 soc_ddr_clk_get(void)\n+{\n+\tint mode = sar_get_clock_freq_mode();\n+\n+\tif (mode < 0)\n+\t\treturn 0;\n+\treturn pll_freq_tbl[mode][DDR_CLOCK_ID];\n+}\n+\n+/*\n+ * Get Ring (Fabric) clock frequency in Hz.\n+ */\n+static u32 soc_ring_clk_get(void)\n+{\n+\tint mode = sar_get_clock_freq_mode();\n+\n+\tif (mode < 0)\n+\t\treturn 0;\n+\treturn pll_freq_tbl[mode][RING_CLOCK_ID];\n+}\n+\n+/*\n+ * Get MSS clock frequency in Hz.\n+ */\n+static u32 soc_mss_clk_get(void)\n+{\n+\treturn AP806_MSS_CLOCK;\n+}\n+\n+/*\n+ * Get LLC status and mode.\n+ * Returns 1 if LLC is enabled, 0 otherwise.\n+ * If excl_mode is not NULL, sets it to 1 if exclusive mode is enabled.\n+ */\n+static int llc_mode_get(int *excl_mode)\n+{\n+\tu32 val;\n+\tint ret = 0, excl = 0;\n+\n+\tval = readl(LLC_BASE + LLC_CTRL);\n+\tif (val & LLC_CTRL_EN) {\n+\t\tret = 1;\n+\t\tif (val & LLC_EXCLUSIVE_EN)\n+\t\t\texcl = 1;\n+\t}\n+\tif (excl_mode)\n+\t\t*excl_mode = excl;\n+\n+\treturn ret;\n+}\n+\n+/*\n+ * Print SoC clock information.\n+ */\n+void soc_print_clock_info(void)\n+{\n+\tprintf(\"Clock: CPU %-4d [MHz]\\n\", soc_cpu_clk_get() / MHz);\n+\tprintf(\"\\tDDR %-4d [MHz]\\n\", soc_ddr_clk_get() / MHz);\n+\tprintf(\"\\tFABRIC %-4d [MHz]\\n\", soc_ring_clk_get() / MHz);\n+\tprintf(\"\\tMSS %-4d [MHz]\\n\", soc_mss_clk_get() / MHz);\n+}\n+\n+/*\n+ * Print SoC-specific information: DDR width and LLC status.\n+ */\n+void soc_print_soc_info(void)\n+{\n+\tint llc_en, llc_excl_mode;\n+\n+\tprintf(\"\\tDDR 64 Bit width\\n\");\n+\n+\tllc_en = llc_mode_get(&llc_excl_mode);\n+\tprintf(\"\\tLLC %s%s\\n\", llc_en ? \"Enabled\" : \"Disabled\",\n+\t llc_excl_mode ? \" (Exclusive Mode)\" : \"\");\n+}\ndiff --git a/arch/arm/mach-mvebu/armada8k/soc_info.h b/arch/arm/mach-mvebu/armada8k/soc_info.h\nnew file mode 100644\nindex 00000000000..41afe7a2508\n--- /dev/null\n+++ b/arch/arm/mach-mvebu/armada8k/soc_info.h\n@@ -0,0 +1,14 @@\n+/* SPDX-License-Identifier: GPL-2.0+ */\n+/*\n+ * Copyright (C) 2015 Marvell International Ltd.\n+ *\n+ * Marvell Armada 8K SoC info functions\n+ */\n+\n+#ifndef _ARMADA8K_SOC_INFO_H_\n+#define _ARMADA8K_SOC_INFO_H_\n+\n+void soc_print_clock_info(void);\n+void soc_print_soc_info(void);\n+\n+#endif /* _ARMADA8K_SOC_INFO_H_ */\n", "prefixes": [ "v2", "1/5" ] }