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GET /api/1.2/patches/2225503/?format=api
{ "id": 2225503, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2225503/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260421053140.752059-13-joel@jms.id.au/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.2/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260421053140.752059-13-joel@jms.id.au>", "list_archive_url": null, "date": "2026-04-21T05:31:37", "name": "[v3,12/13] hw/riscv/atlantis: Integrate i2c buses", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "e23b9054311d87a5ba3ad688701c83f888ddbc30", "submitter": { "id": 48628, "url": "http://patchwork.ozlabs.org/api/1.2/people/48628/?format=api", "name": "Joel Stanley", "email": "joel@jms.id.au" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260421053140.752059-13-joel@jms.id.au/mbox/", "series": [ { "id": 500733, "url": "http://patchwork.ozlabs.org/api/1.2/series/500733/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500733", "date": "2026-04-21T05:31:26", "name": "hw/riscv: Add the Tenstorrent Atlantis machine", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/500733/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2225503/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2225503/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=KQCCizHq;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g09zp2fh8z1yCv\n\tfor <incoming@patchwork.ozlabs.org>; Tue, 21 Apr 2026 15:35:18 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1wF3kP-0000wQ-Dr; Tue, 21 Apr 2026 01:34:09 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <joel.stan@gmail.com>)\n id 1wF3kH-0000g6-SG\n for qemu-devel@nongnu.org; Tue, 21 Apr 2026 01:34:04 -0400", "from mail-pj1-x1033.google.com ([2607:f8b0:4864:20::1033])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <joel.stan@gmail.com>)\n id 1wF3kG-0004Zq-3H\n for qemu-devel@nongnu.org; Tue, 21 Apr 2026 01:34:01 -0400", "by mail-pj1-x1033.google.com with SMTP id\n 98e67ed59e1d1-35d99031e4eso2578667a91.1\n for <qemu-devel@nongnu.org>; Mon, 20 Apr 2026 22:33:58 -0700 (PDT)", "from donnager-debian.. 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"AeBDieto/B359E+uhfv7E1d6XFomtIpm4/v/JKMzYZTOz/Ljo4cSC0EIXGOdJ7BonlH\n uOSffR+cnxJBBVH0m1T5CCChmAX/9h6Eji6t1y3GYH9cMCqLoBo8kK29yahJeqI1LeK7SGQNwiL\n bnHxXVLnYu+kzv7RxR5OVlLB0jC8h22E1m3s+To/nkfqKaNCnq4hqOrnFTN4K9apgp0qoRBxbbt\n khd4YEG+7DjLj/0YzETh8EndFjbGWC13NyVe6h+fZ5iHILxbiZIbjkIgEfAr+47Tqq+ZKzDWf/1\n zczHMmOaXReZvUWaS64ibTbAPRLO9mToh2aptv9h3Y/fGY7A5K6G3xUFkKijD09KIDhasYarmCk\n MRAHHACdl/xcNgk6IW2sZjc/Dxrr8aFd53ZkjBOgMmliSZIcsNnHrWKZAPe7cRgTh3CL9hBmNgf\n HVO1xfsunGjElzFIwZC+iHoIYlJa+s9HhI5rXjK/L80FvQfjhwKJfqTsISfApDkTYZyUGZ87gdT\n cwagAv3qjCrvNRZi2rlbNr/5xLyaCldr9Yk9w==", "X-Received": "by 2002:a17:90b:3808:b0:35f:b572:ece9 with SMTP id\n 98e67ed59e1d1-361403bdcccmr18220616a91.5.1776749637755;\n Mon, 20 Apr 2026 22:33:57 -0700 (PDT)", "From": "Joel Stanley <joel@jms.id.au>", "To": "Alistair Francis <alistair.francis@wdc.com>,\n Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>", "Cc": "Michael Ellerman <mpe@kernel.org>, Nicholas Piggin <npiggin@gmail.com>,\n Joel Stanley <jms@oss.tenstorrent.com>,\n Anirudh Srinivasan <asrinivasan@oss.tenstorrent.com>,\n qemu-riscv@nongnu.org, qemu-devel@nongnu.org", "Subject": "[PATCH v3 12/13] hw/riscv/atlantis: Integrate i2c buses", "Date": "Tue, 21 Apr 2026 15:31:37 +1000", "Message-ID": "<20260421053140.752059-13-joel@jms.id.au>", "X-Mailer": "git-send-email 2.47.3", "In-Reply-To": "<20260421053140.752059-1-joel@jms.id.au>", "References": "<20260421053140.752059-1-joel@jms.id.au>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2607:f8b0:4864:20::1033;\n envelope-from=joel.stan@gmail.com; helo=mail-pj1-x1033.google.com", "X-Spam_score_int": "-16", "X-Spam_score": "-1.7", "X-Spam_bar": "-", "X-Spam_report": "(-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.001,\n FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=no autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Now that we have the DesignWare model we can add buses to the\ntt-atlantis machine.\n\nProvide a fixed clock in the device tree so that the Linux driver probes\nwithout WARNing.\n\nSigned-off-by: Joel Stanley <joel@jms.id.au>\n---\nv3:\n - Add device tree clock\nv2:\n - Correct count from 4 to 5\n - Fix headers location\n - Use HWADDR_PRIX to be consistent\n---\n include/hw/riscv/tt_atlantis.h | 13 +++++++++\n hw/riscv/tt_atlantis.c | 53 ++++++++++++++++++++++++++++++++++\n hw/riscv/Kconfig | 1 +\n 3 files changed, 67 insertions(+)", "diff": "diff --git a/include/hw/riscv/tt_atlantis.h b/include/hw/riscv/tt_atlantis.h\nindex c0a0827a5167..b39c7e090e0b 100644\n--- a/include/hw/riscv/tt_atlantis.h\n+++ b/include/hw/riscv/tt_atlantis.h\n@@ -11,12 +11,15 @@\n \n #include \"hw/core/boards.h\"\n #include \"hw/core/sysbus.h\"\n+#include \"hw/i2c/designware_i2c.h\"\n #include \"hw/intc/riscv_imsic.h\"\n #include \"hw/riscv/riscv_hart.h\"\n \n #define TYPE_TT_ATLANTIS_MACHINE MACHINE_TYPE_NAME(\"tt-atlantis\")\n OBJECT_DECLARE_SIMPLE_TYPE(TTAtlantisState, TT_ATLANTIS_MACHINE)\n \n+#define TT_ATL_NUM_I2C 5\n+\n struct TTAtlantisState {\n /*< private >*/\n MachineState parent;\n@@ -29,12 +32,18 @@ struct TTAtlantisState {\n RISCVHartArrayState soc;\n DeviceState *irqchip;\n GPEXHost gpex_host;\n+ DesignWareI2CState i2c[TT_ATL_NUM_I2C];\n \n int fdt_size;\n };\n \n enum {\n TT_ATL_SYSCON_IRQ = 10,\n+ TT_ATL_I2C0_IRQ = 33,\n+ TT_ATL_I2C1_IRQ = 34,\n+ TT_ATL_I2C2_IRQ = 35,\n+ TT_ATL_I2C3_IRQ = 36,\n+ TT_ATL_I2C4_IRQ = 37,\n TT_ATL_UART0_IRQ = 38,\n TT_ATL_UART1_IRQ = 39,\n TT_ATL_UART2_IRQ = 40,\n@@ -50,6 +59,10 @@ enum {\n TT_ATL_DDR_HI,\n TT_ATL_FW_CFG,\n TT_ATL_I2C0,\n+ TT_ATL_I2C1,\n+ TT_ATL_I2C2,\n+ TT_ATL_I2C3,\n+ TT_ATL_I2C4,\n TT_ATL_MAPLIC,\n TT_ATL_MIMSIC,\n TT_ATL_PCIE_ECAM0,\ndiff --git a/hw/riscv/tt_atlantis.c b/hw/riscv/tt_atlantis.c\nindex e1753d3c1f18..bf08b7ed320e 100644\n--- a/hw/riscv/tt_atlantis.c\n+++ b/hw/riscv/tt_atlantis.c\n@@ -64,6 +64,11 @@ static const MemMapEntry tt_atlantis_memmap[] = {\n [TT_ATL_TIMER] = { 0xa8020000, 0x10000 },\n [TT_ATL_WDT0] = { 0xa8030000, 0x10000 },\n [TT_ATL_UART0] = { 0xb0100000, 0x10000 },\n+ [TT_ATL_I2C0] = { 0xb0400000, 0x10000 },\n+ [TT_ATL_I2C1] = { 0xb0500000, 0x10000 },\n+ [TT_ATL_I2C2] = { 0xb0600000, 0x10000 },\n+ [TT_ATL_I2C3] = { 0xb0700000, 0x10000 },\n+ [TT_ATL_I2C4] = { 0xb0800000, 0x10000 },\n [TT_ATL_MAPLIC] = { 0xcc000000, 0x4000000 },\n [TT_ATL_SAPLIC] = { 0xe8000000, 0x4000000 },\n [TT_ATL_DDR_HI] = { 0x100000000, 0x1000000000 },\n@@ -475,10 +480,36 @@ static void create_fdt_fw_cfg(void *fdt, const MemMapEntry *mem)\n qemu_fdt_setprop(fdt, name, \"dma-coherent\", NULL, 0);\n }\n \n+static void create_fdt_clk(void *fdt, const char *name, uint32_t clk_phandle)\n+{\n+ qemu_fdt_add_subnode(fdt, name);\n+ qemu_fdt_setprop_string(fdt, name, \"compatible\", \"fixed-clock\");\n+ qemu_fdt_setprop_cell(fdt, name, \"#clock-cells\", 0);\n+ qemu_fdt_setprop_cell(fdt, name, \"clock-frequency\", 100000000);\n+ qemu_fdt_setprop_cell(fdt, name, \"phandle\", clk_phandle);\n+}\n+\n+static void create_fdt_i2c(void *fdt, const MemMapEntry *mem, uint32_t irq,\n+ uint32_t irqchip_phandle, uint32_t clk_phandle)\n+{\n+ g_autofree char *name = g_strdup_printf(\"/soc/i2c@%\"HWADDR_PRIX, mem->base);\n+\n+ qemu_fdt_add_subnode(fdt, name);\n+ qemu_fdt_setprop_string(fdt, name, \"compatible\", \"snps,designware-i2c\");\n+ qemu_fdt_setprop_sized_cells(fdt, name, \"reg\", 2, mem->base, 2, mem->size);\n+ qemu_fdt_setprop_cell(fdt, name, \"interrupt-parent\", irqchip_phandle);\n+ qemu_fdt_setprop_cells(fdt, name, \"interrupts\", irq, 0x4);\n+ qemu_fdt_setprop_cell(fdt, name, \"clocks\", clk_phandle);\n+ qemu_fdt_setprop_cell(fdt, name, \"clock-frequency\", 100000);\n+ qemu_fdt_setprop_cell(fdt, name, \"#address-cells\", 1);\n+ qemu_fdt_setprop_cell(fdt, name, \"#size-cells\", 0);\n+}\n+\n static void finalize_fdt(TTAtlantisState *s)\n {\n uint32_t aplic_s_phandle = next_phandle();\n uint32_t imsic_s_phandle = next_phandle();\n+ uint32_t periph_clk_phandle = next_phandle();\n void *fdt = MACHINE(s)->fdt;\n \n create_fdt_cpu(s, s->memmap, aplic_s_phandle, imsic_s_phandle);\n@@ -502,6 +533,15 @@ static void finalize_fdt(TTAtlantisState *s)\n \n create_fdt_uart(fdt, &s->memmap[TT_ATL_UART0], TT_ATL_UART0_IRQ,\n aplic_s_phandle);\n+\n+ create_fdt_clk(fdt, \"/periph-clk\", periph_clk_phandle);\n+\n+ for (int i = 0; i < TT_ATL_NUM_I2C; i++) {\n+ create_fdt_i2c(fdt,\n+ &s->memmap[TT_ATL_I2C0 + i],\n+ TT_ATL_I2C0_IRQ + i,\n+ aplic_s_phandle, periph_clk_phandle);\n+ }\n }\n \n static void create_fdt(TTAtlantisState *s)\n@@ -818,6 +858,19 @@ static void tt_atlantis_machine_init(MachineState *machine)\n qdev_get_gpio_in(s->irqchip, TT_ATL_UART0_IRQ),\n 115200, serial_hd(0), DEVICE_LITTLE_ENDIAN);\n \n+ /* I2C */\n+ for (int i = 0; i < TT_ATL_NUM_I2C; i++) {\n+ object_initialize_child(OBJECT(s), \"i2c[*]\", &s->i2c[i],\n+ TYPE_DESIGNWARE_I2C);\n+ sysbus_realize(SYS_BUS_DEVICE(&s->i2c[i]), &error_fatal);\n+ SysBusDevice *sbd = SYS_BUS_DEVICE(&s->i2c[i]);\n+ memory_region_add_subregion(system_memory,\n+ s->memmap[TT_ATL_I2C0 + i].base,\n+ sysbus_mmio_get_region(sbd, 0));\n+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0,\n+ qdev_get_gpio_in(s->irqchip, TT_ATL_I2C0_IRQ + i));\n+ }\n+\n /* Load or create device tree */\n if (machine->dtb) {\n machine->fdt = load_device_tree(machine->dtb, &s->fdt_size);\ndiff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig\nindex 2ddee591eb90..4c2cf01995e7 100644\n--- a/hw/riscv/Kconfig\n+++ b/hw/riscv/Kconfig\n@@ -136,6 +136,7 @@ config TENSTORRENT\n select RISCV_APLIC\n select RISCV_IMSIC\n select FW_CFG_DMA\n+ select DESIGNWARE_I2C\n \n config XIANGSHAN_KUNMINGHU\n bool\n", "prefixes": [ "v3", "12/13" ] }