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GET /api/1.2/patches/2225468/?format=api
{ "id": 2225468, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2225468/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260421051346.41106-27-richard.henderson@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.2/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260421051346.41106-27-richard.henderson@linaro.org>", "list_archive_url": null, "date": "2026-04-21T05:13:35", "name": "[26/37] target/arm: Implement BF1CVT, BF1CVTL, BF2CVT, BF2CVTL for SME", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "6b164afbb9b9f2eb0240b3f87d444c74a71da1f4", "submitter": { "id": 72104, "url": "http://patchwork.ozlabs.org/api/1.2/people/72104/?format=api", "name": "Richard Henderson", "email": "richard.henderson@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260421051346.41106-27-richard.henderson@linaro.org/mbox/", "series": [ { "id": 500729, "url": "http://patchwork.ozlabs.org/api/1.2/series/500729/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500729", "date": "2026-04-21T05:13:11", "name": "target/arm: Implement FEAT_FAMINMAX, FEAT_FPMR, FEAT_FP8", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/500729/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2225468/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2225468/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=CICDkrqR;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g09dV1TlZz1yJG\n\tfor <incoming@patchwork.ozlabs.org>; Tue, 21 Apr 2026 15:19:26 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1wF3Sb-0000Vi-Fa; Tue, 21 Apr 2026 01:15:45 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <richard.henderson@linaro.org>)\n id 1wF3Rq-0008C5-Fz\n for qemu-devel@nongnu.org; Tue, 21 Apr 2026 01:14:58 -0400", "from mail-pl1-x632.google.com ([2607:f8b0:4864:20::632])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <richard.henderson@linaro.org>)\n id 1wF3Rn-0006eP-AD\n for qemu-devel@nongnu.org; Tue, 21 Apr 2026 01:14:58 -0400", "by mail-pl1-x632.google.com with SMTP id\n d9443c01a7336-2ab232cc803so18287225ad.3\n for <qemu-devel@nongnu.org>; Mon, 20 Apr 2026 22:14:54 -0700 (PDT)", "from stoup.. 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helo=mail-pl1-x632.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Signed-off-by: Richard Henderson <richard.henderson@linaro.org>\n---\n target/arm/tcg/helper-fp8-defs.h | 2 +\n target/arm/tcg/fp8_helper.c | 79 ++++++++++++++++++++++++++++++++\n target/arm/tcg/translate-sme.c | 19 ++++++++\n target/arm/tcg/sme.decode | 5 ++\n 4 files changed, 105 insertions(+)", "diff": "diff --git a/target/arm/tcg/helper-fp8-defs.h b/target/arm/tcg/helper-fp8-defs.h\nindex 18ff483bb0..966f83d796 100644\n--- a/target/arm/tcg/helper-fp8-defs.h\n+++ b/target/arm/tcg/helper-fp8-defs.h\n@@ -5,3 +5,5 @@\n \n DEF_HELPER_FLAGS_4(advsimd_bfcvtl, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)\n DEF_HELPER_FLAGS_4(sve2_bfcvt, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)\n+DEF_HELPER_FLAGS_4(sme2_bfcvt_hb, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)\n+DEF_HELPER_FLAGS_4(sme2_bfcvtl_hb, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)\ndiff --git a/target/arm/tcg/fp8_helper.c b/target/arm/tcg/fp8_helper.c\nindex b03345c670..daf9c35720 100644\n--- a/target/arm/tcg/fp8_helper.c\n+++ b/target/arm/tcg/fp8_helper.c\n@@ -149,3 +149,82 @@ void HELPER(sve2_bfcvt)(void *vd, void *vn, CPUARMState *env, uint32_t desc)\n \n fp8_finish(env, &ctx);\n }\n+\n+void HELPER(sme2_bfcvt_hb)(void *vd, void *vn, CPUARMState *env, uint32_t desc)\n+{\n+ FP8Context ctx = fp8_src_start(env, desc, 0x3f);\n+ uint8_t *n = vn;\n+ uint16_t *d0 = vd;\n+ uint16_t *d1 = vd + sizeof(ARMVectorReg);\n+ size_t oprsz = simd_oprsz(desc);\n+ size_t nelem = oprsz / 2;\n+ ARMVectorReg scratch;\n+\n+ if (vectors_overlap(vd, 2, vn, 1)) {\n+ n = memcpy(&scratch, vn, oprsz);\n+ }\n+\n+ switch (ctx.f8fmt) {\n+ case OFP8_E5M2:\n+ for (size_t i = 0; i < nelem; ++i) {\n+ float8_e5m2 e = n[H1(i)];\n+ d0[H2(i)] = float8_e5m2_to_bfloat16(e, ctx.scale, &ctx.stat);\n+ }\n+ for (size_t i = 0; i < nelem; ++i) {\n+ float8_e5m2 e = n[H1(i) + nelem];\n+ d1[H2(i)] = float8_e5m2_to_bfloat16(e, ctx.scale, &ctx.stat);\n+ }\n+ break;\n+ case OFP8_E4M3:\n+ for (size_t i = 0; i < nelem; ++i) {\n+ float8_e4m3 e = n[H1(i)];\n+ d0[H2(i)] = float8_e4m3_to_bfloat16(e, ctx.scale, &ctx.stat);\n+ }\n+ for (size_t i = 0; i < nelem; ++i) {\n+ float8_e4m3 e = n[H1(i) + nelem];\n+ d1[H2(i)] = float8_e4m3_to_bfloat16(e, ctx.scale, &ctx.stat);\n+ }\n+ break;\n+ default:\n+ bfloat16_invalid_input(d0, nelem, &ctx.stat);\n+ memcpy(d1, d0, oprsz);\n+ break;\n+ }\n+\n+ fp8_finish(env, &ctx);\n+}\n+\n+void HELPER(sme2_bfcvtl_hb)(void *vd, void *vn, CPUARMState *env, uint32_t desc)\n+{\n+ FP8Context ctx = fp8_src_start(env, desc, 0x3f);\n+ uint8_t *n = vn;\n+ uint16_t *d0 = vd;\n+ uint16_t *d1 = vd + sizeof(ARMVectorReg);\n+ size_t oprsz = simd_oprsz(desc);\n+ size_t nelem = oprsz / 2;\n+\n+ switch (ctx.f8fmt) {\n+ case OFP8_E5M2:\n+ for (size_t i = 0; i < nelem; ++i) {\n+ float8_e5m2 e0 = n[H1(2 * i + 0)];\n+ float8_e5m2 e1 = n[H1(2 * i + 1)];\n+ d0[H2(i)] = float8_e5m2_to_bfloat16(e0, ctx.scale, &ctx.stat);\n+ d1[H2(i)] = float8_e5m2_to_bfloat16(e1, ctx.scale, &ctx.stat);\n+ }\n+ break;\n+ case OFP8_E4M3:\n+ for (size_t i = 0; i < nelem; ++i) {\n+ float8_e4m3 e0 = n[H1(2 * i + 0)];\n+ float8_e4m3 e1 = n[H1(2 * i + 1)];\n+ d0[H2(i)] = float8_e4m3_to_bfloat16(e0, ctx.scale, &ctx.stat);\n+ d1[H2(i)] = float8_e4m3_to_bfloat16(e1, ctx.scale, &ctx.stat);\n+ }\n+ break;\n+ default:\n+ bfloat16_invalid_input(d0, nelem, &ctx.stat);\n+ memcpy(d1, d0, oprsz);\n+ break;\n+ }\n+\n+ fp8_finish(env, &ctx);\n+}\ndiff --git a/target/arm/tcg/translate-sme.c b/target/arm/tcg/translate-sme.c\nindex 1267d3e65f..3e1da83535 100644\n--- a/target/arm/tcg/translate-sme.c\n+++ b/target/arm/tcg/translate-sme.c\n@@ -22,6 +22,7 @@\n #include \"helper-a64.h\"\n #include \"helper-sme.h\"\n #include \"helper-sve.h\"\n+#include \"helper-fp8.h\"\n #include \"translate.h\"\n #include \"translate-a64.h\"\n \n@@ -1531,6 +1532,24 @@ TRANS_FEAT(UUNPK_4bh, aa64_sme2, do_zz, a, 0, gen_helper_sme2_uunpk4_bh)\n TRANS_FEAT(UUNPK_4hs, aa64_sme2, do_zz, a, 0, gen_helper_sme2_uunpk4_hs)\n TRANS_FEAT(UUNPK_4sd, aa64_sme2, do_zz, a, 0, gen_helper_sme2_uunpk4_sd)\n \n+static bool do_f8cvt(DisasContext *s, arg_zz_n *a,\n+ gen_helper_gvec_2_ptr *fn, bool issrc2)\n+{\n+ if (fpmr_access_check(s) && sme_sm_enabled_check(s)) {\n+ int svl = streaming_vec_reg_size(s);\n+ tcg_gen_gvec_2_ptr(vec_full_reg_offset(s, a->zd),\n+ vec_full_reg_offset(s, a->zn),\n+ tcg_env, svl, svl,\n+ issrc2 | (FPST_ZA << 2), fn);\n+ }\n+ return true;\n+}\n+\n+TRANS_FEAT(BF1CVT, aa64_sme2_f8cvt, do_f8cvt, a, gen_helper_sme2_bfcvt_hb, 0)\n+TRANS_FEAT(BF2CVT, aa64_sme2_f8cvt, do_f8cvt, a, gen_helper_sme2_bfcvt_hb, 1)\n+TRANS_FEAT(BF1CVTL, aa64_sme2_f8cvt, do_f8cvt, a, gen_helper_sme2_bfcvtl_hb, 0)\n+TRANS_FEAT(BF2CVTL, aa64_sme2_f8cvt, do_f8cvt, a, gen_helper_sme2_bfcvtl_hb, 1)\n+\n static bool do_zipuzp_4(DisasContext *s, arg_zz_e *a,\n gen_helper_gvec_2 * const fn[5])\n {\ndiff --git a/target/arm/tcg/sme.decode b/target/arm/tcg/sme.decode\nindex 7a8e1abb59..df9586c1a5 100644\n--- a/target/arm/tcg/sme.decode\n+++ b/target/arm/tcg/sme.decode\n@@ -853,6 +853,11 @@ UUNPK_4bh 11000001 011 10101 111000 ....0 ...01 @zz_4x2_n1\n UUNPK_4hs 11000001 101 10101 111000 ....0 ...01 @zz_4x2_n1\n UUNPK_4sd 11000001 111 10101 111000 ....0 ...01 @zz_4x2_n1\n \n+BF1CVT 11000001 011 00110 111000 ..... ....0 @zz_2x1\n+BF2CVT 11000001 111 00110 111000 ..... ....0 @zz_2x1\n+BF1CVTL 11000001 011 00110 111000 ..... ....1 @zz_2x1\n+BF2CVTL 11000001 111 00110 111000 ..... ....1 @zz_2x1\n+\n ZIP_4 11000001 esz:2 1 10110 111000 ...00 ... 00 \\\n &zz_e zd=%zd_ax4 zn=%zn_ax4\n ZIP_4 11000001 001 10111 111000 ...00 ... 00 \\\n", "prefixes": [ "26/37" ] }