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GET /api/1.2/patches/2225458/?format=api
{ "id": 2225458, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2225458/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260421051346.41106-19-richard.henderson@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.2/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260421051346.41106-19-richard.henderson@linaro.org>", "list_archive_url": null, "date": "2026-04-21T05:13:27", "name": "[18/37] target/arm: Implement FSCALE for SME", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "e48206ef67012bbffe9ae5a7e92a138e2a089988", "submitter": { "id": 72104, "url": "http://patchwork.ozlabs.org/api/1.2/people/72104/?format=api", "name": "Richard Henderson", "email": "richard.henderson@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260421051346.41106-19-richard.henderson@linaro.org/mbox/", "series": [ { "id": 500729, "url": "http://patchwork.ozlabs.org/api/1.2/series/500729/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500729", "date": "2026-04-21T05:13:11", "name": "target/arm: Implement FEAT_FAMINMAX, FEAT_FPMR, FEAT_FP8", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/500729/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2225458/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2225458/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=vDdYnR2W;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g09cP0KpYz1yCv\n\tfor <incoming@patchwork.ozlabs.org>; Tue, 21 Apr 2026 15:18:29 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1wF3S2-0008Lj-LR; Tue, 21 Apr 2026 01:15:10 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <richard.henderson@linaro.org>)\n id 1wF3RZ-00082K-Nh\n for qemu-devel@nongnu.org; Tue, 21 Apr 2026 01:14:43 -0400", "from mail-pl1-x631.google.com ([2607:f8b0:4864:20::631])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <richard.henderson@linaro.org>)\n id 1wF3RU-0006VA-HF\n for qemu-devel@nongnu.org; Tue, 21 Apr 2026 01:14:38 -0400", "by mail-pl1-x631.google.com with SMTP id\n d9443c01a7336-2ad21f437eeso24886785ad.0\n for <qemu-devel@nongnu.org>; Mon, 20 Apr 2026 22:14:35 -0700 (PDT)", "from stoup.. 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helo=mail-pl1-x631.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Signed-off-by: Richard Henderson <richard.henderson@linaro.org>\n---\n target/arm/cpu-features.h | 5 +++++\n target/arm/tcg/translate-sme.c | 15 +++++++++++++--\n target/arm/tcg/sme.decode | 6 ++++++\n 3 files changed, 24 insertions(+), 2 deletions(-)", "diff": "diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h\nindex 87d16b57dd..8a6e5d555b 100644\n--- a/target/arm/cpu-features.h\n+++ b/target/arm/cpu-features.h\n@@ -1603,6 +1603,11 @@ static inline bool isar_feature_aa64_sme2_faminmax(const ARMISARegisters *id)\n return isar_feature_aa64_sme2(id) && isar_feature_aa64_faminmax(id);\n }\n \n+static inline bool isar_feature_aa64_sme2_f8cvt(const ARMISARegisters *id)\n+{\n+ return isar_feature_aa64_sme2(id) && isar_feature_aa64_f8cvt(id);\n+}\n+\n static inline bool isar_feature_aa64_sve_i8mm(const ARMISARegisters *id)\n {\n return isar_feature_aa64_sve(id) && isar_feature_aa64_sme_sve_i8mm(id);\ndiff --git a/target/arm/tcg/translate-sme.c b/target/arm/tcg/translate-sme.c\nindex ca6b130cfe..c6a8eec32c 100644\n--- a/target/arm/tcg/translate-sme.c\n+++ b/target/arm/tcg/translate-sme.c\n@@ -706,9 +706,12 @@ static bool do_z2z_n1_fpst(DisasContext *s, arg_z2z_en *a,\n {\n int esz = a->esz, n, dn, vsz, mofs;\n bool overlap = false;\n- gen_helper_gvec_3_ptr *fn;\n+ gen_helper_gvec_3_ptr *fn = fns[esz];\n TCGv_ptr fpst;\n \n+ if (fn == NULL) {\n+ return false;\n+ }\n /* These insns use MO_8 to encode BFloat16. */\n if (esz == MO_8 && !dc_isar_feature(aa64_sme_b16b16, s)) {\n return false;\n@@ -718,7 +721,6 @@ static bool do_z2z_n1_fpst(DisasContext *s, arg_z2z_en *a,\n }\n \n fpst = fpstatus_ptr(esz == MO_16 ? FPST_A64_F16 : FPST_A64);\n- fn = fns[esz];\n n = a->n;\n dn = a->zdn;\n mofs = vec_full_reg_offset(s, a->zm);\n@@ -830,6 +832,15 @@ static gen_helper_gvec_3_ptr * const f_vector_famin[4] = {\n };\n TRANS_FEAT(FAMIN_nn, aa64_sme2_faminmax, do_z2z_nn_fpst, a, f_vector_famin)\n \n+static gen_helper_gvec_3_ptr * const f_vector_fscale[4] = {\n+ NULL,\n+ gen_helper_gvec_fscale_h,\n+ gen_helper_gvec_fscale_s,\n+ gen_helper_gvec_fscale_d,\n+};\n+TRANS_FEAT(FSCALE_n1, aa64_sme2_f8cvt, do_z2z_n1_fpst, a, f_vector_fscale)\n+TRANS_FEAT(FSCALE_nn, aa64_sme2_f8cvt, do_z2z_nn_fpst, a, f_vector_fscale)\n+\n /* Add/Sub vector Z[m] to each Z[n*N] with result in ZA[d*N]. */\n static bool do_azz_n1(DisasContext *s, arg_azz_n *a, int esz,\n GVecGen3FnVar *fn)\ndiff --git a/target/arm/tcg/sme.decode b/target/arm/tcg/sme.decode\nindex 9dec7318a4..ee874be1a6 100644\n--- a/target/arm/tcg/sme.decode\n+++ b/target/arm/tcg/sme.decode\n@@ -250,6 +250,9 @@ ADD_n1 1100000 1 .. 10 .... 1010.0 11000 .... 0 @z2z_4x1\n SQDMULH_n1 1100000 1 .. 10 .... 1010.1 00000 .... 0 @z2z_2x1\n SQDMULH_n1 1100000 1 .. 10 .... 1010.1 00000 .... 0 @z2z_4x1\n \n+FSCALE_n1 1100000 1 .. 10 .... 1010.0 01100 .... 0 @z2z_2x1\n+FSCALE_n1 1100000 1 .. 10 .... 1010.0 01100 .... 0 @z2z_4x1\n+\n ### SME2 Multi-vector Multiple Vectors SVE Destructive\n \n %zm_ax2 17:4 !function=times_2\n@@ -291,6 +294,9 @@ FAMAX_nn 1100000 1 .. 1 ..... 1011.0 01010 .... 0 @z2z_4x4\n FAMIN_nn 1100000 1 .. 1 ..... 1011.0 01010 .... 1 @z2z_2x2\n FAMIN_nn 1100000 1 .. 1 ..... 1011.0 01010 .... 1 @z2z_4x4\n \n+FSCALE_nn 1100000 1 .. 1 ..... 1011.0 01100 .... 0 @z2z_2x2\n+FSCALE_nn 1100000 1 .. 1 ..... 1011.0 01100 .... 0 @z2z_4x4\n+\n ### SME2 Multi-vector Multiple and Single Array Vectors\n \n &azz_n n off rv zn zm\n", "prefixes": [ "18/37" ] }