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GET /api/1.2/patches/2224658/?format=api
{ "id": 2224658, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2224658/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260417173105.1648172-17-peter.maydell@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.2/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260417173105.1648172-17-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2026-04-17T17:31:04", "name": "[16/17] target/arm: Implement translate_for_debug", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "6db6cb75dc1ae5c197e4ecd0c1a7385bc2b1291d", "submitter": { "id": 5111, "url": "http://patchwork.ozlabs.org/api/1.2/people/5111/?format=api", "name": "Peter Maydell", "email": "peter.maydell@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260417173105.1648172-17-peter.maydell@linaro.org/mbox/", "series": [ { "id": 500380, "url": "http://patchwork.ozlabs.org/api/1.2/series/500380/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500380", "date": "2026-04-17T17:30:51", "name": "Handle sub-page granularity in cpu_memory_rw_debug()", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/500380/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2224658/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2224658/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=NAbTLBAB;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fy29V5RXbz1yD3\n\tfor <incoming@patchwork.ozlabs.org>; Sat, 18 Apr 2026 03:36:14 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1wDn35-0007MA-1w; Fri, 17 Apr 2026 13:32:11 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1wDn2l-0006vV-P4\n for qemu-devel@nongnu.org; Fri, 17 Apr 2026 13:31:56 -0400", "from mail-wr1-x431.google.com ([2a00:1450:4864:20::431])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1wDn2i-0002P2-A4\n for qemu-devel@nongnu.org; Fri, 17 Apr 2026 13:31:51 -0400", "by mail-wr1-x431.google.com with SMTP id\n ffacd0b85a97d-43d77f60944so688538f8f.3\n for <qemu-devel@nongnu.org>; Fri, 17 Apr 2026 10:31:46 -0700 (PDT)", "from lanath.. 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Iglesias\" <edgar.iglesias@gmail.com>,\n Jiaxun Yang <jiaxun.yang@flygoat.com>, Nicholas Piggin <npiggin@gmail.com>,\n Chinmay Rath <rathc@linux.ibm.com>, Glenn Miles <milesg@linux.ibm.com>,\n Palmer Dabbelt <palmer@dabbelt.com>,\n Alistair Francis <alistair.francis@wdc.com>, Weiwei Li <liwei1518@gmail.com>,\n Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>,\n Liu Zhiwei <zhiwei_liu@linux.alibaba.com>,\n Chao Liu <chao.liu.zevorn@gmail.com>, Ilya Leoshkevich <iii@linux.ibm.com>,\n David Hildenbrand <david@kernel.org>,\n Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>,\n Artyom Tarasenko <atar4qemu@gmail.com>", "Subject": "[PATCH 16/17] target/arm: Implement translate_for_debug", "Date": "Fri, 17 Apr 2026 18:31:04 +0100", "Message-ID": "<20260417173105.1648172-17-peter.maydell@linaro.org>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260417173105.1648172-1-peter.maydell@linaro.org>", "References": "<20260417173105.1648172-1-peter.maydell@linaro.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2a00:1450:4864:20::431;\n envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x431.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Implement the translate_for_debug method instead of the\nget_phys_addr_attrs_debug one. This allows us to pass the caller the\nlg_page_size from our internal GetPhysAddrResult struct.\n\nAwkwardly, translate_for_debug's \"true on success\" convention\nis the opposite of the one we use internally in ptw.c, so\nwe have to be careful about the sense of the return values.\nThis corresponds to the way that arm_cpu_tlb_fill_align()\nalso has to return true when get_phys_addr() returns false.\n\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\n---\n target/arm/cpu.c | 2 +-\n target/arm/cpu.h | 3 ---\n target/arm/internals.h | 4 ++++\n target/arm/ptw.c | 37 ++++++++++++++++++++++---------------\n 4 files changed, 27 insertions(+), 19 deletions(-)", "diff": "diff --git a/target/arm/cpu.c b/target/arm/cpu.c\nindex f28c74a94b..c014375cb7 100644\n--- a/target/arm/cpu.c\n+++ b/target/arm/cpu.c\n@@ -2295,7 +2295,7 @@ static vaddr aarch64_untagged_addr(CPUState *cs, vaddr x)\n \n static const struct SysemuCPUOps arm_sysemu_ops = {\n .has_work = arm_cpu_has_work,\n- .get_phys_addr_attrs_debug = arm_cpu_get_phys_addr_attrs_debug,\n+ .translate_for_debug = arm_cpu_translate_for_debug,\n .asidx_from_attrs = arm_asidx_from_attrs,\n .write_elf32_note = arm_cpu_write_elf32_note,\n .write_elf64_note = arm_cpu_write_elf64_note,\ndiff --git a/target/arm/cpu.h b/target/arm/cpu.h\nindex 917e4668da..ea3c65ba1a 100644\n--- a/target/arm/cpu.h\n+++ b/target/arm/cpu.h\n@@ -1231,9 +1231,6 @@ extern const VMStateDescription vmstate_arm_cpu;\n void arm_cpu_do_interrupt(CPUState *cpu);\n void arm_v7m_cpu_do_interrupt(CPUState *cpu);\n \n-hwaddr arm_cpu_get_phys_addr_attrs_debug(CPUState *cpu, vaddr addr,\n- MemTxAttrs *attrs);\n-\n typedef struct ARMGranuleProtectionConfig {\n /* GPCCR_EL3 */\n uint64_t gpccr;\ndiff --git a/target/arm/internals.h b/target/arm/internals.h\nindex 85980f0e69..5527c004db 100644\n--- a/target/arm/internals.h\n+++ b/target/arm/internals.h\n@@ -1532,6 +1532,10 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,\n \n void arm_log_exception(CPUState *cs);\n \n+/* Implementation of SysemuCPUOps::translate_for_debug */\n+bool arm_cpu_translate_for_debug(CPUState *cs, vaddr addr,\n+ TranslateForDebugResult *result);\n+\n #endif /* !CONFIG_USER_ONLY */\n \n /*\ndiff --git a/target/arm/ptw.c b/target/arm/ptw.c\nindex 8be6f243e6..ae4089a14c 100644\n--- a/target/arm/ptw.c\n+++ b/target/arm/ptw.c\n@@ -3922,8 +3922,9 @@ bool get_phys_addr(CPUARMState *env, vaddr address,\n memop, result, fi);\n }\n \n-static hwaddr arm_cpu_get_phys_addr(CPUARMState *env, vaddr addr,\n- MemTxAttrs *attrs, ARMMMUIdx mmu_idx)\n+static bool arm_cpu_get_phys_addr(CPUARMState *env, vaddr addr,\n+ TranslateForDebugResult *result,\n+ ARMMMUIdx mmu_idx)\n {\n S1Translate ptw = {\n .in_mmu_idx = mmu_idx,\n@@ -3935,25 +3936,30 @@ static hwaddr arm_cpu_get_phys_addr(CPUARMState *env, vaddr addr,\n GetPhysAddrResult res = {};\n ARMMMUFaultInfo fi = {};\n bool ret = get_phys_addr_gpc(env, &ptw, addr, MMU_DATA_LOAD, 0, &res, &fi);\n- *attrs = res.f.attrs;\n \n- if (ret) {\n- return -1;\n+ if (!ret) {\n+ /* translation succeeded */\n+ result->physaddr = res.f.phys_addr;\n+ result->attrs = res.f.attrs;\n+ result->lg_page_size = res.f.lg_page_size;\n }\n- return res.f.phys_addr;\n+ return ret;\n }\n \n-hwaddr arm_cpu_get_phys_addr_attrs_debug(CPUState *cs, vaddr addr,\n- MemTxAttrs *attrs)\n+bool arm_cpu_translate_for_debug(CPUState *cs, vaddr addr,\n+ TranslateForDebugResult *result)\n {\n ARMCPU *cpu = ARM_CPU(cs);\n CPUARMState *env = &cpu->env;\n ARMMMUIdx mmu_idx = arm_mmu_idx(env);\n \n- hwaddr res = arm_cpu_get_phys_addr(env, addr, attrs, mmu_idx);\n-\n- if (res != -1) {\n- return res;\n+ /*\n+ * Note that this function returns true on translation success,\n+ * but arm_cpu_get_phys_addr() and all the other get_phys_addr\n+ * style functions in this file return true on failure.\n+ */\n+ if (!arm_cpu_get_phys_addr(env, addr, result, mmu_idx)) {\n+ return true;\n }\n \n /*\n@@ -3964,11 +3970,12 @@ hwaddr arm_cpu_get_phys_addr_attrs_debug(CPUState *cs, vaddr addr,\n switch (mmu_idx) {\n case ARMMMUIdx_E10_1:\n case ARMMMUIdx_E10_1_PAN:\n- return arm_cpu_get_phys_addr(env, addr, attrs, ARMMMUIdx_E10_0);\n+ return !arm_cpu_get_phys_addr(env, addr, result, ARMMMUIdx_E10_0);\n case ARMMMUIdx_E20_2:\n case ARMMMUIdx_E20_2_PAN:\n- return arm_cpu_get_phys_addr(env, addr, attrs, ARMMMUIdx_E20_0);\n+ return !arm_cpu_get_phys_addr(env, addr, result, ARMMMUIdx_E20_0);\n default:\n- return -1;\n+ /* translation failed */\n+ return false;\n }\n }\n", "prefixes": [ "16/17" ] }