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GET /api/1.2/patches/2224653/?format=api
{ "id": 2224653, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2224653/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260417173105.1648172-5-peter.maydell@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.2/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260417173105.1648172-5-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2026-04-17T17:30:52", "name": "[04/17] target/sparc: Make get_phys_page_debug handle non-page-aligned addrs", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "acc07f76fb0927aa523d5e6bd402a1c78379abbe", "submitter": { "id": 5111, "url": "http://patchwork.ozlabs.org/api/1.2/people/5111/?format=api", "name": "Peter Maydell", "email": "peter.maydell@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260417173105.1648172-5-peter.maydell@linaro.org/mbox/", "series": [ { "id": 500380, "url": "http://patchwork.ozlabs.org/api/1.2/series/500380/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500380", "date": "2026-04-17T17:30:51", "name": "Handle sub-page granularity in cpu_memory_rw_debug()", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/500380/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2224653/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2224653/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=YxSLEa8u;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fy29D2m7gz1yJ8\n\tfor <incoming@patchwork.ozlabs.org>; Sat, 18 Apr 2026 03:36:00 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1wDn2v-0007At-QU; Fri, 17 Apr 2026 13:32:01 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1wDn2G-0006jS-AV\n for qemu-devel@nongnu.org; Fri, 17 Apr 2026 13:31:31 -0400", "from mail-wm1-x336.google.com ([2a00:1450:4864:20::336])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1wDn2B-00022V-Sw\n for qemu-devel@nongnu.org; Fri, 17 Apr 2026 13:31:19 -0400", "by mail-wm1-x336.google.com with SMTP id\n 5b1f17b1804b1-488a4bc360bso5895495e9.0\n for <qemu-devel@nongnu.org>; Fri, 17 Apr 2026 10:31:15 -0700 (PDT)", "from lanath.. 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Iglesias\" <edgar.iglesias@gmail.com>,\n Jiaxun Yang <jiaxun.yang@flygoat.com>, Nicholas Piggin <npiggin@gmail.com>,\n Chinmay Rath <rathc@linux.ibm.com>, Glenn Miles <milesg@linux.ibm.com>,\n Palmer Dabbelt <palmer@dabbelt.com>,\n Alistair Francis <alistair.francis@wdc.com>, Weiwei Li <liwei1518@gmail.com>,\n Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>,\n Liu Zhiwei <zhiwei_liu@linux.alibaba.com>,\n Chao Liu <chao.liu.zevorn@gmail.com>, Ilya Leoshkevich <iii@linux.ibm.com>,\n David Hildenbrand <david@kernel.org>,\n Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>,\n Artyom Tarasenko <atar4qemu@gmail.com>", "Subject": "[PATCH 04/17] target/sparc: Make get_phys_page_debug handle\n non-page-aligned addrs", "Date": "Fri, 17 Apr 2026 18:30:52 +0100", "Message-ID": "<20260417173105.1648172-5-peter.maydell@linaro.org>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260417173105.1648172-1-peter.maydell@linaro.org>", "References": "<20260417173105.1648172-1-peter.maydell@linaro.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2a00:1450:4864:20::336;\n envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Currently our implementations of SysemuCPUOps::get_phys_page_debug\nand SysemuCPUOps::get_phys_page_attrs_debug are a mix of \"accepts a\nnon-page-aligned virtual address and returns the corresponding\nnon-page-aligned physical address\" and \"only returns a page-aligned\nphysical address\". This is awkward for callsites, which in practice\nall want the physical address for an arbitrary virtual address and\nhave to work around the possibility of getting a page-aligned\naddress, and it doesn't account for protection being possibly on a\nsub-page-sized granularity. We want to standardize on the\nimplementation having to handle non-page-aligned addresses.\n\nThe sparc TLB lookup code can handle non-aligned input addresses but\nwill return page-aligned results. Rather than attempting to change\nthe internals of the lookup code, we take the simple approach of\nORing the page offset back into the phys_addr result.\n\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\n---\n target/sparc/mmu_helper.c | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)", "diff": "diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c\nindex a6f76a1ab7..25f8a85fae 100644\n--- a/target/sparc/mmu_helper.c\n+++ b/target/sparc/mmu_helper.c\n@@ -913,7 +913,7 @@ hwaddr sparc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)\n return -1;\n }\n }\n- return phys_addr;\n+ return phys_addr | (addr & ~TARGET_PAGE_MASK);\n }\n \n G_NORETURN void sparc_cpu_do_unaligned_access(CPUState *cs, vaddr addr,\n", "prefixes": [ "04/17" ] }