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GET /api/1.2/patches/2224631/?format=api
{ "id": 2224631, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2224631/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260417173105.1648172-15-peter.maydell@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.2/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260417173105.1648172-15-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2026-04-17T17:31:02", "name": "[14/17] hw/core: Implement new cpu_translate_for_debug()", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "270903e46564f5a89cafe7395b4a3a0b9a4f1743", "submitter": { "id": 5111, "url": "http://patchwork.ozlabs.org/api/1.2/people/5111/?format=api", "name": "Peter Maydell", "email": "peter.maydell@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260417173105.1648172-15-peter.maydell@linaro.org/mbox/", "series": [ { "id": 500380, "url": "http://patchwork.ozlabs.org/api/1.2/series/500380/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500380", "date": "2026-04-17T17:30:51", "name": "Handle sub-page granularity in cpu_memory_rw_debug()", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/500380/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2224631/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2224631/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=nd3kD9WY;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fy27C5rHfz1yDF\n\tfor <incoming@patchwork.ozlabs.org>; Sat, 18 Apr 2026 03:34:15 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1wDn30-0007He-Ci; Fri, 17 Apr 2026 13:32:06 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1wDn2i-0006v4-Im\n for qemu-devel@nongnu.org; Fri, 17 Apr 2026 13:31:54 -0400", "from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1wDn2d-0002L5-6a\n for qemu-devel@nongnu.org; Fri, 17 Apr 2026 13:31:46 -0400", "by mail-wr1-x42d.google.com with SMTP id\n ffacd0b85a97d-43d7605ec91so794039f8f.3\n for <qemu-devel@nongnu.org>; Fri, 17 Apr 2026 10:31:42 -0700 (PDT)", "from lanath.. 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Iglesias\" <edgar.iglesias@gmail.com>,\n Jiaxun Yang <jiaxun.yang@flygoat.com>, Nicholas Piggin <npiggin@gmail.com>,\n Chinmay Rath <rathc@linux.ibm.com>, Glenn Miles <milesg@linux.ibm.com>,\n Palmer Dabbelt <palmer@dabbelt.com>,\n Alistair Francis <alistair.francis@wdc.com>, Weiwei Li <liwei1518@gmail.com>,\n Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>,\n Liu Zhiwei <zhiwei_liu@linux.alibaba.com>,\n Chao Liu <chao.liu.zevorn@gmail.com>, Ilya Leoshkevich <iii@linux.ibm.com>,\n David Hildenbrand <david@kernel.org>,\n Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>,\n Artyom Tarasenko <atar4qemu@gmail.com>", "Subject": "[PATCH 14/17] hw/core: Implement new cpu_translate_for_debug()", "Date": "Fri, 17 Apr 2026 18:31:02 +0100", "Message-ID": "<20260417173105.1648172-15-peter.maydell@linaro.org>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260417173105.1648172-1-peter.maydell@linaro.org>", "References": "<20260417173105.1648172-1-peter.maydell@linaro.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2a00:1450:4864:20::42d;\n envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "In cpu_memory_rw_debug() we need to do a virtual-to-physical address\ntranslation for debug access. Currently we assume that the\ntranslation is valid for an entire guest page, but this may not be\ntrue if the target implements some protection regions that have\nsub-page granularity. (Currently the only such target is the Arm\nCPUs when using an MPU, as in R-profile and M-profile.)\n\nFor TCG's emulated accesses, we handle sub-page granularity by the\nCPU filling in the lg_page_size field of the CPUTLBEntryFull struct\nto tell us how large the region covered by the result is. But we\ndidn't extend this to the debug-access code path, with the result\nthat debug accesses might incorrectly fail because they are looking\nat the mapping for the address rounded down to a page boundary.\n\nProvide a cpu_translate_for_debug() function which reports to the\ncaller not just the physical address and attributes of the\ntranslation but also the lg_page_size for which it is valid. The\nfallback implementation calls cpu_get_phys_addr_attrs_debug() and\nassumes target-page-sized validity.\n\nNB: the \"return true on valid access, false on failure\" follows\nthe same convention as TCGCPUOps::tlb_fill_align() (though it\nis the opposite of what we use in some other places, e.g.\nin target/arm's get_phys_addr_* functions).\n\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\n---\n hw/core/cpu-system.c | 32 ++++++++++++++++++++++++++++++++\n include/hw/core/cpu.h | 32 ++++++++++++++++++++++++++++++++\n include/hw/core/sysemu-cpu-ops.h | 27 +++++++++++++++++++++++++--\n 3 files changed, 89 insertions(+), 2 deletions(-)", "diff": "diff --git a/hw/core/cpu-system.c b/hw/core/cpu-system.c\nindex 05c126ecb6..cab65d549a 100644\n--- a/hw/core/cpu-system.c\n+++ b/hw/core/cpu-system.c\n@@ -22,6 +22,7 @@\n #include \"qapi/error.h\"\n #include \"system/address-spaces.h\"\n #include \"exec/cputlb.h\"\n+#include \"exec/target_page.h\"\n #include \"system/memory.h\"\n #include \"qemu/target-info.h\"\n #include \"hw/core/qdev.h\"\n@@ -55,6 +56,37 @@ bool cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list,\n return false;\n }\n \n+bool cpu_translate_for_debug(CPUState *cpu, vaddr addr,\n+ TranslateForDebugResult *result)\n+{\n+ if (cpu->cc->sysemu_ops->translate_for_debug) {\n+ return cpu->cc->sysemu_ops->translate_for_debug(cpu, addr, result);\n+ } else {\n+ /* Fallbacks for CPUs which don't implement translate_for_debug */\n+ if (cpu->cc->sysemu_ops->get_phys_addr_attrs_debug) {\n+ result->physaddr =\n+ cpu->cc->sysemu_ops->get_phys_addr_attrs_debug(cpu, addr,\n+ &result->attrs);\n+ } else {\n+ result->physaddr\n+ = cpu->cc->sysemu_ops->get_phys_addr_debug(cpu, addr);\n+ result->attrs = MEMTXATTRS_UNSPECIFIED;\n+ }\n+ if (result->physaddr == -1) {\n+ return false;\n+ }\n+ /* Indicate that this is a debug access. */\n+ result->attrs.debug = 1;\n+ /*\n+ * Assume memory access permissions are valid for the whole page.\n+ * Targets where this isn't true should implement the\n+ * translate_for_debug method.\n+ */\n+ result->lg_page_size = TARGET_PAGE_SIZE;\n+ return true;\n+ }\n+}\n+\n hwaddr cpu_get_phys_addr_attrs_debug(CPUState *cpu, vaddr addr,\n MemTxAttrs *attrs)\n {\ndiff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h\nindex 0941757c55..084d691e6c 100644\n--- a/include/hw/core/cpu.h\n+++ b/include/hw/core/cpu.h\n@@ -778,6 +778,38 @@ hwaddr cpu_get_phys_addr_attrs_debug(CPUState *cpu, vaddr addr,\n */\n hwaddr cpu_get_phys_addr_debug(CPUState *cpu, vaddr addr);\n \n+/**\n+ * TranslateForDebugResult: gives result of cpu_translate_for_debug()\n+ *\n+ * @physaddr: the physical address corresponding to the virtual address\n+ * @attrs: the transaction attributes for this access\n+ * @lg_page_size: log2 of the size of the aligned block of memory\n+ * that this physaddr and attrs are valid for.\n+ */\n+typedef struct TranslateForDebugResult {\n+ hwaddr physaddr;\n+ MemTxAttrs attrs;\n+ uint8_t lg_page_size;\n+} TranslateForDebugResult;\n+\n+/**\n+ * cpu_translate_for_debug:\n+ * @cpu: The CPU use for the virtual-to-physical translation\n+ * @addr: The virtual address\n+ * @result: Struct filled in with results of translation\n+ *\n+ * Perform a virtual-to-physical address translation for debug accesses.\n+ * Use it only for debugging because no protection checks are done.\n+ *\n+ * The address need not be page-aligned; the returned address in @result\n+ * will be the physical address corresponding to that virtual address.\n+ *\n+ * Returns: false on translation failure; true on successful translation\n+ * and fills in the fields of @result.\n+ */\n+bool cpu_translate_for_debug(CPUState *cpu, vaddr addr,\n+ TranslateForDebugResult *result);\n+\n /** cpu_asidx_from_attrs:\n * @cpu: CPU\n * @attrs: memory transaction attributes\ndiff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-ops.h\nindex a87c55d922..8625ebb564 100644\n--- a/include/hw/core/sysemu-cpu-ops.h\n+++ b/include/hw/core/sysemu-cpu-ops.h\n@@ -33,19 +33,42 @@ typedef struct SysemuCPUOps {\n * @get_phys_addr_debug: Callback for obtaining a physical address.\n * This must be able to handle a non-page-aligned address, and will\n * return the physical address corresponding to that address.\n+ *\n+ * CPUs should prefer to implement translate_for_debug instead of\n+ * this (and must do so if their translations are not always valid\n+ * for a complete target page or they use memory attributes).\n */\n hwaddr (*get_phys_addr_debug)(CPUState *cpu, vaddr addr);\n /**\n * @get_phys_addr_attrs_debug: Callback for obtaining a physical address\n * and the associated memory transaction attributes to use for the\n * access.\n- * CPUs which use memory transaction attributes should implement this\n- * instead of get_phys_addr_debug.\n+ *\n * This must be able to handle a non-page-aligned address, and will\n * return the physical address corresponding to that address.\n+ *\n+ * CPUs should prefer to implement translate_for_debug instead of\n+ * this (and must do so if their translations are not always valid\n+ * for a complete target page).\n */\n hwaddr (*get_phys_addr_attrs_debug)(CPUState *cpu, vaddr addr,\n MemTxAttrs *attrs);\n+ /**\n+ * @translate_for_debug: Callback for translating a virtual address into\n+ * a physical address for debug purposes.\n+ * The implementation should fill in @result with the physical address,\n+ * transaction attributes, and log2 of the size of the aligned block of\n+ * memory that the translation is valid for.\n+ * This must be able to handle a non-page-aligned address, and will\n+ * return the physical address corresponding to that address.\n+ * The attributes must include the debug flag being set.\n+ * Returns false on translation failure; on success returns true and\n+ * fills in @result.\n+ *\n+ * This is the preferred method to implement for new CPUs.\n+ */\n+ bool (*translate_for_debug)(CPUState *cpu, vaddr addr,\n+ TranslateForDebugResult *result);\n /**\n * @asidx_from_attrs: Callback to return the CPU AddressSpace to use for\n * a memory access with the specified memory transaction attributes.\n", "prefixes": [ "14/17" ] }