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GET /api/1.2/patches/2224598/?format=api
{ "id": 2224598, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2224598/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260417164328.1009132-6-alex.bennee@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.2/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260417164328.1009132-6-alex.bennee@linaro.org>", "list_archive_url": null, "date": "2026-04-17T16:43:25", "name": "[5/7] tests/tcg: add HW page for aarch64 tests", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "075af2efd0861b44f8ac7f2f76bd53981b842473", "submitter": { "id": 39532, "url": "http://patchwork.ozlabs.org/api/1.2/people/39532/?format=api", "name": "Alex Bennée", "email": "alex.bennee@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260417164328.1009132-6-alex.bennee@linaro.org/mbox/", "series": [ { "id": 500373, "url": "http://patchwork.ozlabs.org/api/1.2/series/500373/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500373", "date": "2026-04-17T16:43:20", "name": "tests/tcg: more capabilities for aarch64-softmmu tests", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/500373/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2224598/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2224598/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=KqYPDkG0;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=UTF-8", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2a00:1450:4864:20::329;\n envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x329.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "If the test cases need to program items like the GIC we need to define\nthe region as Device-nGnRE memory. As this is for test cases just map\nthe whole first GB block (which is all HW in the -M virt machine).\n\nSigned-off-by: Alex Bennée <alex.bennee@linaro.org>\n---\n tests/tcg/aarch64/system/lib/pgtable.c | 24 +++++++++++++++++-------\n 1 file changed, 17 insertions(+), 7 deletions(-)", "diff": "diff --git a/tests/tcg/aarch64/system/lib/pgtable.c b/tests/tcg/aarch64/system/lib/pgtable.c\nindex a558f5f0dd5..5e7d95fd3d7 100644\n--- a/tests/tcg/aarch64/system/lib/pgtable.c\n+++ b/tests/tcg/aarch64/system/lib/pgtable.c\n@@ -17,14 +17,18 @@ uint64_t ttb_l1[512] __attribute__((aligned(4096)));\n uint64_t ttb_l2[512] __attribute__((aligned(4096)));\n \n /*\n- * Setup a flat address mapping page-tables. Stage one simply\n- * maps RAM to the first Gb. The stage2 tables have two 2mb\n- * translation block entries covering a series of adjacent\n- * 4k pages.\n+ * Setup a flat address mapping page-tables.\n+ *\n+ * ttb (Level 1):\n+ * - Entry 0 [0 - 1GB]: 1GB Device block (for GIC and other H/W)\n+ * - Entry 1 [1GB - 2GB]: Table entry pointing to ttb_l2 (for RAM)\n */\n void setup_pgtables(void)\n {\n- /* L1 entry points to L2 table */\n+ /* L1 entry 0: 1GB Device block mapping at 0x0 */\n+ pgt_map_l1_block(ttb_l1, 0, 0, DESC_AF | DESC_ATTRINDX(2));\n+\n+ /* L1 entry 1: points to L2 table for finer permissions */\n pgt_map_l1_table(ttb_l1, (uintptr_t)_text_start, ttb_l2);\n \n /* L2 entries: 2MB blocks */\n@@ -40,8 +44,14 @@ void setup_pgtables(void)\n /* Set TTBR0_EL1 */\n write_sysreg(ttb_l1, ttbr0_el1);\n \n- /* Set MAIR_EL1 */\n- write_sysreg(0xeeULL, mair_el1);\n+ /*\n+ * Set MAIR_EL1\n+ *\n+ * Attr0 (0xee): Normal memory, Outer/Inner WB/WA/Read-Alloc\n+ * Attr1 (0x00): MTE page\n+ * Attr2 (0x04): Device-nGnRE memory (for the first 1GB)\n+ */\n+ write_sysreg(0x0400eeULL, mair_el1);\n \n /* Set TCR_EL1 */\n uint64_t tcr = TCR_EL1_IPS_40BIT | TCR_EL1_TG0_4KB | TCR_EL1_ORGN0_WBWA | TCR_EL1_IRGN0_WBWA | TCR_EL1_T0SZ(25);\n", "prefixes": [ "5/7" ] }