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GET /api/1.2/patches/2224554/?format=api
{ "id": 2224554, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2224554/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/a4a985723ca53660e72f7a825fb53299adba5570.1776438369.git.chao.liu.zevorn@gmail.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.2/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<a4a985723ca53660e72f7a825fb53299adba5570.1776438369.git.chao.liu.zevorn@gmail.com>", "list_archive_url": null, "date": "2026-04-17T15:11:26", "name": "[v6,2/5] hw/riscv: add k230 board initial support", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "3dac7745d88bfd306e16c4268d50aae7c90bd602", "submitter": { "id": 92265, "url": "http://patchwork.ozlabs.org/api/1.2/people/92265/?format=api", "name": "Chao Liu", "email": "chao.liu.zevorn@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/a4a985723ca53660e72f7a825fb53299adba5570.1776438369.git.chao.liu.zevorn@gmail.com/mbox/", "series": [ { "id": 500360, "url": "http://patchwork.ozlabs.org/api/1.2/series/500360/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500360", "date": "2026-04-17T15:11:28", "name": "Add support for K230 board", "version": 6, "mbox": "http://patchwork.ozlabs.org/series/500360/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2224554/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2224554/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=RlvMEdfw;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail-vs1-xe42.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "From: Chao Liu <chao.liu@zevorn.cn>\n\nK230 Board Compatible with kendryte K230 SDK.\n\nPreliminarily supports the C908 small core, which can\nrun the U-Boot and Linux kernel compiled by the K230 SDK.\n\nSigned-off-by: Chao Liu <chao.liu.zevorn@gmail.com>\nReviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>\nReported-by: Peng Jiang <3160104094@zju.edu.cn>\n---\n MAINTAINERS | 8 +-\n hw/riscv/Kconfig | 10 +\n hw/riscv/k230.c | 484 ++++++++++++++++++++++++++++++++++++++++\n hw/riscv/meson.build | 2 +-\n include/hw/riscv/k230.h | 150 +++++++++++++\n 5 files changed, 652 insertions(+), 2 deletions(-)\n create mode 100644 hw/riscv/k230.c\n create mode 100644 include/hw/riscv/k230.h", "diff": "diff --git a/MAINTAINERS b/MAINTAINERS\nindex aa4267b158..c429c63961 100644\n--- a/MAINTAINERS\n+++ b/MAINTAINERS\n@@ -1773,6 +1773,12 @@ F: docs/system/riscv/xiangshan-kunminghu.rst\n F: hw/riscv/xiangshan_kmh.c\n F: include/hw/riscv/xiangshan_kmh.h\n \n+K230 Machines\n+M: Chao Liu <chao.liu.zevorn@gmail.com>\n+S: Maintained\n+F: hw/riscv/k230.c\n+F: include/hw/riscv/k230.h\n+\n RX Machines\n -----------\n rx-gdbsim\n@@ -3620,7 +3626,7 @@ M: Alexander Bulekov <alxndr@bu.edu>\n R: Paolo Bonzini <pbonzini@redhat.com>\n R: Stefan Hajnoczi <stefanha@redhat.com>\n R: Fabiano Rosas <farosas@suse.de>\n-R: Darren Kenny <darren.kenny@oracle.com> \n+R: Darren Kenny <darren.kenny@oracle.com>\n R: Qiuhao Li <Qiuhao.Li@outlook.com>\n S: Maintained\n F: tests/qtest/fuzz/\ndiff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig\nindex 0222c93f87..b1a7357866 100644\n--- a/hw/riscv/Kconfig\n+++ b/hw/riscv/Kconfig\n@@ -134,3 +134,13 @@ config MIPS_BOSTON_AIA\n default y\n select PCI_EXPRESS\n select PCI_EXPRESS_XILINX\n+\n+config K230\n+ bool\n+ default y\n+ depends on RISCV64\n+ select RISCV_ACLINT\n+ select RISCV_APLIC\n+ select RISCV_IMSIC\n+ select SERIAL_MM\n+ select UNIMP\ndiff --git a/hw/riscv/k230.c b/hw/riscv/k230.c\nnew file mode 100644\nindex 0000000000..2537023a05\n--- /dev/null\n+++ b/hw/riscv/k230.c\n@@ -0,0 +1,484 @@\n+/*\n+ * QEMU RISC-V Virt Board Compatible with Kendryte K230 SDK\n+ *\n+ * Copyright (c) 2025 Chao Liu <chao.liu.zevorn@gmail.com>\n+ *\n+ * SPDX-License-Identifier: GPL-2.0-or-later\n+ *\n+ * Provides a board compatible with the Kendryte K230 SDK\n+ *\n+ * Documentation: K230_Technical_Reference_Manual_V0.3.1_20241118.pdf\n+ *\n+ * For more information, see <https://www.kendryte.com/en/proDetail/230>\n+ *\n+ * This program is free software; you can redistribute it and/or modify it\n+ * under the terms and conditions of the GNU General Public License,\n+ * version 2 or later, as published by the Free Software Foundation.\n+ *\n+ * This program is distributed in the hope it will be useful, but WITHOUT\n+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n+ * more details.\n+ *\n+ * You should have received a copy of the GNU General Public License along with\n+ * this program. If not, see <http://www.gnu.org/licenses/>.\n+ */\n+\n+#include \"qemu/osdep.h\"\n+#include \"cpu-qom.h\"\n+#include \"qemu/cutils.h\"\n+#include \"qemu/error-report.h\"\n+#include \"qapi/error.h\"\n+#include \"system/system.h\"\n+#include \"system/memory.h\"\n+#include \"target/riscv/cpu.h\"\n+#include \"chardev/char.h\"\n+#include \"hw/core/loader.h\"\n+#include \"hw/core/sysbus.h\"\n+#include \"hw/riscv/k230.h\"\n+#include \"hw/riscv/boot.h\"\n+#include \"hw/intc/riscv_aclint.h\"\n+#include \"hw/intc/sifive_plic.h\"\n+#include \"hw/char/serial-mm.h\"\n+#include \"hw/misc/unimp.h\"\n+\n+static const MemMapEntry memmap[] = {\n+ [K230_DEV_DDRC] = { 0x00000000, 0x80000000 },\n+ [K230_DEV_KPU_L2_CACHE] = { 0x80000000, 0x00200000 },\n+ [K230_DEV_SRAM] = { 0x80200000, 0x00200000 },\n+ [K230_DEV_KPU_CFG] = { 0x80400000, 0x00000800 },\n+ [K230_DEV_FFT] = { 0x80400800, 0x00000400 },\n+ [K230_DEV_AI_2D_ENGINE] = { 0x80400C00, 0x00000800 },\n+ [K230_DEV_GSDMA] = { 0x80800000, 0x00004000 },\n+ [K230_DEV_DMA] = { 0x80804000, 0x00004000 },\n+ [K230_DEV_DECOMP_GZIP] = { 0x80808000, 0x00004000 },\n+ [K230_DEV_NON_AI_2D] = { 0x8080C000, 0x00004000 },\n+ [K230_DEV_ISP] = { 0x90000000, 0x00008000 },\n+ [K230_DEV_DEWARP] = { 0x90008000, 0x00001000 },\n+ [K230_DEV_RX_CSI] = { 0x90009000, 0x00002000 },\n+ [K230_DEV_H264] = { 0x90400000, 0x00010000 },\n+ [K230_DEV_2P5D] = { 0x90800000, 0x00040000 },\n+ [K230_DEV_VO] = { 0x90840000, 0x00010000 },\n+ [K230_DEV_VO_CFG] = { 0x90850000, 0x00001000 },\n+ [K230_DEV_3D_ENGINE] = { 0x90A00000, 0x00000800 },\n+ [K230_DEV_PMU] = { 0x91000000, 0x00000C00 },\n+ [K230_DEV_RTC] = { 0x91000C00, 0x00000400 },\n+ [K230_DEV_CMU] = { 0x91100000, 0x00001000 },\n+ [K230_DEV_RMU] = { 0x91101000, 0x00001000 },\n+ [K230_DEV_BOOT] = { 0x91102000, 0x00001000 },\n+ [K230_DEV_PWR] = { 0x91103000, 0x00001000 },\n+ [K230_DEV_MAILBOX] = { 0x91104000, 0x00001000 },\n+ [K230_DEV_IOMUX] = { 0x91105000, 0x00000800 },\n+ [K230_DEV_TIMER] = { 0x91105800, 0x00000800 },\n+ [K230_DEV_WDT0] = { 0x91106000, 0x00000800 },\n+ [K230_DEV_WDT1] = { 0x91106800, 0x00000800 },\n+ [K230_DEV_TS] = { 0x91107000, 0x00000800 },\n+ [K230_DEV_HDI] = { 0x91107800, 0x00000800 },\n+ [K230_DEV_STC] = { 0x91108000, 0x00000800 },\n+ [K230_DEV_BOOTROM] = { 0x91200000, 0x00010000 },\n+ [K230_DEV_SECURITY] = { 0x91210000, 0x00008000 },\n+ [K230_DEV_UART0] = { 0x91400000, 0x00001000 },\n+ [K230_DEV_UART1] = { 0x91401000, 0x00001000 },\n+ [K230_DEV_UART2] = { 0x91402000, 0x00001000 },\n+ [K230_DEV_UART3] = { 0x91403000, 0x00001000 },\n+ [K230_DEV_UART4] = { 0x91404000, 0x00001000 },\n+ [K230_DEV_I2C0] = { 0x91405000, 0x00001000 },\n+ [K230_DEV_I2C1] = { 0x91406000, 0x00001000 },\n+ [K230_DEV_I2C2] = { 0x91407000, 0x00001000 },\n+ [K230_DEV_I2C3] = { 0x91408000, 0x00001000 },\n+ [K230_DEV_I2C4] = { 0x91409000, 0x00001000 },\n+ [K230_DEV_PWM] = { 0x9140A000, 0x00001000 },\n+ [K230_DEV_GPIO0] = { 0x9140B000, 0x00001000 },\n+ [K230_DEV_GPIO1] = { 0x9140C000, 0x00001000 },\n+ [K230_DEV_ADC] = { 0x9140D000, 0x00001000 },\n+ [K230_DEV_CODEC] = { 0x9140E000, 0x00001000 },\n+ [K230_DEV_I2S] = { 0x9140F000, 0x00001000 },\n+ [K230_DEV_USB0] = { 0x91500000, 0x00010000 },\n+ [K230_DEV_USB1] = { 0x91540000, 0x00010000 },\n+ [K230_DEV_SD0] = { 0x91580000, 0x00001000 },\n+ [K230_DEV_SD1] = { 0x91581000, 0x00001000 },\n+ [K230_DEV_QSPI0] = { 0x91582000, 0x00001000 },\n+ [K230_DEV_QSPI1] = { 0x91583000, 0x00001000 },\n+ [K230_DEV_SPI] = { 0x91584000, 0x00001000 },\n+ [K230_DEV_HI_SYS_CFG] = { 0x91585000, 0x00000400 },\n+ [K230_DEV_DDRC_CFG] = { 0x98000000, 0x02000000 },\n+ [K230_DEV_FLASH] = { 0xC0000000, 0x08000000 },\n+ [K230_DEV_PLIC] = { 0xF00000000, 0x00400000 },\n+ [K230_DEV_CLINT] = { 0xF04000000, 0x00400000 },\n+};\n+\n+static void k230_soc_init(Object *obj)\n+{\n+ K230SoCState *s = RISCV_K230_SOC(obj);\n+ RISCVHartArrayState *cpu0 = &s->c908_cpu;\n+\n+ object_initialize_child(obj, \"c908-cpu\", cpu0, TYPE_RISCV_HART_ARRAY);\n+ qdev_prop_set_uint32(DEVICE(cpu0), \"hartid-base\", 0);\n+ qdev_prop_set_string(DEVICE(cpu0), \"cpu-type\", TYPE_RISCV_CPU_THEAD_C908);\n+ qdev_prop_set_uint64(DEVICE(cpu0), \"resetvec\",\n+ memmap[K230_DEV_BOOTROM].base);\n+}\n+\n+static DeviceState *k230_create_plic(int base_hartid, int hartid_count)\n+{\n+ g_autofree char *plic_hart_config = NULL;\n+\n+ /* Per-socket PLIC hart topology configuration string */\n+ plic_hart_config = riscv_plic_hart_config_string(hartid_count);\n+\n+ /* Per-socket PLIC */\n+ return sifive_plic_create(memmap[K230_DEV_PLIC].base,\n+ plic_hart_config, hartid_count, base_hartid,\n+ K230_PLIC_NUM_SOURCES,\n+ K230_PLIC_NUM_PRIORITIES,\n+ K230_PLIC_PRIORITY_BASE, K230_PLIC_PENDING_BASE,\n+ K230_PLIC_ENABLE_BASE, K230_PLIC_ENABLE_STRIDE,\n+ K230_PLIC_CONTEXT_BASE,\n+ K230_PLIC_CONTEXT_STRIDE,\n+ memmap[K230_DEV_PLIC].size);\n+}\n+\n+static void k230_soc_realize(DeviceState *dev, Error **errp)\n+{\n+ K230SoCState *s = RISCV_K230_SOC(dev);\n+ MemoryRegion *sys_mem = get_system_memory();\n+ int c908_cpus;\n+\n+ sysbus_realize(SYS_BUS_DEVICE(&s->c908_cpu), &error_fatal);\n+\n+ c908_cpus = s->c908_cpu.num_harts;\n+\n+ /* SRAM */\n+ memory_region_init_ram(&s->sram, OBJECT(dev), \"sram\",\n+ memmap[K230_DEV_SRAM].size, &error_fatal);\n+ memory_region_add_subregion(sys_mem, memmap[K230_DEV_SRAM].base,\n+ &s->sram);\n+\n+ /* BootROM */\n+ memory_region_init_rom(&s->bootrom, OBJECT(dev), \"bootrom\",\n+ memmap[K230_DEV_BOOTROM].size, &error_fatal);\n+ memory_region_add_subregion(sys_mem, memmap[K230_DEV_BOOTROM].base,\n+ &s->bootrom);\n+\n+ /* PLIC */\n+ s->c908_plic = k230_create_plic(C908_CPU_HARTID, c908_cpus);\n+\n+ /* CLINT */\n+ riscv_aclint_swi_create(memmap[K230_DEV_CLINT].base,\n+ C908_CPU_HARTID, c908_cpus, false);\n+ riscv_aclint_mtimer_create(memmap[K230_DEV_CLINT].base + 0x4000,\n+ RISCV_ACLINT_DEFAULT_MTIMER_SIZE,\n+ C908_CPU_HARTID, c908_cpus,\n+ RISCV_ACLINT_DEFAULT_MTIMECMP,\n+ RISCV_ACLINT_DEFAULT_MTIME,\n+ RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true);\n+\n+ /* UART */\n+ serial_mm_init(sys_mem, memmap[K230_DEV_UART0].base, 2,\n+ qdev_get_gpio_in(DEVICE(s->c908_plic), K230_UART0_IRQ),\n+ 399193, serial_hd(0), DEVICE_LITTLE_ENDIAN);\n+ serial_mm_init(sys_mem, memmap[K230_DEV_UART1].base, 2,\n+ qdev_get_gpio_in(DEVICE(s->c908_plic), K230_UART1_IRQ),\n+ 399193, serial_hd(1), DEVICE_LITTLE_ENDIAN);\n+ serial_mm_init(sys_mem, memmap[K230_DEV_UART2].base, 2,\n+ qdev_get_gpio_in(DEVICE(s->c908_plic), K230_UART2_IRQ),\n+ 399193, serial_hd(2), DEVICE_LITTLE_ENDIAN);\n+ serial_mm_init(sys_mem, memmap[K230_DEV_UART3].base, 2,\n+ qdev_get_gpio_in(DEVICE(s->c908_plic), K230_UART3_IRQ),\n+ 399193, serial_hd(3), DEVICE_LITTLE_ENDIAN);\n+ serial_mm_init(sys_mem, memmap[K230_DEV_UART4].base, 2,\n+ qdev_get_gpio_in(DEVICE(s->c908_plic), K230_UART4_IRQ),\n+ 399193, serial_hd(4), DEVICE_LITTLE_ENDIAN);\n+\n+ /* unimplemented devices */\n+ create_unimplemented_device(\"kpu.l2-cache\",\n+ memmap[K230_DEV_KPU_L2_CACHE].base,\n+ memmap[K230_DEV_KPU_L2_CACHE].size);\n+\n+ create_unimplemented_device(\"kpu_cfg\", memmap[K230_DEV_KPU_CFG].base,\n+ memmap[K230_DEV_KPU_CFG].size);\n+\n+ create_unimplemented_device(\"fft\", memmap[K230_DEV_FFT].base,\n+ memmap[K230_DEV_FFT].size);\n+\n+ create_unimplemented_device(\"2d-engine.ai\",\n+ memmap[K230_DEV_AI_2D_ENGINE].base,\n+ memmap[K230_DEV_AI_2D_ENGINE].size);\n+\n+ create_unimplemented_device(\"gsdma\", memmap[K230_DEV_GSDMA].base,\n+ memmap[K230_DEV_GSDMA].size);\n+\n+ create_unimplemented_device(\"dma\", memmap[K230_DEV_DMA].base,\n+ memmap[K230_DEV_DMA].size);\n+\n+ create_unimplemented_device(\"decomp-gzip\",\n+ memmap[K230_DEV_DECOMP_GZIP].base,\n+ memmap[K230_DEV_DECOMP_GZIP].size);\n+\n+ create_unimplemented_device(\"2d-engine.non-ai\",\n+ memmap[K230_DEV_NON_AI_2D].base,\n+ memmap[K230_DEV_NON_AI_2D].size);\n+\n+ create_unimplemented_device(\"isp\", memmap[K230_DEV_ISP].base,\n+ memmap[K230_DEV_ISP].size);\n+\n+ create_unimplemented_device(\"dewarp\", memmap[K230_DEV_DEWARP].base,\n+ memmap[K230_DEV_DEWARP].size);\n+\n+ create_unimplemented_device(\"rx-csi\", memmap[K230_DEV_RX_CSI].base,\n+ memmap[K230_DEV_RX_CSI].size);\n+\n+ create_unimplemented_device(\"vpu\", memmap[K230_DEV_H264].base,\n+ memmap[K230_DEV_H264].size);\n+\n+ create_unimplemented_device(\"gpu\", memmap[K230_DEV_2P5D].base,\n+ memmap[K230_DEV_2P5D].size);\n+\n+ create_unimplemented_device(\"vo\", memmap[K230_DEV_VO].base,\n+ memmap[K230_DEV_VO].size);\n+\n+ create_unimplemented_device(\"vo_cfg\", memmap[K230_DEV_VO_CFG].base,\n+ memmap[K230_DEV_VO_CFG].size);\n+\n+ create_unimplemented_device(\"3d-engine\", memmap[K230_DEV_3D_ENGINE].base,\n+ memmap[K230_DEV_3D_ENGINE].size);\n+\n+ create_unimplemented_device(\"pmu\", memmap[K230_DEV_PMU].base,\n+ memmap[K230_DEV_PMU].size);\n+\n+ create_unimplemented_device(\"rtc\", memmap[K230_DEV_RTC].base,\n+ memmap[K230_DEV_RTC].size);\n+\n+ create_unimplemented_device(\"cmu\", memmap[K230_DEV_CMU].base,\n+ memmap[K230_DEV_CMU].size);\n+\n+ create_unimplemented_device(\"rmu\", memmap[K230_DEV_RMU].base,\n+ memmap[K230_DEV_RMU].size);\n+\n+ create_unimplemented_device(\"boot\", memmap[K230_DEV_BOOT].base,\n+ memmap[K230_DEV_BOOT].size);\n+\n+ create_unimplemented_device(\"pwr\", memmap[K230_DEV_PWR].base,\n+ memmap[K230_DEV_PWR].size);\n+\n+ create_unimplemented_device(\"ipcm\", memmap[K230_DEV_MAILBOX].base,\n+ memmap[K230_DEV_MAILBOX].size);\n+\n+ create_unimplemented_device(\"iomux\", memmap[K230_DEV_IOMUX].base,\n+ memmap[K230_DEV_IOMUX].size);\n+\n+ create_unimplemented_device(\"timer\", memmap[K230_DEV_TIMER].base,\n+ memmap[K230_DEV_TIMER].size);\n+\n+ create_unimplemented_device(\"wdt0\", memmap[K230_DEV_WDT0].base,\n+ memmap[K230_DEV_WDT0].size);\n+\n+ create_unimplemented_device(\"wdt1\", memmap[K230_DEV_WDT1].base,\n+ memmap[K230_DEV_WDT1].size);\n+\n+ create_unimplemented_device(\"ts\", memmap[K230_DEV_TS].base,\n+ memmap[K230_DEV_TS].size);\n+\n+ create_unimplemented_device(\"hdi\", memmap[K230_DEV_HDI].base,\n+ memmap[K230_DEV_HDI].size);\n+\n+ create_unimplemented_device(\"stc\", memmap[K230_DEV_STC].base,\n+ memmap[K230_DEV_STC].size);\n+\n+ create_unimplemented_device(\"security\", memmap[K230_DEV_SECURITY].base,\n+ memmap[K230_DEV_SECURITY].size);\n+\n+ create_unimplemented_device(\"i2c0\", memmap[K230_DEV_I2C0].base,\n+ memmap[K230_DEV_I2C0].size);\n+\n+ create_unimplemented_device(\"i2c1\", memmap[K230_DEV_I2C1].base,\n+ memmap[K230_DEV_I2C1].size);\n+\n+ create_unimplemented_device(\"i2c2\", memmap[K230_DEV_I2C2].base,\n+ memmap[K230_DEV_I2C2].size);\n+\n+ create_unimplemented_device(\"i2c3\", memmap[K230_DEV_I2C3].base,\n+ memmap[K230_DEV_I2C3].size);\n+\n+ create_unimplemented_device(\"i2c4\", memmap[K230_DEV_I2C4].base,\n+ memmap[K230_DEV_I2C4].size);\n+\n+ create_unimplemented_device(\"pwm\", memmap[K230_DEV_PWM].base,\n+ memmap[K230_DEV_PWM].size);\n+\n+ create_unimplemented_device(\"gpio0\", memmap[K230_DEV_GPIO0].base,\n+ memmap[K230_DEV_GPIO0].size);\n+\n+ create_unimplemented_device(\"gpio1\", memmap[K230_DEV_GPIO1].base,\n+ memmap[K230_DEV_GPIO1].size);\n+\n+ create_unimplemented_device(\"adc\", memmap[K230_DEV_ADC].base,\n+ memmap[K230_DEV_ADC].size);\n+\n+ create_unimplemented_device(\"codec\", memmap[K230_DEV_CODEC].base,\n+ memmap[K230_DEV_CODEC].size);\n+\n+ create_unimplemented_device(\"i2s\", memmap[K230_DEV_I2S].base,\n+ memmap[K230_DEV_I2S].size);\n+\n+ create_unimplemented_device(\"usb0\", memmap[K230_DEV_USB0].base,\n+ memmap[K230_DEV_USB0].size);\n+\n+ create_unimplemented_device(\"usb1\", memmap[K230_DEV_USB1].base,\n+ memmap[K230_DEV_USB1].size);\n+\n+ create_unimplemented_device(\"sd0\", memmap[K230_DEV_SD0].base,\n+ memmap[K230_DEV_SD0].size);\n+\n+ create_unimplemented_device(\"sd1\", memmap[K230_DEV_SD1].base,\n+ memmap[K230_DEV_SD1].size);\n+\n+ create_unimplemented_device(\"qspi0\", memmap[K230_DEV_QSPI0].base,\n+ memmap[K230_DEV_QSPI0].size);\n+\n+ create_unimplemented_device(\"qspi1\", memmap[K230_DEV_QSPI1].base,\n+ memmap[K230_DEV_QSPI1].size);\n+\n+ create_unimplemented_device(\"spi\", memmap[K230_DEV_SPI].base,\n+ memmap[K230_DEV_SPI].size);\n+\n+ create_unimplemented_device(\"hi_sys_cfg\", memmap[K230_DEV_HI_SYS_CFG].base,\n+ memmap[K230_DEV_HI_SYS_CFG].size);\n+\n+ create_unimplemented_device(\"ddrc_cfg\", memmap[K230_DEV_DDRC_CFG].base,\n+ memmap[K230_DEV_DDRC_CFG].size);\n+\n+ create_unimplemented_device(\"flash\", memmap[K230_DEV_FLASH].base,\n+ memmap[K230_DEV_FLASH].size);\n+}\n+\n+static void k230_soc_class_init(ObjectClass *oc, const void *data)\n+{\n+ DeviceClass *dc = DEVICE_CLASS(oc);\n+\n+ dc->realize = k230_soc_realize;\n+}\n+\n+static const TypeInfo k230_soc_type_info = {\n+ .name = TYPE_RISCV_K230_SOC,\n+ .parent = TYPE_DEVICE,\n+ .instance_size = sizeof(K230SoCState),\n+ .instance_init = k230_soc_init,\n+ .class_init = k230_soc_class_init,\n+};\n+\n+static void k230_soc_register_types(void)\n+{\n+ type_register_static(&k230_soc_type_info);\n+}\n+\n+type_init(k230_soc_register_types)\n+\n+static void k230_machine_done(Notifier *notifier, void *data)\n+{\n+ K230MachineState *s = container_of(notifier, K230MachineState,\n+ machine_done);\n+ MachineState *machine = MACHINE(s);\n+ hwaddr start_addr = memmap[K230_DEV_DDRC].base;\n+ target_ulong firmware_end_addr, kernel_start_addr;\n+ const char *firmware_name = riscv_default_firmware_name(&s->soc.c908_cpu);\n+ uint64_t kernel_entry = 0;\n+ RISCVBootInfo boot_info;\n+\n+ firmware_end_addr = riscv_find_and_load_firmware(machine, firmware_name,\n+ &start_addr, NULL);\n+\n+ /* Mask ROM reset vector */\n+ uint32_t reset_vec[] = {\n+ /* 0x91200000: auipc t0, 0x0 */ 0x00000297,\n+ /* 0x91200004: addi t0, t0, 36 # <trap> */ 0x03028293,\n+ /* 0x91200008: csrw mtvec, t0 */ 0x30529073,\n+ /* 0x9120000C: csrr a0, misa */ 0x301012F3,\n+ /* 0x91200010: lui t0, 0x1 */ 0x000012B7,\n+ /* 0x91200014: slli t0, t0, 1 */ 0x00129293,\n+ /* 0x91200018: and t0, a0, t0 */ 0x005572B3,\n+ /* 0x9120001C: bnez t0, loop */ 0x00511063,\n+ /* entry: */\n+ /* 0x91200020: addiw t0, zero, 1 */ 0x0010029b,\n+ /* 0x91200024: slli t0, t0, 0x1b */ 0x01b29293,\n+ /* 0x91200028: jr t0 # uboot 0x8000000 */ 0x00028067,\n+ /* loop: */\n+ /* 0x9120002C: j 0x9120002C # <loop> */ 0x0000006f,\n+ /* trap: */\n+ /* 0x91200030: j 0x91200030 # <trap> */ 0x0000006f,\n+ };\n+\n+ /* copy in the reset vector in little_endian byte order */\n+ for (int i = 0; i < sizeof(reset_vec) >> 2; i++) {\n+ reset_vec[i] = cpu_to_le32(reset_vec[i]);\n+ }\n+ rom_add_blob_fixed_as(\"mrom.reset\", reset_vec, sizeof(reset_vec),\n+ memmap[K230_DEV_BOOTROM].base, &address_space_memory);\n+\n+ riscv_boot_info_init(&boot_info, &s->soc.c908_cpu);\n+\n+ if (machine->kernel_filename && !kernel_entry) {\n+ kernel_start_addr = riscv_calc_kernel_start_addr(&boot_info,\n+ firmware_end_addr);\n+ riscv_load_kernel(machine, &boot_info, kernel_start_addr,\n+ true, NULL);\n+ kernel_entry = boot_info.image_low_addr;\n+ }\n+}\n+\n+static void k230_machine_init(MachineState *machine)\n+{\n+ MachineClass *mc = MACHINE_GET_CLASS(machine);\n+\n+ K230MachineState *s = RISCV_K230_MACHINE(machine);\n+ MemoryRegion *sys_mem = get_system_memory();\n+\n+ if (machine->ram_size < mc->default_ram_size) {\n+ char *sz = size_to_str(mc->default_ram_size);\n+ error_report(\"Invalid RAM size, should be %s\", sz);\n+ g_free(sz);\n+ exit(EXIT_FAILURE);\n+ }\n+\n+ /* Initialize SoC */\n+ object_initialize_child(OBJECT(machine), \"soc\", &s->soc,\n+ TYPE_RISCV_K230_SOC);\n+ qdev_realize(DEVICE(&s->soc), NULL, &error_fatal);\n+\n+ /* Data Memory */\n+ memory_region_add_subregion(sys_mem, memmap[K230_DEV_DDRC].base,\n+ machine->ram);\n+\n+ s->machine_done.notify = k230_machine_done;\n+ qemu_add_machine_init_done_notifier(&s->machine_done);\n+}\n+\n+static void k230_machine_instance_init(Object *obj)\n+{\n+}\n+\n+static void k230_machine_class_init(ObjectClass *oc, const void *data)\n+{\n+ MachineClass *mc = MACHINE_CLASS(oc);\n+\n+ mc->desc = \"RISC-V Board compatible with Kendryte K230 SDK\";\n+ mc->init = k230_machine_init;\n+ mc->default_cpus = 2;\n+ mc->default_ram_id = \"riscv.K230.ram\"; /* DDR */\n+ mc->default_ram_size = memmap[K230_DEV_DDRC].size;\n+}\n+\n+static const TypeInfo k230_machine_typeinfo = {\n+ .name = TYPE_RISCV_K230_MACHINE,\n+ .parent = TYPE_MACHINE,\n+ .class_init = k230_machine_class_init,\n+ .instance_init = k230_machine_instance_init,\n+ .instance_size = sizeof(K230MachineState),\n+};\n+\n+static void k230_machine_init_register_types(void)\n+{\n+ type_register_static(&k230_machine_typeinfo);\n+}\n+\n+type_init(k230_machine_init_register_types)\ndiff --git a/hw/riscv/meson.build b/hw/riscv/meson.build\nindex 533472e22a..09cf855984 100644\n--- a/hw/riscv/meson.build\n+++ b/hw/riscv/meson.build\n@@ -14,8 +14,8 @@ riscv_ss.add(when: 'CONFIG_RISCV_IOMMU', if_true: files(\n \t'riscv-iommu.c', 'riscv-iommu-pci.c', 'riscv-iommu-sys.c', 'riscv-iommu-hpm.c'))\n riscv_ss.add(when: 'CONFIG_MICROBLAZE_V', if_true: files('microblaze-v-generic.c'))\n riscv_ss.add(when: 'CONFIG_XIANGSHAN_KUNMINGHU', if_true: files('xiangshan_kmh.c'))\n-\n riscv_ss.add(when: 'CONFIG_RISCV_MIPS_CPS', if_true: files('cps.c'))\n riscv_ss.add(when: 'CONFIG_MIPS_BOSTON_AIA', if_true: files('boston-aia.c'))\n+riscv_ss.add(when: 'CONFIG_K230', if_true: files('k230.c'))\n \n hw_arch += {'riscv': riscv_ss}\ndiff --git a/include/hw/riscv/k230.h b/include/hw/riscv/k230.h\nnew file mode 100644\nindex 0000000000..830175b756\n--- /dev/null\n+++ b/include/hw/riscv/k230.h\n@@ -0,0 +1,150 @@\n+/*\n+ * QEMU RISC-V Virt Board Compatible with kendryte K230 SDK\n+ *\n+ * Copyright (c) 2025 Chao Liu <chao.liu.zevorn@gmail.com>\n+ *\n+ * SPDX-License-Identifier: GPL-2.0-or-later\n+ *\n+ * Provides a board compatible with the kendryte K230 SDK\n+ *\n+ * Documentation: K230_Technical_Reference_Manual_V0.3.1_20241118.pdf\n+ *\n+ * For more information, see <https://www.kendryte.com/en/proDetail/230>\n+ *\n+ * This program is free software; you can redistribute it and/or modify it\n+ * under the terms and conditions of the GNU General Public License,\n+ * version 2 or later, as published by the Free Software Foundation.\n+ *\n+ * This program is distributed in the hope it will be useful, but WITHOUT\n+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n+ * more details.\n+ *\n+ * You should have received a copy of the GNU General Public License along with\n+ * this program. If not, see <http://www.gnu.org/licenses/>.\n+ */\n+#ifndef HW_K230_H\n+#define HW_K230_H\n+\n+#include \"hw/core/boards.h\"\n+#include \"hw/riscv/riscv_hart.h\"\n+\n+#define C908_CPU_HARTID (0)\n+\n+#define TYPE_RISCV_K230_SOC \"riscv.k230.soc\"\n+#define RISCV_K230_SOC(obj) \\\n+ OBJECT_CHECK(K230SoCState, (obj), TYPE_RISCV_K230_SOC)\n+\n+typedef struct K230SoCState {\n+ /*< private >*/\n+ DeviceState parent_obj;\n+\n+ /*< public >*/\n+ RISCVHartArrayState c908_cpu; /* Small core */\n+\n+ MemoryRegion sram;\n+ MemoryRegion bootrom;\n+\n+ DeviceState *c908_plic;\n+} K230SoCState;\n+\n+#define TYPE_RISCV_K230_MACHINE MACHINE_TYPE_NAME(\"k230\")\n+#define RISCV_K230_MACHINE(obj) \\\n+ OBJECT_CHECK(K230MachineState, (obj), TYPE_RISCV_K230_MACHINE)\n+\n+typedef struct K230MachineState {\n+ /*< private >*/\n+ MachineState parent_obj;\n+\n+ /*< public >*/\n+ K230SoCState soc;\n+ Notifier machine_done;\n+} K230MachineState;\n+\n+enum {\n+ K230_DEV_DDRC,\n+ K230_DEV_KPU_L2_CACHE,\n+ K230_DEV_SRAM,\n+ K230_DEV_KPU_CFG,\n+ K230_DEV_FFT,\n+ K230_DEV_AI_2D_ENGINE,\n+ K230_DEV_GSDMA,\n+ K230_DEV_DMA,\n+ K230_DEV_DECOMP_GZIP,\n+ K230_DEV_NON_AI_2D,\n+ K230_DEV_ISP,\n+ K230_DEV_DEWARP,\n+ K230_DEV_RX_CSI,\n+ K230_DEV_H264,\n+ K230_DEV_2P5D,\n+ K230_DEV_VO,\n+ K230_DEV_VO_CFG,\n+ K230_DEV_3D_ENGINE,\n+ K230_DEV_PMU,\n+ K230_DEV_RTC,\n+ K230_DEV_CMU,\n+ K230_DEV_RMU,\n+ K230_DEV_BOOT,\n+ K230_DEV_PWR,\n+ K230_DEV_MAILBOX,\n+ K230_DEV_IOMUX,\n+ K230_DEV_TIMER,\n+ K230_DEV_WDT0,\n+ K230_DEV_WDT1,\n+ K230_DEV_TS,\n+ K230_DEV_HDI,\n+ K230_DEV_STC,\n+ K230_DEV_BOOTROM,\n+ K230_DEV_SECURITY,\n+ K230_DEV_UART0,\n+ K230_DEV_UART1,\n+ K230_DEV_UART2,\n+ K230_DEV_UART3,\n+ K230_DEV_UART4,\n+ K230_DEV_I2C0,\n+ K230_DEV_I2C1,\n+ K230_DEV_I2C2,\n+ K230_DEV_I2C3,\n+ K230_DEV_I2C4,\n+ K230_DEV_PWM,\n+ K230_DEV_GPIO0,\n+ K230_DEV_GPIO1,\n+ K230_DEV_ADC,\n+ K230_DEV_CODEC,\n+ K230_DEV_I2S,\n+ K230_DEV_USB0,\n+ K230_DEV_USB1,\n+ K230_DEV_SD0,\n+ K230_DEV_SD1,\n+ K230_DEV_QSPI0,\n+ K230_DEV_QSPI1,\n+ K230_DEV_SPI,\n+ K230_DEV_HI_SYS_CFG,\n+ K230_DEV_DDRC_CFG,\n+ K230_DEV_FLASH,\n+ K230_DEV_PLIC,\n+ K230_DEV_CLINT,\n+};\n+\n+enum {\n+ K230_UART0_IRQ = 16,\n+ K230_UART1_IRQ = 17,\n+ K230_UART2_IRQ = 18,\n+ K230_UART3_IRQ = 19,\n+ K230_UART4_IRQ = 20,\n+};\n+\n+/*\n+ * Integrates with the interrupt controller (PLIC),\n+ * which can process 208 interrupt external sources\n+ */\n+#define K230_PLIC_NUM_SOURCES 208\n+#define K230_PLIC_NUM_PRIORITIES 7\n+#define K230_PLIC_PRIORITY_BASE 0x00\n+#define K230_PLIC_PENDING_BASE 0x1000\n+#define K230_PLIC_ENABLE_BASE 0x2000\n+#define K230_PLIC_ENABLE_STRIDE 0x80\n+#define K230_PLIC_CONTEXT_BASE 0x200000\n+#define K230_PLIC_CONTEXT_STRIDE 0x1000\n+\n+#endif\n", "prefixes": [ "v6", "2/5" ] }