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GET /api/1.2/patches/2224401/?format=api
{ "id": 2224401, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2224401/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260417105618.3621-30-magnuskulke@linux.microsoft.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.2/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260417105618.3621-30-magnuskulke@linux.microsoft.com>", "list_archive_url": null, "date": "2026-04-17T10:56:13", "name": "[29/34] target/i386/mshv: migrate pending ints/excs", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "2c33c6b122a58f662bc8e00f0f207be912d8eccb", "submitter": { "id": 90753, "url": "http://patchwork.ozlabs.org/api/1.2/people/90753/?format=api", "name": "Magnus Kulke", "email": "magnuskulke@linux.microsoft.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260417105618.3621-30-magnuskulke@linux.microsoft.com/mbox/", "series": [ { "id": 500310, "url": "http://patchwork.ozlabs.org/api/1.2/series/500310/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500310", "date": "2026-04-17T10:55:44", "name": "Add migration support to the MSHV accelerator", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/500310/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2224401/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2224401/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=linux.microsoft.com header.i=@linux.microsoft.com\n header.a=rsa-sha256 header.s=default header.b=l0W1urtz;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fxsMH2zWbz1yJ8\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 17 Apr 2026 20:59:07 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1wDgu4-00053R-O3; Fri, 17 Apr 2026 06:58:28 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <magnuskulke@linux.microsoft.com>)\n id 1wDgu1-0004d2-2E\n for qemu-devel@nongnu.org; Fri, 17 Apr 2026 06:58:25 -0400", "from linux.microsoft.com ([13.77.154.182])\n by eggs.gnu.org with esmtp (Exim 4.90_1)\n (envelope-from <magnuskulke@linux.microsoft.com>) id 1wDgty-0001st-Gr\n for qemu-devel@nongnu.org; Fri, 17 Apr 2026 06:58:24 -0400", "from DESKTOP-TUU1E5L.fritz.box (p5086d620.dip0.t-ipconnect.de\n [80.134.214.32])\n by linux.microsoft.com (Postfix) with ESMTPSA id 74E7120B703B;\n Fri, 17 Apr 2026 03:58:08 -0700 (PDT)" ], "DKIM-Filter": "OpenDKIM Filter v2.11.0 linux.microsoft.com 74E7120B703B", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com;\n s=default; t=1776423491;\n bh=OwK5aPSkKTlyX/GdZb57ht2F3r7x/kha1Hyji7w66N4=;\n h=From:To:Cc:Subject:Date:In-Reply-To:References:From;\n b=l0W1urtzsSxJOVhnhETHMGePW4gboLAc0OTkQ8MpBB+vlHkQPSFHIvQJhbjaSTaMv\n V70ueNCCqD4RFa7N/9IDeydpYlx7t2Zf2y606XDe8c64faIBcXUeeRa6143n+3PG/h\n h4s9UVkjDjXMyf2heCTQ2Ha8LM/IdHs2obCjdqf0=", "From": "Magnus Kulke <magnuskulke@linux.microsoft.com>", "To": "qemu-devel@nongnu.org", "Cc": "kvm@vger.kernel.org, Magnus Kulke <magnuskulke@microsoft.com>,\n Wei Liu <liuwe@microsoft.com>, \"Michael S. Tsirkin\" <mst@redhat.com>,\n\t=?utf-8?q?C=C3=A9dric_Le_Goater?= <clg@redhat.com>,\n Zhao Liu <zhao1.liu@intel.com>,\n Richard Henderson <richard.henderson@linaro.org>,\n Paolo Bonzini <pbonzini@redhat.com>, Wei Liu <wei.liu@kernel.org>,\n Magnus Kulke <magnuskulke@linux.microsoft.com>,\n Alex Williamson <alex@shazbot.org>,\n Marcel Apfelbaum <marcel.apfelbaum@gmail.com>, =?utf-8?q?Philippe_Mathieu-D?=\n\t=?utf-8?q?aud=C3=A9?= <philmd@linaro.org>,\n Marcelo Tosatti <mtosatti@redhat.com>", "Subject": "[PATCH 29/34] target/i386/mshv: migrate pending ints/excs", "Date": "Fri, 17 Apr 2026 12:56:13 +0200", "Message-Id": "<20260417105618.3621-30-magnuskulke@linux.microsoft.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20260417105618.3621-1-magnuskulke@linux.microsoft.com>", "References": "<20260417105618.3621-1-magnuskulke@linux.microsoft.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=13.77.154.182;\n envelope-from=magnuskulke@linux.microsoft.com; helo=linux.microsoft.com", "X-Spam_score_int": "-42", "X-Spam_score": "-4.3", "X-Spam_bar": "----", "X-Spam_report": "(-4.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, RCVD_IN_DNSWL_MED=-2.3,\n RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001,\n SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "We use PENDING_INTERRUPTION, INTERRUPT_STATE, PENDING_EVENT hv registers\nto map and roundtrip from/to CPUX86State.\n\nWe ignore HV_REGISTER_PENDING_EVENT1 which represent events for nested\nvirt contexts, as we don't support nested virt with MSHV currently.\n\nSigned-off-by: Magnus Kulke <magnuskulke@linux.microsoft.com>\n---\n include/hw/hyperv/hvgdk_mini.h | 3 +\n include/system/mshv_int.h | 13 +++\n target/i386/mshv/mshv-cpu.c | 168 +++++++++++++++++++++++++++++++++\n 3 files changed, 184 insertions(+)", "diff": "diff --git a/include/hw/hyperv/hvgdk_mini.h b/include/hw/hyperv/hvgdk_mini.h\nindex e987f59bb9..e3fd2530ac 100644\n--- a/include/hw/hyperv/hvgdk_mini.h\n+++ b/include/hw/hyperv/hvgdk_mini.h\n@@ -28,6 +28,9 @@ typedef enum hv_register_name {\n \n /* Pending Interruption Register */\n HV_REGISTER_PENDING_INTERRUPTION = 0x00010002,\n+ HV_REGISTER_INTERRUPT_STATE = 0x00010003,\n+ HV_REGISTER_PENDING_EVENT0 = 0x00010004,\n+ HV_REGISTER_PENDING_EVENT1 = 0x00010005,\n \n /* X64 User-Mode Registers */\n HV_X64_REGISTER_RAX = 0x00020000,\ndiff --git a/include/system/mshv_int.h b/include/system/mshv_int.h\nindex 7052f20a00..bc16b794b2 100644\n--- a/include/system/mshv_int.h\n+++ b/include/system/mshv_int.h\n@@ -18,6 +18,19 @@\n \n struct mshv_get_set_vp_state;\n \n+/*\n+ * Interruption-type encoding, used by the hypervisor in\n+ * hv_x64_pending_interruption_register.interruption_type\n+ * See TLFS 6.0 section 7.9.2, p55\n+ * https://learn.microsoft.com/en-us/virtualization/hyper-v-on-windows/tlfs/tlfs\n+ */\n+#define MSHV_HV_INTERRUPTION_TYPE_EXT_INT 0\n+#define MSHV_HV_INTERRUPTION_TYPE_NMI 2\n+#define MSHV_HV_INTERRUPTION_TYPE_HW_EXC 3\n+#define MSHV_HV_INTERRUPTION_TYPE_SW_INT 4\n+#define MSHV_HV_INTERRUPTION_TYPE_PRIV_SW_EXC 5\n+#define MSHV_HV_INTERRUPTION_TYPE_SW_EXC 6\n+\n typedef struct hyperv_message hv_message;\n \n typedef struct MshvHvCallArgs {\ndiff --git a/target/i386/mshv/mshv-cpu.c b/target/i386/mshv/mshv-cpu.c\nindex 43dbbd6fbd..517b38a32d 100644\n--- a/target/i386/mshv/mshv-cpu.c\n+++ b/target/i386/mshv/mshv-cpu.c\n@@ -584,6 +584,164 @@ static int load_regs(CPUState *cpu)\n return 0;\n }\n \n+static int get_vcpu_events(CPUState *cpu)\n+{\n+ X86CPU *x86cpu = X86_CPU(cpu);\n+ CPUX86State *env = &x86cpu->env;\n+ struct hv_register_assoc assocs[] = {\n+ { .name = HV_REGISTER_PENDING_INTERRUPTION },\n+ { .name = HV_REGISTER_INTERRUPT_STATE },\n+ { .name = HV_REGISTER_PENDING_EVENT0 },\n+ };\n+ union hv_x64_pending_interruption_register pending_int;\n+ union hv_x64_interrupt_state_register int_state;\n+ union hv_x64_pending_exception_event pending_exc;\n+ int ret;\n+\n+ ret = mshv_get_generic_regs(cpu, assocs, ARRAY_SIZE(assocs));\n+ if (ret < 0) {\n+ error_report(\"failed to get vcpu event registers\");\n+ return -1;\n+ }\n+\n+ pending_int.as_uint64 = assocs[0].value.reg64;\n+ int_state.as_uint64 = assocs[1].value.reg64;\n+ pending_exc = assocs[2].value.pending_exception_event;\n+\n+ /* Clear previous state. injected ints/excs are blanked w/ -1 */\n+ env->interrupt_injected = -1;\n+ env->soft_interrupt = 0;\n+ env->exception_injected = 0;\n+ env->exception_pending = 0;\n+ env->exception_nr = -1;\n+ env->has_error_code = 0;\n+ env->error_code = 0;\n+ env->exception_has_payload = 0;\n+ env->exception_payload = 0;\n+ env->nmi_injected = 0;\n+\n+ if (pending_int.interruption_pending) {\n+ switch (pending_int.interruption_type) {\n+ case MSHV_HV_INTERRUPTION_TYPE_EXT_INT:\n+ env->interrupt_injected = pending_int.interruption_vector;\n+ break;\n+ case MSHV_HV_INTERRUPTION_TYPE_NMI:\n+ env->nmi_injected = 1;\n+ break;\n+ case MSHV_HV_INTERRUPTION_TYPE_HW_EXC:\n+ env->exception_injected = 1;\n+ env->exception_nr = pending_int.interruption_vector;\n+ env->has_error_code = pending_int.deliver_error_code;\n+ env->error_code = pending_int.error_code;\n+ break;\n+ case MSHV_HV_INTERRUPTION_TYPE_SW_INT:\n+ env->interrupt_injected = pending_int.interruption_vector;\n+ env->soft_interrupt = 1;\n+ break;\n+ case MSHV_HV_INTERRUPTION_TYPE_SW_EXC:\n+ case MSHV_HV_INTERRUPTION_TYPE_PRIV_SW_EXC:\n+ env->exception_injected = 1;\n+ env->exception_nr = pending_int.interruption_vector;\n+ env->has_error_code = pending_int.deliver_error_code;\n+ env->error_code = pending_int.error_code;\n+ break;\n+ default:\n+ error_report(\"unknown interruption type %u\",\n+ pending_int.interruption_type);\n+ return -EINVAL;\n+ }\n+ }\n+\n+ /* disabled for one instr after STI, MOV/POP SS, see hvf_store_events() */\n+ if (int_state.interrupt_shadow) {\n+ env->hflags |= HF_INHIBIT_IRQ_MASK;\n+ } else {\n+ env->hflags &= ~HF_INHIBIT_IRQ_MASK;\n+ }\n+\n+ /* see kvm_get_vcpu_events(), hvf_store_events() */\n+ if (int_state.nmi_masked) {\n+ env->hflags2 |= HF2_NMI_MASK;\n+ } else {\n+ env->hflags2 &= ~HF2_NMI_MASK;\n+ }\n+\n+ /* HV_REGISTER_PENDING_EVENT0: pending exception not yet injected */\n+ if (pending_exc.event_pending) {\n+ env->exception_pending = 1;\n+ env->exception_nr = pending_exc.vector;\n+ env->has_error_code = pending_exc.deliver_error_code;\n+ env->error_code = pending_exc.error_code;\n+ env->exception_has_payload = (pending_exc.exception_parameter != 0);\n+ env->exception_payload = pending_exc.exception_parameter;\n+ }\n+\n+ /*\n+ * Ignoring HV_REGISTER_PENDING_EVENT1, virtualization fault events, MSHV\n+ * does not support nested virtualization.\n+ */\n+\n+ return 0;\n+}\n+\n+static int set_vcpu_events(const CPUState *cpu)\n+{\n+ X86CPU *x86cpu = X86_CPU(cpu);\n+ CPUX86State *env = &x86cpu->env;\n+ union hv_x64_pending_interruption_register pending_int = { 0 };\n+ union hv_x64_interrupt_state_register int_state = { 0 };\n+ union hv_x64_pending_exception_event pending_exc = { 0 };\n+ struct hv_register_assoc assocs[3];\n+ int ret;\n+\n+ /* build pending_int from CPUX86State */\n+ if (env->exception_injected) {\n+ pending_int.interruption_pending = 1;\n+ pending_int.interruption_type = MSHV_HV_INTERRUPTION_TYPE_HW_EXC;\n+ pending_int.interruption_vector = env->exception_nr;\n+ pending_int.deliver_error_code = env->has_error_code;\n+ pending_int.error_code = env->error_code;\n+ } else if (env->nmi_injected) {\n+ pending_int.interruption_pending = 1;\n+ pending_int.interruption_type = MSHV_HV_INTERRUPTION_TYPE_NMI;\n+ pending_int.interruption_vector = EXCP02_NMI;\n+ } else if (env->interrupt_injected >= 0) {\n+ pending_int.interruption_pending = 1;\n+ pending_int.interruption_type = env->soft_interrupt\n+ ? MSHV_HV_INTERRUPTION_TYPE_SW_INT\n+ : MSHV_HV_INTERRUPTION_TYPE_EXT_INT;\n+ pending_int.interruption_vector = env->interrupt_injected;\n+ }\n+\n+ /* build int_state, normalize to bool */\n+ int_state.interrupt_shadow = !!(env->hflags & HF_INHIBIT_IRQ_MASK);\n+ int_state.nmi_masked = !!(env->hflags2 & HF2_NMI_MASK);\n+\n+ /* build pending_exc */\n+ if (env->exception_pending) {\n+ pending_exc.event_pending = 1;\n+ pending_exc.vector = env->exception_nr;\n+ pending_exc.deliver_error_code = env->has_error_code;\n+ pending_exc.error_code = env->error_code;\n+ pending_exc.exception_parameter = env->exception_payload;\n+ }\n+\n+ assocs[0].name = HV_REGISTER_PENDING_INTERRUPTION;\n+ assocs[0].value.reg64 = pending_int.as_uint64;\n+ assocs[1].name = HV_REGISTER_INTERRUPT_STATE;\n+ assocs[1].value.reg64 = int_state.as_uint64;\n+ assocs[2].name = HV_REGISTER_PENDING_EVENT0;\n+ assocs[2].value.pending_exception_event = pending_exc;\n+\n+ ret = mshv_set_generic_regs(cpu, assocs, ARRAY_SIZE(assocs));\n+ if (ret < 0) {\n+ error_report(\"failed to set vcpu event registers\");\n+ return -1;\n+ }\n+\n+ return 0;\n+}\n+\n int mshv_arch_load_vcpu_state(CPUState *cpu)\n {\n int ret;\n@@ -623,6 +781,11 @@ int mshv_arch_load_vcpu_state(CPUState *cpu)\n return ret;\n }\n \n+ ret = get_vcpu_events(cpu);\n+ if (ret < 0) {\n+ return ret;\n+ }\n+\n return 0;\n }\n \n@@ -1112,6 +1275,11 @@ int mshv_arch_store_vcpu_state(const CPUState *cpu)\n return ret;\n }\n \n+ ret = set_vcpu_events(cpu);\n+ if (ret < 0) {\n+ return ret;\n+ }\n+\n return 0;\n }\n \n", "prefixes": [ "29/34" ] }