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GET /api/1.2/patches/2224364/?format=api
{ "id": 2224364, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2224364/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260417104652.17857-11-xiaoou@iscas.ac.cn/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.2/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260417104652.17857-11-xiaoou@iscas.ac.cn>", "list_archive_url": null, "date": "2026-04-17T10:46:47", "name": "[10/14] target/riscv: rvp: add Q-format multiplication operations", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "fae61057d1709a891a64c9fa73317f69ea05d49d", "submitter": { "id": 89843, "url": "http://patchwork.ozlabs.org/api/1.2/people/89843/?format=api", "name": "Molly Chen", "email": "xiaoou@iscas.ac.cn" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260417104652.17857-11-xiaoou@iscas.ac.cn/mbox/", "series": [ { "id": 500307, "url": "http://patchwork.ozlabs.org/api/1.2/series/500307/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500307", "date": "2026-04-17T10:46:37", "name": "target/riscv: add support for RISC-V P extension (v0.20 draft)", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/500307/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2224364/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2224364/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)", "Received": [ "from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fxs7Y4MHYz1yCv\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 17 Apr 2026 20:48:57 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1wDgjW-0001Ft-RX; Fri, 17 Apr 2026 06:47:34 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <xiaoou@iscas.ac.cn>)\n id 1wDgjP-00017T-HB; Fri, 17 Apr 2026 06:47:28 -0400", "from smtp21.cstnet.cn ([159.226.251.21] helo=cstnet.cn)\n by eggs.gnu.org with esmtps (TLS1.2:DHE_RSA_AES_256_CBC_SHA1:256)\n (Exim 4.90_1) (envelope-from <xiaoou@iscas.ac.cn>)\n id 1wDgjL-0007zq-9r; Fri, 17 Apr 2026 06:47:27 -0400", "from Huawei.localdomain (unknown [36.110.52.2])\n by APP-01 (Coremail) with SMTP id qwCowAB3H2ulD+JpLDmSDQ--.804S12;\n Fri, 17 Apr 2026 18:47:19 +0800 (CST)" ], "From": "Molly Chen <xiaoou@iscas.ac.cn>", "To": "palmer@dabbelt.com, alistair.francis@wdc.com, liwei1518@gmail.com,\n daniel.barboza@oss.qualcomm.com, zhiwei_liu@linux.alibaba.com,\n chao.liu.zevorn@gmail.com", "Cc": "xiaoou@iscas.ac.cn,\n\tqemu-riscv@nongnu.org,\n\tqemu-devel@nongnu.org", "Subject": "[PATCH 10/14] target/riscv: rvp: add Q-format multiplication\n operations", "Date": "Fri, 17 Apr 2026 18:46:47 +0800", "Message-Id": "<20260417104652.17857-11-xiaoou@iscas.ac.cn>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20260417104652.17857-1-xiaoou@iscas.ac.cn>", "References": "<20260417104652.17857-1-xiaoou@iscas.ac.cn>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-CM-TRANSID": "qwCowAB3H2ulD+JpLDmSDQ--.804S12", "X-Coremail-Antispam": "1UD129KBjvAXoW3trW3Ar43XF43Aw17Kw1kAFb_yoW8Aw1rAo\n W3Gw1Yy395uw17ur409w4UX3WUXrZ2qw1DXw4UZr47Xa4xKrnrKF45J34kAFyxGrWayrW7\n WFZ3JF1rtFy3C3sxn29KB7ZKAUJUUUU8529EdanIXcx71UUUUU7v73VFW2AGmfu7bjvjm3\n AaLaJ3UjIYCTnIWjp_UUUOb7AC8VAFwI0_Wr0E3s1l1xkIjI8I6I8E6xAIw20EY4v20xva\n j40_Wr0E3s1l1IIY67AEw4v_Jr0_Jr4l82xGYIkIc2x26280x7IE14v26r126s0DM28Irc\n Ia0xkI8VCY1x0267AKxVW5JVCq3wA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK021l\n 84ACjcxK6xIIjxv20xvE14v26ryj6F1UM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26r4UJV\n WxJr1l84ACjcxK6I8E87Iv67AKxVW0oVCq3wA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_GcCE\n 3s1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E2I\n x0cI8IcVAFwI0_Jrv_JF1lYx0Ex4A2jsIE14v26r4j6F4UMcvjeVCFs4IE7xkEbVWUJVW8\n JwACjcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1lc7CjxVAaw2AFwI0_Jw\n 0_GFyl42xK82IYc2Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AK\n xVWUJVWUGwC20s026x8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r1q6r43MIIYrx\n kI7VAKI48JMIIF0xvE2Ix0cI8IcVAFwI0_Gr0_Xr1lIxAIcVC0I7IYx2IY6xkF7I0E14v2\n 6r4UJVWxJr1lIxAIcVCF04k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r4j6F\n 4UMIIF0xvEx4A2jsIEc7CjxVAFwI0_Gr1j6F4UJbIYCTnIWIevJa73UjIFyTuYvjfU5Tmh\n DUUUU", "X-Originating-IP": "[36.110.52.2]", "X-CM-SenderInfo": "50ld003x6l2u1dvotugofq/", "Received-SPF": "pass client-ip=159.226.251.21; envelope-from=xiaoou@iscas.ac.cn;\n helo=cstnet.cn", "X-Spam_score_int": "-21", "X-Spam_score": "-2.2", "X-Spam_bar": "--", "X-Spam_report": "(-2.2 / 5.0 requ) BAYES_00=-1.9, HK_RANDOM_ENVFROM=0.998,\n HK_RANDOM_FROM=0.998, RCVD_IN_DNSWL_MED=-2.3,\n RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001,\n SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Signed-off-by: Molly Chen <xiaoou@iscas.ac.cn>\n---\n target/riscv/helper.h | 28 ++\n target/riscv/insn32.decode | 43 +++\n target/riscv/insn_trans/trans_rvp.c.inc | 28 ++\n target/riscv/psimd_helper.c | 446 ++++++++++++++++++++++++\n 4 files changed, 545 insertions(+)", "diff": "diff --git a/target/riscv/helper.h b/target/riscv/helper.h\nindex 54f8591672..a5ecf9b7d7 100644\n--- a/target/riscv/helper.h\n+++ b/target/riscv/helper.h\n@@ -1661,3 +1661,31 @@ DEF_HELPER_4(maccsu_w11, i64, env, i64, i64, i64)\n DEF_HELPER_4(maccu_w00, i64, env, i64, i64, i64)\n DEF_HELPER_4(maccu_w01, i64, env, i64, i64, i64)\n DEF_HELPER_4(maccu_w11, i64, env, i64, i64, i64)\n+\n+/* Packed SIMD - Q-Format Multiplication Operations */\n+DEF_HELPER_3(pmulq_h, tl, env, tl, tl)\n+DEF_HELPER_3(pmulqr_h, tl, env, tl, tl)\n+DEF_HELPER_3(pmulq_w, i64, env, i64, i64)\n+DEF_HELPER_3(pmulqr_w, i64, env, i64, i64)\n+DEF_HELPER_3(mulq, i32, env, i32, i32)\n+DEF_HELPER_3(mulqr, i32, env, i32, i32)\n+\n+/* Packed SIMD - Q-Format Multiply-Accumulate Operations */\n+DEF_HELPER_4(mqacc_h00, i32, env, i32, i32, i32)\n+DEF_HELPER_4(mqacc_h01, i32, env, i32, i32, i32)\n+DEF_HELPER_4(mqacc_h11, i32, env, i32, i32, i32)\n+DEF_HELPER_4(mqracc_h00, i32, env, i32, i32, i32)\n+DEF_HELPER_4(mqracc_h01, i32, env, i32, i32, i32)\n+DEF_HELPER_4(mqracc_h11, i32, env, i32, i32, i32)\n+DEF_HELPER_4(mqacc_w00, i64, env, i64, i64, i64)\n+DEF_HELPER_4(mqacc_w01, i64, env, i64, i64, i64)\n+DEF_HELPER_4(mqacc_w11, i64, env, i64, i64, i64)\n+DEF_HELPER_4(mqracc_w00, i64, env, i64, i64, i64)\n+DEF_HELPER_4(mqracc_w01, i64, env, i64, i64, i64)\n+DEF_HELPER_4(mqracc_w11, i64, env, i64, i64, i64)\n+DEF_HELPER_4(pmqacc_w_h00, i64, env, i64, i64, i64)\n+DEF_HELPER_4(pmqacc_w_h01, i64, env, i64, i64, i64)\n+DEF_HELPER_4(pmqacc_w_h11, i64, env, i64, i64, i64)\n+DEF_HELPER_4(pmqracc_w_h00, i64, env, i64, i64, i64)\n+DEF_HELPER_4(pmqracc_w_h01, i64, env, i64, i64, i64)\n+DEF_HELPER_4(pmqracc_w_h11, i64, env, i64, i64, i64)\ndiff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode\nindex 9944d0b52c..b2a89e3a1f 100644\n--- a/target/riscv/insn32.decode\n+++ b/target/riscv/insn32.decode\n@@ -1505,3 +1505,46 @@ maccsu_w11 11111 11 ..... ..... 011 ..... 0111011 @r\n maccu_w00 10101 11 ..... ..... 011 ..... 0111011 @r\n maccu_w01 10111 11 ..... ..... 001 ..... 0111011 @r\n maccu_w11 10111 11 ..... ..... 011 ..... 0111011 @r\n+\n+# Packed SIMD - Q-Format Multiplication Operations\n+pmulq_h 11010 00 ..... ..... 111 ..... 0111011 @r\n+pmulqr_h 11010 10 ..... ..... 111 ..... 0111011 @r\n+{\n+ mulq 11010 01 ..... ..... 111 ..... 0111011 @r\n+ pmulq_w 11010 01 ..... ..... 111 ..... 0111011 @r\n+}\n+{\n+ mulqr 11010 11 ..... ..... 111 ..... 0111011 @r\n+ pmulqr_w 11010 11 ..... ..... 111 ..... 0111011 @r\n+}\n+# Packed SIMD - Q-Format Multiply-Accumulate Operations\n+{\n+ mqacc_h00 11101 00 ..... ..... 111 ..... 0111011 @r\n+ pmqacc_w_h00 11101 00 ..... ..... 111 ..... 0111011 @r\n+}\n+{\n+ mqacc_h01 11111 00 ..... ..... 101 ..... 0111011 @r\n+ pmqacc_w_h01 11111 00 ..... ..... 101 ..... 0111011 @r\n+}\n+{\n+ mqacc_h11 11111 00 ..... ..... 111 ..... 0111011 @r\n+ pmqacc_w_h11 11111 00 ..... ..... 111 ..... 0111011 @r\n+}\n+{\n+ mqracc_h00 11101 10 ..... ..... 111 ..... 0111011 @r\n+ pmqracc_w_h00 11101 10 ..... ..... 111 ..... 0111011 @r\n+}\n+{\n+ mqracc_h01 11111 10 ..... ..... 101 ..... 0111011 @r\n+ pmqracc_w_h01 11111 10 ..... ..... 101 ..... 0111011 @r\n+}\n+{\n+ mqracc_h11 11111 10 ..... ..... 111 ..... 0111011 @r\n+ pmqracc_w_h11 11111 10 ..... ..... 111 ..... 0111011 @r\n+}\n+mqacc_w00 11101 01 ..... ..... 111 ..... 0111011 @r\n+mqacc_w01 11111 01 ..... ..... 101 ..... 0111011 @r\n+mqacc_w11 11111 01 ..... ..... 111 ..... 0111011 @r\n+mqracc_w00 11101 11 ..... ..... 111 ..... 0111011 @r\n+mqracc_w01 11111 11 ..... ..... 101 ..... 0111011 @r\n+mqracc_w11 11111 11 ..... ..... 111 ..... 0111011 @r\ndiff --git a/target/riscv/insn_trans/trans_rvp.c.inc b/target/riscv/insn_trans/trans_rvp.c.inc\nindex b3476c26ad..3310e23dce 100644\n--- a/target/riscv/insn_trans/trans_rvp.c.inc\n+++ b/target/riscv/insn_trans/trans_rvp.c.inc\n@@ -830,3 +830,31 @@ GEN_SIMD_TRANS_ACC_64(maccsu_w11)\n GEN_SIMD_TRANS_ACC_64(maccu_w00)\n GEN_SIMD_TRANS_ACC_64(maccu_w01)\n GEN_SIMD_TRANS_ACC_64(maccu_w11)\n+\n+/* Packed SIMD - Q-Format Multiplication Operations */\n+GEN_SIMD_TRANS(pmulq_h)\n+GEN_SIMD_TRANS(pmulqr_h)\n+GEN_SIMD_TRANS_64(pmulq_w)\n+GEN_SIMD_TRANS_64(pmulqr_w)\n+GEN_SIMD_TRANS_32(mulq)\n+GEN_SIMD_TRANS_32(mulqr)\n+\n+/* Packed SIMD - Q-Format Multiply-Accumulate Operations */\n+GEN_SIMD_TRANS_ACC_32(mqacc_h00)\n+GEN_SIMD_TRANS_ACC_32(mqacc_h01)\n+GEN_SIMD_TRANS_ACC_32(mqacc_h11)\n+GEN_SIMD_TRANS_ACC_32(mqracc_h00)\n+GEN_SIMD_TRANS_ACC_32(mqracc_h01)\n+GEN_SIMD_TRANS_ACC_32(mqracc_h11)\n+GEN_SIMD_TRANS_ACC_64(mqacc_w00)\n+GEN_SIMD_TRANS_ACC_64(mqacc_w01)\n+GEN_SIMD_TRANS_ACC_64(mqacc_w11)\n+GEN_SIMD_TRANS_ACC_64(mqracc_w00)\n+GEN_SIMD_TRANS_ACC_64(mqracc_w01)\n+GEN_SIMD_TRANS_ACC_64(mqracc_w11)\n+GEN_SIMD_TRANS_ACC_64(pmqacc_w_h00)\n+GEN_SIMD_TRANS_ACC_64(pmqacc_w_h01)\n+GEN_SIMD_TRANS_ACC_64(pmqacc_w_h11)\n+GEN_SIMD_TRANS_ACC_64(pmqracc_w_h00)\n+GEN_SIMD_TRANS_ACC_64(pmqracc_w_h01)\n+GEN_SIMD_TRANS_ACC_64(pmqracc_w_h11)\ndiff --git a/target/riscv/psimd_helper.c b/target/riscv/psimd_helper.c\nindex bddd24c997..d69a2f6453 100644\n--- a/target/riscv/psimd_helper.c\n+++ b/target/riscv/psimd_helper.c\n@@ -5628,3 +5628,449 @@ uint64_t HELPER(maccu_w11)(CPURISCVState *env, uint64_t rs1,\n uint64_t mul = (uint64_t)s1_w1 * (uint64_t)s2_w1;\n return d_w + mul;\n }\n+\n+/* Q-Format Multiplication Operations */\n+\n+/**\n+ * PMULQ.H - Packed signed Q-format multiply (fractional)\n+ */\n+target_ulong HELPER(pmulq_h)(CPURISCVState *env, target_ulong rs1,\n+ target_ulong rs2)\n+{\n+ target_ulong rd = 0;\n+ int elems = ELEMS_H(rd);\n+ int sat = 0;\n+\n+ for (int i = 0; i < elems; i++) {\n+ int16_t e1 = (int16_t)EXTRACT16(rs1, i);\n+ int16_t e2 = (int16_t)EXTRACT16(rs2, i);\n+ uint16_t result;\n+\n+ if ((e1 == -32768) && (e2 == -32768)) {\n+ sat = 1;\n+ result = 0x7FFF;\n+ } else {\n+ int32_t prod = (int32_t)e1 * (int32_t)e2;\n+ result = (prod >> 15) & 0xFFFF;\n+ }\n+ rd = INSERT16(rd, result, i);\n+ }\n+\n+ if (sat) {\n+ env->vxsat = 1;\n+ }\n+ return rd;\n+}\n+\n+/**\n+ * PMULQR.H - Packed signed Q-format multiply with rounding\n+ */\n+target_ulong HELPER(pmulqr_h)(CPURISCVState *env, target_ulong rs1,\n+ target_ulong rs2)\n+{\n+ target_ulong rd = 0;\n+ int elems = ELEMS_H(rd);\n+ int sat = 0;\n+\n+ for (int i = 0; i < elems; i++) {\n+ int16_t e1 = (int16_t)EXTRACT16(rs1, i);\n+ int16_t e2 = (int16_t)EXTRACT16(rs2, i);\n+ uint16_t result;\n+\n+ if ((e1 == -32768) && (e2 == -32768)) {\n+ sat = 1;\n+ result = 0x7FFF;\n+ } else {\n+ int32_t prod = (int32_t)e1 * (int32_t)e2 + (1 << 14);\n+ result = (prod >> 15) & 0xFFFF;\n+ }\n+ rd = INSERT16(rd, result, i);\n+ }\n+\n+ if (sat) {\n+ env->vxsat = 1;\n+ }\n+ return rd;\n+}\n+\n+/**\n+ * PMULQ.W - Packed signed 32-bit Q-format multiply (RV64 only)\n+ */\n+uint64_t HELPER(pmulq_w)(CPURISCVState *env, uint64_t rs1, uint64_t rs2)\n+{\n+ uint64_t rd = 0;\n+ int elems = 2;\n+ int sat = 0;\n+\n+ for (int i = 0; i < elems; i++) {\n+ int32_t e1 = (int32_t)EXTRACT32(rs1, i);\n+ int32_t e2 = (int32_t)EXTRACT32(rs2, i);\n+ uint32_t result;\n+\n+ if ((e1 == -2147483647 - 1) && (e2 == -2147483647 - 1)) {\n+ sat = 1;\n+ result = 0x7FFFFFFF;\n+ } else {\n+ int64_t prod = (int64_t)e1 * (int64_t)e2;\n+ result = (uint32_t)(prod >> 31);\n+ }\n+ rd = INSERT32(rd, result, i);\n+ }\n+\n+ if (sat) {\n+ env->vxsat = 1;\n+ }\n+ return rd;\n+}\n+\n+/**\n+ * PMULQR.W - Packed signed 32-bit Q-format multiply with rounding (RV64 only)\n+ */\n+uint64_t HELPER(pmulqr_w)(CPURISCVState *env, uint64_t rs1, uint64_t rs2)\n+{\n+ uint64_t rd = 0;\n+ int elems = 2;\n+ int sat = 0;\n+\n+ for (int i = 0; i < elems; i++) {\n+ int32_t e1 = (int32_t)EXTRACT32(rs1, i);\n+ int32_t e2 = (int32_t)EXTRACT32(rs2, i);\n+ uint32_t result;\n+\n+ if ((e1 == -2147483647 - 1) && (e2 == -2147483647 - 1)) {\n+ sat = 1;\n+ result = 0x7FFFFFFF;\n+ } else {\n+ int64_t prod = (int64_t)e1 * (int64_t)e2 + (1LL << 30);\n+ result = (uint32_t)(prod >> 31);\n+ }\n+ rd = INSERT32(rd, result, i);\n+ }\n+\n+ if (sat) {\n+ env->vxsat = 1;\n+ }\n+ return rd;\n+}\n+\n+/**\n+ * MULQ - 32-bit signed Q-format multiply\n+ */\n+uint32_t HELPER(mulq)(CPURISCVState *env, uint32_t rs1, uint32_t rs2)\n+{\n+ int32_t a = (int32_t)rs1;\n+ int32_t b = (int32_t)rs2;\n+\n+ if ((a == -2147483647 - 1) && (b == -2147483647 - 1)) {\n+ env->vxsat = 1;\n+ return 0x7FFFFFFF;\n+ } else {\n+ int64_t prod = (int64_t)a * (int64_t)b;\n+ return (uint32_t)(prod >> 31);\n+ }\n+}\n+\n+/**\n+ * MULQR - 32-bit signed Q-format multiply with rounding\n+ */\n+uint32_t HELPER(mulqr)(CPURISCVState *env, uint32_t rs1, uint32_t rs2)\n+{\n+ int32_t a = (int32_t)rs1;\n+ int32_t b = (int32_t)rs2;\n+\n+ if ((a == -2147483647 - 1) && (b == -2147483647 - 1)) {\n+ env->vxsat = 1;\n+ return 0x7FFFFFFF;\n+ } else {\n+ int64_t prod = (int64_t)a * (int64_t)b + (1LL << 30);\n+ return (uint32_t)(prod >> 31);\n+ }\n+}\n+\n+\n+/* Q-Format Multiply-Accumulate Operations */\n+\n+/**\n+ * MQACC.H00 - Q-format multiply accumulate, both operands low halfword\n+ */\n+uint32_t HELPER(mqacc_h00)(CPURISCVState *env, uint32_t rs1,\n+ uint32_t rs2, uint32_t dest)\n+{\n+ int16_t s1_h0 = (int16_t)(rs1 & 0xFFFF);\n+ int16_t s2_h0 = (int16_t)(rs2 & 0xFFFF);\n+ int32_t d = (int32_t)dest;\n+ int64_t prod = (int64_t)s1_h0 * (int64_t)s2_h0;\n+ return (uint32_t)(d + (int32_t)(prod >> 15));\n+}\n+\n+/**\n+ * MQACC.H01 - Q-format multiply accumulate, rs1 low, rs2 high\n+ */\n+uint32_t HELPER(mqacc_h01)(CPURISCVState *env, uint32_t rs1,\n+ uint32_t rs2, uint32_t dest)\n+{\n+ int16_t s1_h0 = (int16_t)(rs1 & 0xFFFF);\n+ int16_t s2_h1 = (int16_t)((rs2 >> 16) & 0xFFFF);\n+ int32_t d = (int32_t)dest;\n+ int64_t prod = (int64_t)s1_h0 * (int64_t)s2_h1;\n+ return (uint32_t)(d + (int32_t)(prod >> 15));\n+}\n+\n+/**\n+ * MQACC.H11 - Q-format multiply accumulate, both operands high halfword\n+ */\n+uint32_t HELPER(mqacc_h11)(CPURISCVState *env, uint32_t rs1,\n+ uint32_t rs2, uint32_t dest)\n+{\n+ int16_t s1_h1 = (int16_t)((rs1 >> 16) & 0xFFFF);\n+ int16_t s2_h1 = (int16_t)((rs2 >> 16) & 0xFFFF);\n+ int32_t d = (int32_t)dest;\n+ int64_t prod = (int64_t)s1_h1 * (int64_t)s2_h1;\n+ return (uint32_t)(d + (int32_t)(prod >> 15));\n+}\n+\n+/**\n+ * MQRACC.H00 - Q-format multiply accumulate with rounding, both low halfword\n+ */\n+uint32_t HELPER(mqracc_h00)(CPURISCVState *env, uint32_t rs1,\n+ uint32_t rs2, uint32_t dest)\n+{\n+ int16_t s1_h0 = (int16_t)(rs1 & 0xFFFF);\n+ int16_t s2_h0 = (int16_t)(rs2 & 0xFFFF);\n+ int32_t d = (int32_t)dest;\n+ int64_t prod = (int64_t)s1_h0 * (int64_t)s2_h0 + (1LL << 14);\n+ return (uint32_t)(d + (int32_t)(prod >> 15));\n+}\n+\n+/**\n+ * MQRACC.H01 - Q-format multiply accumulate with rounding, rs1 low, rs2 high\n+ */\n+uint32_t HELPER(mqracc_h01)(CPURISCVState *env, uint32_t rs1,\n+ uint32_t rs2, uint32_t dest)\n+{\n+ int16_t s1_h0 = (int16_t)(rs1 & 0xFFFF);\n+ int16_t s2_h1 = (int16_t)((rs2 >> 16) & 0xFFFF);\n+ int32_t d = (int32_t)dest;\n+ int64_t prod = (int64_t)s1_h0 * (int64_t)s2_h1 + (1LL << 14);\n+ return (uint32_t)(d + (int32_t)(prod >> 15));\n+}\n+\n+/**\n+ * MQRACC.H11 - Q-format multiply accumulate with rounding, both high halfword\n+ */\n+uint32_t HELPER(mqracc_h11)(CPURISCVState *env, uint32_t rs1,\n+ uint32_t rs2, uint32_t dest)\n+{\n+ int16_t s1_h1 = (int16_t)((rs1 >> 16) & 0xFFFF);\n+ int16_t s2_h1 = (int16_t)((rs2 >> 16) & 0xFFFF);\n+ int32_t d = (int32_t)dest;\n+ int64_t prod = (int64_t)s1_h1 * (int64_t)s2_h1 + (1LL << 14);\n+ return (uint32_t)(d + (int32_t)(prod >> 15));\n+}\n+\n+/**\n+ * MQACC.W00 - Q-format multiply accumulate, both low word (RV64)\n+ */\n+uint64_t HELPER(mqacc_w00)(CPURISCVState *env, uint64_t rs1,\n+ uint64_t rs2, uint64_t dest)\n+{\n+ int32_t s1_w0 = (int32_t)(rs1 & 0xFFFFFFFF);\n+ int32_t s2_w0 = (int32_t)(rs2 & 0xFFFFFFFF);\n+ int64_t d = (int64_t)dest;\n+ int64_t prod = (int64_t)s1_w0 * (int64_t)s2_w0;\n+ __int128_t prod_95 = ((__int128_t)prod) >> 31;\n+ return (uint64_t)(d + (int64_t)prod_95);\n+}\n+\n+/**\n+ * MQACC.W01 - Q-format multiply accumulate, rs1 low, rs2 high (RV64)\n+ */\n+uint64_t HELPER(mqacc_w01)(CPURISCVState *env, uint64_t rs1,\n+ uint64_t rs2, uint64_t dest)\n+{\n+ int32_t s1_w0 = (int32_t)(rs1 & 0xFFFFFFFF);\n+ int32_t s2_w1 = (int32_t)((rs2 >> 32) & 0xFFFFFFFF);\n+ int64_t d = (int64_t)dest;\n+ int64_t prod = (int64_t)s1_w0 * (int64_t)s2_w1;\n+ __int128_t prod_95 = ((__int128_t)prod) >> 31;\n+ return (uint64_t)(d + (int64_t)prod_95);\n+}\n+\n+/**\n+ * MQACC.W11 - Q-format multiply accumulate, both high word (RV64)\n+ */\n+uint64_t HELPER(mqacc_w11)(CPURISCVState *env, uint64_t rs1,\n+ uint64_t rs2, uint64_t dest)\n+{\n+ int32_t s1_w1 = (int32_t)((rs1 >> 32) & 0xFFFFFFFF);\n+ int32_t s2_w1 = (int32_t)((rs2 >> 32) & 0xFFFFFFFF);\n+ int64_t d = (int64_t)dest;\n+ int64_t prod = (int64_t)s1_w1 * (int64_t)s2_w1;\n+ __int128_t prod_95 = ((__int128_t)prod) >> 31;\n+ return (uint64_t)(d + (int64_t)prod_95);\n+}\n+\n+/**\n+ * MQRACC.W00 - Q-format multiply accumulate with rounding,\n+ * both low word (RV64)\n+ */\n+uint64_t HELPER(mqracc_w00)(CPURISCVState *env, uint64_t rs1,\n+ uint64_t rs2, uint64_t dest)\n+{\n+ int32_t s1_w0 = (int32_t)(rs1 & 0xFFFFFFFF);\n+ int32_t s2_w0 = (int32_t)(rs2 & 0xFFFFFFFF);\n+ int64_t d = (int64_t)dest;\n+ int64_t prod = (int64_t)s1_w0 * (int64_t)s2_w0 + (1LL << 30);\n+ __int128_t prod_95 = ((__int128_t)prod) >> 31;\n+ return (uint64_t)(d + (int64_t)prod_95);\n+}\n+\n+/**\n+ * MQRACC.W01 - Q-format multiply accumulate with rounding,\n+ * rs1 low, rs2 high (RV64)\n+ */\n+uint64_t HELPER(mqracc_w01)(CPURISCVState *env, uint64_t rs1,\n+ uint64_t rs2, uint64_t dest)\n+{\n+ int32_t s1_w0 = (int32_t)(rs1 & 0xFFFFFFFF);\n+ int32_t s2_w1 = (int32_t)((rs2 >> 32) & 0xFFFFFFFF);\n+ int64_t d = (int64_t)dest;\n+ int64_t prod = (int64_t)s1_w0 * (int64_t)s2_w1 + (1LL << 30);\n+ __int128_t prod_95 = ((__int128_t)prod) >> 31;\n+ return (uint64_t)(d + (int64_t)prod_95);\n+}\n+\n+/**\n+ * MQRACC.W11 - Q-format multiply accumulate with rounding,\n+ * both high word (RV64)\n+ */\n+uint64_t HELPER(mqracc_w11)(CPURISCVState *env, uint64_t rs1,\n+ uint64_t rs2, uint64_t dest)\n+{\n+ int32_t s1_w1 = (int32_t)((rs1 >> 32) & 0xFFFFFFFF);\n+ int32_t s2_w1 = (int32_t)((rs2 >> 32) & 0xFFFFFFFF);\n+ int64_t d = (int64_t)dest;\n+ int64_t prod = (int64_t)s1_w1 * (int64_t)s2_w1 + (1LL << 30);\n+ __int128_t prod_95 = ((__int128_t)prod) >> 31;\n+ return (uint64_t)(d + (int64_t)prod_95);\n+}\n+\n+/**\n+ * PMQACC.W.H00 - Packed Q-format multiply accumulate,\n+ * low halfword (RV64)\n+ */\n+uint64_t HELPER(pmqacc_w_h00)(CPURISCVState *env, uint64_t rs1,\n+ uint64_t rs2, uint64_t dest)\n+{\n+ uint64_t rd = 0;\n+\n+ for (int i = 0; i < 2; i++) {\n+ int16_t s1_h0 = (int16_t)EXTRACT16(rs1, i * 2);\n+ int16_t s2_h0 = (int16_t)EXTRACT16(rs2, i * 2);\n+ int32_t d_w = (int32_t)EXTRACT32(dest, i);\n+ int64_t prod = (int64_t)s1_h0 * (int64_t)s2_h0;\n+ uint32_t res = (uint32_t)(d_w + (int32_t)(prod >> 15));\n+ rd = INSERT32(rd, res, i);\n+ }\n+ return rd;\n+}\n+\n+/**\n+ * PMQACC.W.H01 - Packed Q-format multiply accumulate,\n+ * rs1 low, rs2 high (RV64)\n+ */\n+uint64_t HELPER(pmqacc_w_h01)(CPURISCVState *env, uint64_t rs1,\n+ uint64_t rs2, uint64_t dest)\n+{\n+ uint64_t rd = 0;\n+\n+ for (int i = 0; i < 2; i++) {\n+ int16_t s1_h0 = (int16_t)EXTRACT16(rs1, i * 2);\n+ int16_t s2_h1 = (int16_t)EXTRACT16(rs2, i * 2 + 1);\n+ int32_t d_w = (int32_t)EXTRACT32(dest, i);\n+ int64_t prod = (int64_t)s1_h0 * (int64_t)s2_h1;\n+ uint32_t res = (uint32_t)(d_w + (int32_t)(prod >> 15));\n+ rd = INSERT32(rd, res, i);\n+ }\n+ return rd;\n+}\n+\n+/**\n+ * PMQACC.W.H11 - Packed Q-format multiply accumulate,\n+ * both high halfword (RV64)\n+ */\n+uint64_t HELPER(pmqacc_w_h11)(CPURISCVState *env, uint64_t rs1,\n+ uint64_t rs2, uint64_t dest)\n+{\n+ uint64_t rd = 0;\n+\n+ for (int i = 0; i < 2; i++) {\n+ int16_t s1_h1 = (int16_t)EXTRACT16(rs1, i * 2 + 1);\n+ int16_t s2_h1 = (int16_t)EXTRACT16(rs2, i * 2 + 1);\n+ int32_t d_w = (int32_t)EXTRACT32(dest, i);\n+ int64_t prod = (int64_t)s1_h1 * (int64_t)s2_h1;\n+ uint32_t res = (uint32_t)(d_w + (int32_t)(prod >> 15));\n+ rd = INSERT32(rd, res, i);\n+ }\n+ return rd;\n+}\n+\n+/**\n+ * PMQRACC.W.H00 - Packed Q-format multiply accumulate\n+ * with rounding, low halfword (RV64)\n+ */\n+uint64_t HELPER(pmqracc_w_h00)(CPURISCVState *env, uint64_t rs1,\n+ uint64_t rs2, uint64_t dest)\n+{\n+ uint64_t rd = 0;\n+\n+ for (int i = 0; i < 2; i++) {\n+ int16_t s1_h0 = (int16_t)EXTRACT16(rs1, i * 2);\n+ int16_t s2_h0 = (int16_t)EXTRACT16(rs2, i * 2);\n+ int32_t d_w = (int32_t)EXTRACT32(dest, i);\n+ int64_t prod = (int64_t)s1_h0 * (int64_t)s2_h0 + (1LL << 14);\n+ uint32_t res = (uint32_t)(d_w + (int32_t)(prod >> 15));\n+ rd = INSERT32(rd, res, i);\n+ }\n+ return rd;\n+}\n+\n+/**\n+ * PMQRACC.W.H01 - Packed Q-format multiply accumulate\n+ * with rounding, rs1 low, rs2 high (RV64)\n+ */\n+uint64_t HELPER(pmqracc_w_h01)(CPURISCVState *env, uint64_t rs1,\n+ uint64_t rs2, uint64_t dest)\n+{\n+ uint64_t rd = 0;\n+\n+ for (int i = 0; i < 2; i++) {\n+ int16_t s1_h0 = (int16_t)EXTRACT16(rs1, i * 2);\n+ int16_t s2_h1 = (int16_t)EXTRACT16(rs2, i * 2 + 1);\n+ int32_t d_w = (int32_t)EXTRACT32(dest, i);\n+ int64_t prod = (int64_t)s1_h0 * (int64_t)s2_h1 + (1LL << 14);\n+ uint32_t res = (uint32_t)(d_w + (int32_t)(prod >> 15));\n+ rd = INSERT32(rd, res, i);\n+ }\n+ return rd;\n+}\n+\n+/**\n+ * PMQRACC.W.H11 - Packed Q-format multiply accumulate\n+ * with rounding, both high halfword (RV64)\n+ */\n+uint64_t HELPER(pmqracc_w_h11)(CPURISCVState *env, uint64_t rs1,\n+ uint64_t rs2, uint64_t dest)\n+{\n+ uint64_t rd = 0;\n+\n+ for (int i = 0; i < 2; i++) {\n+ int16_t s1_h1 = (int16_t)EXTRACT16(rs1, i * 2 + 1);\n+ int16_t s2_h1 = (int16_t)EXTRACT16(rs2, i * 2 + 1);\n+ int32_t d_w = (int32_t)EXTRACT32(dest, i);\n+ int64_t prod = (int64_t)s1_h1 * (int64_t)s2_h1 + (1LL << 14);\n+ uint32_t res = (uint32_t)(d_w + (int32_t)(prod >> 15));\n+ rd = INSERT32(rd, res, i);\n+ }\n+ return rd;\n+}\n", "prefixes": [ "10/14" ] }