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GET /api/1.2/patches/2224362/?format=api
{ "id": 2224362, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2224362/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260417104652.17857-13-xiaoou@iscas.ac.cn/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.2/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260417104652.17857-13-xiaoou@iscas.ac.cn>", "list_archive_url": null, "date": "2026-04-17T10:46:49", "name": "[12/14] target/riscv: rvp: add load and replicate instructions.", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "d56c6a64b1f7fc8a839a142dbc4f67dfc5f4a44b", "submitter": { "id": 89843, "url": "http://patchwork.ozlabs.org/api/1.2/people/89843/?format=api", "name": "Molly Chen", "email": "xiaoou@iscas.ac.cn" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260417104652.17857-13-xiaoou@iscas.ac.cn/mbox/", "series": [ { "id": 500307, "url": "http://patchwork.ozlabs.org/api/1.2/series/500307/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500307", "date": "2026-04-17T10:46:37", "name": "target/riscv: add support for RISC-V P extension (v0.20 draft)", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/500307/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2224362/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2224362/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)", "Received": [ "from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fxs7F4zyVz1yCv\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 17 Apr 2026 20:48:41 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1wDgjm-0001P9-A8; Fri, 17 Apr 2026 06:47:50 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <xiaoou@iscas.ac.cn>)\n id 1wDgjk-0001OZ-4O; Fri, 17 Apr 2026 06:47:48 -0400", "from smtp21.cstnet.cn ([159.226.251.21] helo=cstnet.cn)\n by eggs.gnu.org with esmtps (TLS1.2:DHE_RSA_AES_256_CBC_SHA1:256)\n (Exim 4.90_1) (envelope-from <xiaoou@iscas.ac.cn>)\n id 1wDgjh-000827-W2; Fri, 17 Apr 2026 06:47:47 -0400", "from Huawei.localdomain (unknown [36.110.52.2])\n by APP-01 (Coremail) with SMTP id qwCowAB3H2ulD+JpLDmSDQ--.804S14;\n Fri, 17 Apr 2026 18:47:22 +0800 (CST)" ], "From": "Molly Chen <xiaoou@iscas.ac.cn>", "To": "palmer@dabbelt.com, alistair.francis@wdc.com, liwei1518@gmail.com,\n daniel.barboza@oss.qualcomm.com, zhiwei_liu@linux.alibaba.com,\n chao.liu.zevorn@gmail.com", "Cc": "xiaoou@iscas.ac.cn,\n\tqemu-riscv@nongnu.org,\n\tqemu-devel@nongnu.org", "Subject": "[PATCH 12/14] target/riscv: rvp: add load and replicate instructions.", "Date": "Fri, 17 Apr 2026 18:46:49 +0800", "Message-Id": "<20260417104652.17857-13-xiaoou@iscas.ac.cn>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20260417104652.17857-1-xiaoou@iscas.ac.cn>", "References": "<20260417104652.17857-1-xiaoou@iscas.ac.cn>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-CM-TRANSID": "qwCowAB3H2ulD+JpLDmSDQ--.804S14", "X-Coremail-Antispam": "1UD129KBjvJXoWxXry3Kr4xuF1DXrWDKw18Grg_yoWrAr4fpF\n 48Gr17GrWkGr13AF93Kr45Jr13Wrs5G34UG3sxW3Z7AF45JFWrA348Kw43tr4FqryDWFWU\n GF1UAryDuFZ5JwUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2\n 9KBjDU0xBIdaVrnRJUUUPY14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0\n rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_JF0E3s1l82xGYI\n kIc2x26xkF7I0E14v26ryj6s0DM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2\n z4x0Y4vE2Ix0cI8IcVAFwI0_Xr0_Ar1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Gr1j6F\n 4UJwA2z4x0Y4vEx4A2jsIE14v26rxl6s0DM28EF7xvwVC2z280aVCY1x0267AKxVW0oVCq\n 3wAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0I7\n IYx2IY67AKxVWUXVWUAwAv7VC2z280aVAFwI0_Gr0_Cr1lOx8S6xCaFVCjc4AY6r1j6r4U\n M4x0Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwCY1x0262kKe7AKxVWUtV\n W8ZwCF04k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14v2\n 6r1j6r18MI8I3I0E7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_Jw0_GFylIxkGc2\n Ij64vIr41lIxAIcVC0I7IYx2IY67AKxVW8JVW5JwCI42IY6xIIjxv20xvEc7CjxVAFwI0_\n Gr1j6F4UJwCI42IY6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Gr0_Cr\n 1lIxAIcVC2z280aVCY1x0267AKxVW8Jr0_Cr1UYxBIdaVFxhVjvjDU0xZFpf9x0JUqLvNU\n UUUU=", "X-Originating-IP": "[36.110.52.2]", "X-CM-SenderInfo": "50ld003x6l2u1dvotugofq/", "Received-SPF": "pass client-ip=159.226.251.21; envelope-from=xiaoou@iscas.ac.cn;\n helo=cstnet.cn", "X-Spam_score_int": "-21", "X-Spam_score": "-2.2", "X-Spam_bar": "--", "X-Spam_report": "(-2.2 / 5.0 requ) BAYES_00=-1.9, HK_RANDOM_ENVFROM=0.998,\n HK_RANDOM_FROM=0.998, RCVD_IN_DNSWL_MED=-2.3,\n RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001,\n SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Signed-off-by: Molly Chen <xiaoou@iscas.ac.cn>\n---\n target/riscv/insn32.decode | 16 ++++++\n target/riscv/insn_trans/trans_rvp.c.inc | 67 +++++++++++++++++++++++++\n target/riscv/translate.c | 2 +\n 3 files changed, 85 insertions(+)", "diff": "diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode\nindex ebfbf8c799..b1bde37de4 100644\n--- a/target/riscv/insn32.decode\n+++ b/target/riscv/insn32.decode\n@@ -44,6 +44,10 @@\n %imm_p_ui16 20:4\n %imm_p_ui32 20:5\n %imm_p_ui64 20:6\n+%imm_p_l1 16:8\n+%imm_p_l2 15:s1 16:9\n+%imm_p_l3 15:s9 24:1 !function=ex_shift_6\n+%imm_p_l4 15:s9 24:1 !function=ex_shift_22\n \n # Argument sets:\n &empty\n@@ -64,6 +68,7 @@\n &k_aes shamt rs2 rs1 rd\n &mop5 imm rd rs1\n &mop3 imm rd rs1 rs2\n+&p_l imm rd\n \n # Formats 32:\n @r ....... ..... ..... ... ..... ....... &r %rs2 %rs1 %rd\n@@ -113,6 +118,10 @@\n @p_ui16 ..... .... ... ..... ... ..... ....... &i imm=%imm_p_ui16 %rs1 %rd\n @p_ui32 ..... .... ... ..... ... ..... ....... &i imm=%imm_p_ui32 %rs1 %rd\n @p_ui64 ..... .... ... ..... ... ..... ....... &i imm=%imm_p_ui64 %rs1 %rd\n+@p_l1 ........ ........ .... ..... ....... &p_l imm=%imm_p_l1 %rd\n+@p_l2 ....... .......... ... ..... ....... &p_l imm=%imm_p_l2 %rd\n+@p_l3 ....... .......... ... ..... ....... &p_l imm=%imm_p_l3 %rd\n+@p_l4 ....... .......... ... ..... ....... &p_l imm=%imm_p_l4 %rd\n \n # Formats 64:\n @sh5 ....... ..... ..... ... ..... ....... &shift shamt=%sh5 %rs1 %rd\n@@ -1596,3 +1605,10 @@ pm4addu_h 10100 11 ..... ..... 101 ..... 0111011 @r\n pm4adda_h 10001 11 ..... ..... 101 ..... 0111011 @r\n pm4addasu_h 11101 11 ..... ..... 101 ..... 0111011 @r\n pm4addau_h 10101 11 ..... ..... 101 ..... 0111011 @r\n+\n+# Packed SIMD - Load and Replicate instructions\n+pli_b 10110100 ........ 0010 ..... 0011011 @p_l1\n+pli_h 1011000 .......... 010 ..... 0011011 @p_l2\n+plui_h 1111000 .......... 010 ..... 0011011 @p_l3\n+pli_w 1011001 ..... ..... 010 ..... 0011011 @p_l2\n+plui_w 1111001 ..... ..... 010 ..... 0011011 @p_l4\ndiff --git a/target/riscv/insn_trans/trans_rvp.c.inc b/target/riscv/insn_trans/trans_rvp.c.inc\nindex 86071d71f7..b82774e00f 100644\n--- a/target/riscv/insn_trans/trans_rvp.c.inc\n+++ b/target/riscv/insn_trans/trans_rvp.c.inc\n@@ -906,3 +906,70 @@ GEN_SIMD_TRANS_64(pm4addu_h)\n GEN_SIMD_TRANS_ACC_64(pm4adda_h)\n GEN_SIMD_TRANS_ACC_64(pm4addasu_h)\n GEN_SIMD_TRANS_ACC_64(pm4addau_h)\n+\n+static bool trans_pli_b(DisasContext *ctx, arg_pli_b * a)\n+{\n+ REQUIRE_EXT(ctx, RVP);\n+ int i = 1;\n+ target_long imm = a->imm;\n+ while (i < TARGET_LONG_SIZE) {\n+ imm = ((imm << 8) + a->imm);\n+ i++;\n+ }\n+ gen_set_gpri(ctx, a->rd, imm);\n+ return true;\n+}\n+\n+static bool trans_pli_h(DisasContext *ctx, arg_pli_h * a)\n+{\n+ REQUIRE_EXT(ctx, RVP);\n+ int i = 1;\n+ target_long imm = a->imm;\n+ while (i < TARGET_LONG_SIZE / 2) {\n+ imm = (imm << 16) + (a->imm & 0xFFFF);\n+ i++;\n+ }\n+ gen_set_gpri(ctx, a->rd, imm);\n+ return true;\n+}\n+\n+static bool trans_plui_h(DisasContext *ctx, arg_plui_h * a)\n+{\n+ REQUIRE_EXT(ctx, RVP);\n+ int i = 1;\n+ target_long imm = a->imm;\n+ while (i < TARGET_LONG_SIZE / 2) {\n+ imm = (imm << 16) + (a->imm & 0xFFFF);\n+ i++;\n+ }\n+ gen_set_gpri(ctx, a->rd, imm);\n+ return true;\n+}\n+\n+static bool trans_pli_w(DisasContext *ctx, arg_pli_w * a)\n+{\n+ REQUIRE_64BIT(ctx);\n+ REQUIRE_EXT(ctx, RVP);\n+ int i = 1;\n+ int64_t imm = a->imm;\n+ while (i < TARGET_LONG_SIZE / 4) {\n+ imm = (imm << 32) + (a->imm & 0xFFFFFFFF);\n+ i++;\n+ }\n+ gen_set_gpri(ctx, a->rd, imm);\n+ return true;\n+}\n+\n+static bool trans_plui_w(DisasContext *ctx, arg_plui_w * a)\n+{\n+ REQUIRE_64BIT(ctx);\n+ REQUIRE_EXT(ctx, RVP);\n+ int i = 1;\n+ int64_t imm = a->imm;\n+ while (i < TARGET_LONG_SIZE / 4) {\n+ imm = (imm << 32) + (a->imm & 0xFFFFFFFF);\n+ i++;\n+ }\n+ gen_set_gpri(ctx, a->rd, imm);\n+ return true;\n+}\ndiff --git a/target/riscv/translate.c b/target/riscv/translate.c\nindex de3ec7a7ec..04efc7aced 100644\n--- a/target/riscv/translate.c\n+++ b/target/riscv/translate.c\n@@ -796,7 +796,9 @@ EX_SH(1)\n EX_SH(2)\n EX_SH(3)\n EX_SH(4)\n+EX_SH(6)\n EX_SH(12)\n+EX_SH(22)\n \n #define REQUIRE_EXT(ctx, ext) do { \\\n if (!has_ext(ctx, ext)) { \\\n", "prefixes": [ "12/14" ] }