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GET /api/1.2/patches/2224356/?format=api
{ "id": 2224356, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2224356/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260417104223.3457417-1-mnissler@meta.com/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/1.2/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260417104223.3457417-1-mnissler@meta.com>", "list_archive_url": null, "date": "2026-04-17T10:42:23", "name": "[pciutils,v3] ls-ecaps: Decode DPC RP PIO registers", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "99f175e10694ab3c703fb45e50c484eed32bbaf7", "submitter": { "id": 93169, "url": "http://patchwork.ozlabs.org/api/1.2/people/93169/?format=api", "name": "Mattias Nissler", "email": "mnissler@meta.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260417104223.3457417-1-mnissler@meta.com/mbox/", "series": [ { "id": 500306, "url": "http://patchwork.ozlabs.org/api/1.2/series/500306/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=500306", "date": "2026-04-17T10:42:23", "name": "[pciutils,v3] ls-ecaps: Decode DPC RP PIO registers", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/500306/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2224356/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2224356/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-pci+bounces-52714-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ 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t=1776422570; c=relaxed/simple;\n\tbh=2cc+r2hddQckl/uVRskHI9l5+gwu1N0Bf10ZnuI9OiA=;\n\th=From:To:CC:Subject:Date:Message-ID:MIME-Version:Content-Type;\n b=GQYr4RkjptbfH0CbY65zq5XnHRRZav92lpSrCeI7Ha9m1cg3mVkAR2h21dLp4qV78obp5wiCOpYnQwc2zdYXFHN9BXa4z5hjmMHd26eo59Id/t1/ukZqF1cpPkg78DCL4LOyT3uzh6hk6SvntwLxJJp7Q0JJRQh5dmzywzXT3QE=", "ARC-Authentication-Results": "i=1; smtp.subspace.kernel.org;\n dmarc=pass (p=reject dis=none) header.from=meta.com;\n spf=pass smtp.mailfrom=meta.com;\n dkim=pass (2048-bit key) header.d=meta.com header.i=@meta.com\n header.b=PfW1whYx; arc=none smtp.client-ip=67.231.145.42", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=meta.com; h=cc\n\t:content-transfer-encoding:content-type:date:from:message-id\n\t:mime-version:subject:to; s=s2048-2025-q2; bh=HIqbeMpWSuPf7AOTcK\n\tpb7D9mzI+uoGPibb81KOOCl0M=; b=PfW1whYxMPzHBnFowmukgxox5bwEg8t+t6\n\tr5SA+l7dcMFuW3yJjbtNZxtrhc1TXvHydYnneVkNMwDapN4tVOPrlS2L3XsJ+cHJ\n\t5D5tys3T2l/HbDbTu9DPCcfnguSJBRp5u5tuh4cs4Fcut0PteiGjfwOgn7kXoTjp\n\tBLgCzqI7n0imzLzJLKXvjPGP4zPjyHt9Ppxvv8+odkjckBb9ADeddrMDrWKNuWMk\n\t0xV6L+hWQsSZTsDFiqigs1YjhaYerWoCJtN0j7i2yyqyo4/VTiL3gWPn/OBdDQKR\n\t2I1dmxyiAe13FbcQNTLoH28TT7YOH5hB4AIMiZ0lkabvbD/QqqJw==", "From": "Mattias Nissler <mnissler@meta.com>", "To": "<linux-pci@vger.kernel.org>", "CC": "=?utf-8?q?Martin_Mare=C5=A1?= <mj@ucw.cz>,\n Mattias Nissler <mnissler@meta.com>", "Subject": "[PATCH pciutils v3] ls-ecaps: Decode DPC RP PIO registers", "Date": "Fri, 17 Apr 2026 03:42:23 -0700", "Message-ID": "<20260417104223.3457417-1-mnissler@meta.com>", "X-Mailer": "git-send-email 2.52.0", "Precedence": "bulk", "X-Mailing-List": "linux-pci@vger.kernel.org", "List-Id": "<linux-pci.vger.kernel.org>", "List-Subscribe": "<mailto:linux-pci+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-pci+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Authority-Analysis": "v=2.4 cv=GKY41ONK c=1 sm=1 tr=0 ts=69e20ea5 cx=c_pps\n a=CB4LiSf2rd0gKozIdrpkBw==:117 a=CB4LiSf2rd0gKozIdrpkBw==:17\n a=A5OVakUREuEA:10 a=VkNPw1HP01LnGYTKEx00:22 a=7x6HtfJdh03M6CCDgxCd:22\n a=U_y8lYiYyhHBU5rMqhb2:22 a=VabnemYjAAAA:8 a=mvVm65g0eZYFh6_jv2gA:9\n a=gKebqoRLp9LExxC7YDUY:22", "X-Proofpoint-GUID": "NArfithib5f_WRI2-MoQ-l7wSnTDKAft", "X-Proofpoint-Spam-Details-Enc": "AW1haW4tMjYwNDE3MDEwNyBTYWx0ZWRfXwq/vH+hselW2\n h9QYM0SxP/oTwxVo6PA5/IsU+AwVEhQVuNh2EocyHZZ2+pJxsJhdNjLm8lj85WjGgnaDPVH60NZ\n IUoUL4iF6VMB+LJj/6xeC4BBMQE0RasScSaFVtLnT7dlk1VniE30vjq/zRHZamy+AqPqHaGFowz\n 4206dmNw5Gb1D1deOITSSboyInRem1MWbDVHv2ludr9K6BqX2wGyclO0qyjQ6Hul2YWgAtrYkfE\n lmZ56wsK2xENBzI0X9+miMUp2FlGdfgO+a8wyPQoBHJ5R5HONa0ahxHlE51eF3hECvi558Y0eE9\n 6PieKBJvzN1ywPs3EOWz6Y82rQfEjfiUfpnkmL3eCqtdGh0XHV6TGRlmWahHnI7iagxYUONdpGm\n HQ6EyBDp/UgnvQCbdXfzucxDetNSGpNek3F9znv4Er2Kdwv//ue5khYUCgMFb/usBKmVYia5aZM\n fmG4nQKmLVdlrOkXizg==", "X-Proofpoint-ORIG-GUID": "NArfithib5f_WRI2-MoQ-l7wSnTDKAft", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-04-16_04,2026-04-16_03,2025-10-01_01" }, "content": "The RP PIO registers in the DPC extended capability contain status\ninformation and control bits related to how root ports handle failing\nrequests.\n\nSample output:\n Capabilities: [380 v1] Downstream Port Containment\n DpcCap: IntMsgNum 0, RPExt+ PoisonedTLP+ SwTrigger+ RP PIO Log 6, DL_ActiveErr+\n DpcCtl: Trigger:0 Cmpl+ INT+ ErrCor+ PoisonedTLP- SwTrigger- DL_ActiveErr-\n DpcSta: Trigger- Reason:00 INT- RPBusy- TriggerExt:00 RP PIO ErrPtr:11\n Source: 0000\n RP PIO:\n Sta: CfgUR+ CfgCA- CfgCTO- IOUR- IOCA- IOCTO- MemUR- MemCA+ MemCTO-\n Msk: CfgUR+ CfgCA+ CfgCTO+ IOUR+ IOCA+ IOCTO+ MemUR- MemCA- MemCTO-\n Sev: CfgUR- CfgCA- CfgCTO- IOUR- IOCA- IOCTO- MemUR- MemCA- MemCTO-\n Err: CfgUR- CfgCA- CfgCTO- IOUR- IOCA- IOCTO- MemUR- MemCA- MemCTO-\n Exc: CfgUR- CfgCA- CfgCTO- IOUR- IOCA- IOCTO- MemUR- MemCA- MemCTO-\n HeaderLog: 00001001 0000220f f7a01100 00000000\n ImpSpecLog: 00000000\n TLPPrefixLog: 00000000\n\nSigned-off-by: Mattias Nissler <mnissler@meta.com>\n---\nChanges:\nv2:\n * fix style issues\n * correct DW read index for prefix log\nv3:\n * check log_size also for header log to align with config_fetch len\n---\n lib/header.h | 18 ++++++++++\n ls-ecaps.c | 100 ++++++++++++++++++++++++++++++++++++++++++++-------\n 2 files changed, 105 insertions(+), 13 deletions(-)", "diff": "diff --git a/lib/header.h b/lib/header.h\nindex 21fb628..507080f 100644\n--- a/lib/header.h\n+++ b/lib/header.h\n@@ -1454,6 +1454,7 @@\n #define PCI_DPC_CAP_SW_TRIGGER\t0x80\t\t/* DPC Software Trigger */\n #define PCI_DPC_CAP_RP_LOG(x)\t(((x) >> 8) & 0xf) /* DPC RP PIO Log Size */\n #define PCI_DPC_CAP_DL_ACT_ERR\t0x1000\t\t/* DPC DL_Active ERR_COR Signal */\n+#define PCI_DPC_CAP_RP_PIO_LOG_SIZE4\t0x2000\t/* RP PIO Log Size [4] */\n #define PCI_DPC_CTL\t\t6\t/* DPC Control */\n #define PCI_DPC_CTL_TRIGGER(x) ((x) & 0x3)\t/* DPC Trigger Enable */\n #define PCI_DPC_CTL_CMPL\t0x4\t\t/* DPC Completion Control */\n@@ -1470,6 +1471,23 @@\n #define PCI_DPC_STS_TRIGGER_EXT(x) (((x) >> 5) & 0x3) /* Trigger Reason Extension */\n #define PCI_DPC_STS_PIO_FEP(x) (((x) >> 8) & 0x1f) /* DPC PIO First Error Pointer */\n #define PCI_DPC_SOURCE\t\t10\t/* DPC Source ID */\n+#define PCI_DPC_RP_PIO_STATUS\t0xc\t/* DPC RP PIO Status */\n+#define PCI_DPC_RP_PIO_CFG_UR\t\t0x00000001\t/* Cfg Request UR Completion */\n+#define PCI_DPC_RP_PIO_CFG_CA\t\t0x00000002\t/* Cfg Request CA Completion */\n+#define PCI_DPC_RP_PIO_CFG_CTO\t\t0x00000004\t/* Cfg Request Completion Timeout */\n+#define PCI_DPC_RP_PIO_IO_UR\t\t0x00000100\t/* I/O Request UR Completion */\n+#define PCI_DPC_RP_PIO_IO_CA\t\t0x00000200\t/* I/O Request CA Completion */\n+#define PCI_DPC_RP_PIO_IO_CTO\t\t0x00000400\t/* I/O Request Completion Timeout */\n+#define PCI_DPC_RP_PIO_MEM_UR\t\t0x00010000\t/* Mem Request UR Completion */\n+#define PCI_DPC_RP_PIO_MEM_CA\t\t0x00020000\t/* Mem Request CA Completion */\n+#define PCI_DPC_RP_PIO_MEM_CTO\t\t0x00040000\t/* Mem Request Completion Timeout */\n+#define PCI_DPC_RP_PIO_MASK\t0x10\t/* DPC RP PIO Mask */\n+#define PCI_DPC_RP_PIO_SEVERITY\t0x14\t/* DPC RP PIO Severity */\n+#define PCI_DPC_RP_PIO_SYSERROR\t0x18\t/* DPC RP PIO SysError */\n+#define PCI_DPC_RP_PIO_EXCEPTION\t0x1c\t/* DPC RP PIO Exception */\n+#define PCI_DPC_RP_PIO_HEADER_LOG\t0x20\t/* DPC RP PIO Header Log */\n+#define PCI_DPC_RP_PIO_IMPSPEC_LOG\t0x30\t/* DPC RP PIO ImpSpec Log */\n+#define PCI_DPC_RP_PIO_TLP_PREFIX_LOG\t0x34\t/* DPC RP PIO TLP Prefix Log */\n \n /* L1 PM Substates Extended Capability */\n #define PCI_L1PM_SUBSTAT_CAP\t0x4\t/* L1 PM Substate Capability */\ndiff --git a/ls-ecaps.c b/ls-ecaps.c\nindex 455c203..8239fd2 100644\n--- a/ls-ecaps.c\n+++ b/ls-ecaps.c\n@@ -233,7 +233,9 @@ cap_aer(struct device *d, int where, int type)\n \n static void cap_dpc(struct device *d, int where)\n {\n- u16 l;\n+ u16 cap, w, log_size;\n+ u32 l, l0, l1, l2, l3;\n+ int i;\n \n printf(\"Downstream Port Containment\\n\");\n if (verbose < 2)\n@@ -242,24 +244,96 @@ static void cap_dpc(struct device *d, int where)\n if (!config_fetch(d, where + PCI_DPC_CAP, 8))\n return;\n \n- l = get_conf_word(d, where + PCI_DPC_CAP);\n+ w = cap = get_conf_word(d, where + PCI_DPC_CAP);\n+ log_size = PCI_DPC_CAP_RP_LOG(cap) | (!!(PCI_DPC_CAP_RP_PIO_LOG_SIZE4 & cap) << 4);\n printf(\"\\t\\tDpcCap:\\tIntMsgNum %d, RPExt%c PoisonedTLP%c SwTrigger%c RP PIO Log %d, DL_ActiveErr%c\\n\",\n- PCI_DPC_CAP_INT_MSG(l), FLAG(l, PCI_DPC_CAP_RP_EXT), FLAG(l, PCI_DPC_CAP_TLP_BLOCK),\n- FLAG(l, PCI_DPC_CAP_SW_TRIGGER), PCI_DPC_CAP_RP_LOG(l), FLAG(l, PCI_DPC_CAP_DL_ACT_ERR));\n+ PCI_DPC_CAP_INT_MSG(w), FLAG(w, PCI_DPC_CAP_RP_EXT), FLAG(w, PCI_DPC_CAP_TLP_BLOCK),\n+ FLAG(w, PCI_DPC_CAP_SW_TRIGGER), log_size, FLAG(w, PCI_DPC_CAP_DL_ACT_ERR));\n \n- l = get_conf_word(d, where + PCI_DPC_CTL);\n+ w = get_conf_word(d, where + PCI_DPC_CTL);\n printf(\"\\t\\tDpcCtl:\\tTrigger:%x Cmpl%c INT%c ErrCor%c PoisonedTLP%c SwTrigger%c DL_ActiveErr%c\\n\",\n- PCI_DPC_CTL_TRIGGER(l), FLAG(l, PCI_DPC_CTL_CMPL), FLAG(l, PCI_DPC_CTL_INT),\n- FLAG(l, PCI_DPC_CTL_ERR_COR), FLAG(l, PCI_DPC_CTL_TLP), FLAG(l, PCI_DPC_CTL_SW_TRIGGER),\n- FLAG(l, PCI_DPC_CTL_DL_ACTIVE));\n+ PCI_DPC_CTL_TRIGGER(w), FLAG(w, PCI_DPC_CTL_CMPL), FLAG(w, PCI_DPC_CTL_INT),\n+ FLAG(w, PCI_DPC_CTL_ERR_COR), FLAG(w, PCI_DPC_CTL_TLP), FLAG(w, PCI_DPC_CTL_SW_TRIGGER),\n+ FLAG(w, PCI_DPC_CTL_DL_ACTIVE));\n \n- l = get_conf_word(d, where + PCI_DPC_STATUS);\n+ w = get_conf_word(d, where + PCI_DPC_STATUS);\n printf(\"\\t\\tDpcSta:\\tTrigger%c Reason:%02x INT%c RPBusy%c TriggerExt:%02x RP PIO ErrPtr:%02x\\n\",\n- FLAG(l, PCI_DPC_STS_TRIGGER), PCI_DPC_STS_REASON(l), FLAG(l, PCI_DPC_STS_INT),\n- FLAG(l, PCI_DPC_STS_RP_BUSY), PCI_DPC_STS_TRIGGER_EXT(l), PCI_DPC_STS_PIO_FEP(l));\n+ FLAG(w, PCI_DPC_STS_TRIGGER), PCI_DPC_STS_REASON(w), FLAG(w, PCI_DPC_STS_INT),\n+ FLAG(w, PCI_DPC_STS_RP_BUSY), PCI_DPC_STS_TRIGGER_EXT(w), PCI_DPC_STS_PIO_FEP(w));\n+\n+ w = get_conf_word(d, where + PCI_DPC_SOURCE);\n+ printf(\"\\t\\tSource:\\t%04x\\n\", w);\n+\n+ if ((cap & PCI_DPC_CAP_RP_EXT) && config_fetch(d, where + PCI_DPC_CAP + 8, 20 + 4 * log_size))\n+ {\n+ printf(\"\\t\\tRP PIO:\\n\");\n+\n+ l = get_conf_long(d, where + PCI_DPC_RP_PIO_STATUS);\n+ printf(\"\\t\\t\\tSta: CfgUR%c CfgCA%c CfgCTO%c IOUR%c IOCA%c IOCTO%c MemUR%c MemCA%c MemCTO%c\\n\",\n+ FLAG(l, PCI_DPC_RP_PIO_CFG_UR), FLAG(l, PCI_DPC_RP_PIO_CFG_CA),\n+ FLAG(l, PCI_DPC_RP_PIO_CFG_CTO), FLAG(l, PCI_DPC_RP_PIO_IO_UR),\n+ FLAG(l, PCI_DPC_RP_PIO_IO_CA), FLAG(l, PCI_DPC_RP_PIO_IO_CTO),\n+ FLAG(l, PCI_DPC_RP_PIO_MEM_UR), FLAG(l, PCI_DPC_RP_PIO_MEM_CA),\n+ FLAG(l, PCI_DPC_RP_PIO_MEM_CTO));\n+\n+ l = get_conf_long(d, where + PCI_DPC_RP_PIO_MASK);\n+ printf(\"\\t\\t\\tMsk: CfgUR%c CfgCA%c CfgCTO%c IOUR%c IOCA%c IOCTO%c MemUR%c MemCA%c MemCTO%c\\n\",\n+ FLAG(l, PCI_DPC_RP_PIO_CFG_UR), FLAG(l, PCI_DPC_RP_PIO_CFG_CA),\n+ FLAG(l, PCI_DPC_RP_PIO_CFG_CTO), FLAG(l, PCI_DPC_RP_PIO_IO_UR),\n+ FLAG(l, PCI_DPC_RP_PIO_IO_CA), FLAG(l, PCI_DPC_RP_PIO_IO_CTO),\n+ FLAG(l, PCI_DPC_RP_PIO_MEM_UR), FLAG(l, PCI_DPC_RP_PIO_MEM_CA),\n+ FLAG(l, PCI_DPC_RP_PIO_MEM_CTO));\n+\n+ l = get_conf_long(d, where + PCI_DPC_RP_PIO_SEVERITY);\n+ printf(\"\\t\\t\\tSev: CfgUR%c CfgCA%c CfgCTO%c IOUR%c IOCA%c IOCTO%c MemUR%c MemCA%c MemCTO%c\\n\",\n+ FLAG(l, PCI_DPC_RP_PIO_CFG_UR), FLAG(l, PCI_DPC_RP_PIO_CFG_CA),\n+ FLAG(l, PCI_DPC_RP_PIO_CFG_CTO), FLAG(l, PCI_DPC_RP_PIO_IO_UR),\n+ FLAG(l, PCI_DPC_RP_PIO_IO_CA), FLAG(l, PCI_DPC_RP_PIO_IO_CTO),\n+ FLAG(l, PCI_DPC_RP_PIO_MEM_UR), FLAG(l, PCI_DPC_RP_PIO_MEM_CA),\n+ FLAG(l, PCI_DPC_RP_PIO_MEM_CTO));\n+\n+ l = get_conf_long(d, where + PCI_DPC_RP_PIO_SYSERROR);\n+ printf(\"\\t\\t\\tErr: CfgUR%c CfgCA%c CfgCTO%c IOUR%c IOCA%c IOCTO%c MemUR%c MemCA%c MemCTO%c\\n\",\n+ FLAG(l, PCI_DPC_RP_PIO_CFG_UR), FLAG(l, PCI_DPC_RP_PIO_CFG_CA),\n+ FLAG(l, PCI_DPC_RP_PIO_CFG_CTO), FLAG(l, PCI_DPC_RP_PIO_IO_UR),\n+ FLAG(l, PCI_DPC_RP_PIO_IO_CA), FLAG(l, PCI_DPC_RP_PIO_IO_CTO),\n+ FLAG(l, PCI_DPC_RP_PIO_MEM_UR), FLAG(l, PCI_DPC_RP_PIO_MEM_CA),\n+ FLAG(l, PCI_DPC_RP_PIO_MEM_CTO));\n+\n+ l = get_conf_long(d, where + PCI_DPC_RP_PIO_EXCEPTION);\n+ printf(\"\\t\\t\\tExc: CfgUR%c CfgCA%c CfgCTO%c IOUR%c IOCA%c IOCTO%c MemUR%c MemCA%c MemCTO%c\\n\",\n+ FLAG(l, PCI_DPC_RP_PIO_CFG_UR), FLAG(l, PCI_DPC_RP_PIO_CFG_CA),\n+ FLAG(l, PCI_DPC_RP_PIO_CFG_CTO), FLAG(l, PCI_DPC_RP_PIO_IO_UR),\n+ FLAG(l, PCI_DPC_RP_PIO_IO_CA), FLAG(l, PCI_DPC_RP_PIO_IO_CTO),\n+ FLAG(l, PCI_DPC_RP_PIO_MEM_UR), FLAG(l, PCI_DPC_RP_PIO_MEM_CA),\n+ FLAG(l, PCI_DPC_RP_PIO_MEM_CTO));\n+\n+ if (log_size >= 4)\n+ {\n+ l0 = get_conf_long(d, where + PCI_DPC_RP_PIO_HEADER_LOG);\n+ l1 = get_conf_long(d, where + PCI_DPC_RP_PIO_HEADER_LOG + 4);\n+ l2 = get_conf_long(d, where + PCI_DPC_RP_PIO_HEADER_LOG + 8);\n+ l3 = get_conf_long(d, where + PCI_DPC_RP_PIO_HEADER_LOG + 12);\n+ printf(\"\\t\\t\\tHeaderLog: %08x %08x %08x %08x\\n\", l0, l1, l2, l3);\n+ }\n \n- l = get_conf_word(d, where + PCI_DPC_SOURCE);\n- printf(\"\\t\\tSource:\\t%04x\\n\", l);\n+ if (log_size >= 5)\n+ {\n+ l = get_conf_long(d, where + PCI_DPC_RP_PIO_IMPSPEC_LOG);\n+ printf(\"\\t\\t\\tImpSpecLog: %08x\\n\", l);\n+ }\n+\n+ if (log_size >= 6)\n+ {\n+ printf(\"\\t\\t\\tTLPPrefixLog:\");\n+ for (i = 5; i < log_size; i++)\n+ {\n+ l = get_conf_long(d, where + PCI_DPC_RP_PIO_TLP_PREFIX_LOG + (i - 5) * 4);\n+ printf(\" %08x\", l);\n+ }\n+ printf(\"\\n\");\n+ }\n+ }\n }\n \n static void\n", "prefixes": [ "pciutils", "v3" ] }