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GET /api/1.2/patches/2224262/?format=api
{ "id": 2224262, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2224262/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260417080328.31918-1-antonb@tenstorrent.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.2/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260417080328.31918-1-antonb@tenstorrent.com>", "list_archive_url": null, "date": "2026-04-17T08:03:28", "name": "target/riscv: rvv: Handle source overlap of vector widening reduction instructions", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "741d2979462ff586f119a664acded47da3286635", "submitter": { "id": 89071, "url": "http://patchwork.ozlabs.org/api/1.2/people/89071/?format=api", "name": "Anton Blanchard", "email": "antonb@tenstorrent.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260417080328.31918-1-antonb@tenstorrent.com/mbox/", "series": [ { "id": 500264, "url": "http://patchwork.ozlabs.org/api/1.2/series/500264/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500264", "date": "2026-04-17T08:03:28", "name": "target/riscv: rvv: Handle source overlap of vector widening reduction instructions", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/500264/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2224262/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2224262/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=tenstorrent.com header.i=@tenstorrent.com\n header.a=rsa-sha256 header.s=google header.b=XefN9Tpu;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail-ot1-x330.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Widening reductions read vs2 as a vector of SEW elements and vs1[0] as a\nscalar of 2*SEW. The ISA does not allow the same vector register to be read\nwith different EEWs, so they must not overlap.\n\nvs1 is read as a scalar from element 0, so it is treated as a single vector\nregister (independent of LMUL) when checking overlap.\n\nSigned-off-by: Anton Blanchard <antonb@tenstorrent.com>\n---\n target/riscv/insn_trans/trans_rvv.c.inc | 1 +\n 1 file changed, 1 insertion(+)", "diff": "diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc\nindex 4df9a40b44..d9a0027e0b 100644\n--- a/target/riscv/insn_trans/trans_rvv.c.inc\n+++ b/target/riscv/insn_trans/trans_rvv.c.inc\n@@ -3062,6 +3062,7 @@ GEN_OPIVV_TRANS(vredxor_vs, reduction_check)\n static bool reduction_widen_check(DisasContext *s, arg_rmrr *a)\n {\n return reduction_check(s, a) && (s->sew < MO_64) &&\n+ !is_overlapped(a->rs1, 1, a->rs2, 1 << MAX(s->lmul, 0)) &&\n ((s->sew + 1) <= (s->cfg_ptr->elen >> 4));\n }\n \n", "prefixes": [] }