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GET /api/1.2/patches/2224245/?format=api
{ "id": 2224245, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2224245/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20260417071546.1610330-3-ghidoliemanuele@gmail.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/1.2/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260417071546.1610330-3-ghidoliemanuele@gmail.com>", "list_archive_url": null, "date": "2026-04-17T07:13:32", "name": "[v2,2/3] board: toradex: add Toradex Verdin iMX95", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "f0971615433aa3e9e8f17c0637a9297d0a60fa92", "submitter": { "id": 85913, "url": "http://patchwork.ozlabs.org/api/1.2/people/85913/?format=api", "name": "Emanuele Ghidoli", "email": "ghidoliemanuele@gmail.com" }, "delegate": { "id": 151988, "url": "http://patchwork.ozlabs.org/api/1.2/users/151988/?format=api", "username": "festevam", "first_name": "Fabio", "last_name": "Estevam", "email": "festevam@gmail.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20260417071546.1610330-3-ghidoliemanuele@gmail.com/mbox/", "series": [ { "id": 500248, "url": "http://patchwork.ozlabs.org/api/1.2/series/500248/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=500248", "date": "2026-04-17T07:13:30", "name": "add Toradex Verdin iMX95 support", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/500248/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2224245/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2224245/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=VbwT8Tk+;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org)", "phobos.denx.de;\n dmarc=pass (p=none dis=none) header.from=gmail.com", "phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de", "phobos.denx.de;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.b=\"VbwT8Tk+\";\n\tdkim-atps=neutral", "phobos.denx.de;\n dmarc=pass (p=none dis=none) header.from=gmail.com", "phobos.denx.de;\n spf=pass smtp.mailfrom=ghidoliemanuele@gmail.com" ], "Received": [ "from phobos.denx.de (phobos.denx.de\n [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fxmQH63v4z1yD3\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 17 Apr 2026 17:16:23 +1000 (AEST)", "from h2850616.stratoserver.net (localhost [IPv6:::1])\n\tby phobos.denx.de (Postfix) with ESMTP id 566408426C;\n\tFri, 17 Apr 2026 09:16:03 +0200 (CEST)", "by phobos.denx.de (Postfix, from userid 109)\n id 27DC28421D; Fri, 17 Apr 2026 09:15:56 +0200 (CEST)", "from mail-wm1-x32c.google.com (mail-wm1-x32c.google.com\n [IPv6:2a00:1450:4864:20::32c])\n (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits))\n (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id 5D1AE83BC8\n for <u-boot@lists.denx.de>; Fri, 17 Apr 2026 09:15:52 +0200 (CEST)", "by mail-wm1-x32c.google.com with SMTP id\n 5b1f17b1804b1-488a29e6110so2663865e9.3\n for <u-boot@lists.denx.de>; Fri, 17 Apr 2026 00:15:52 -0700 (PDT)", "from emanueleg-nb.homenet.telecomitalia.it\n (host-87-2-163-213.retail.telecomitalia.it. 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5b1f17b1804b1-488fb79dc55mr21803045e9.30.1776410151294;\n Fri, 17 Apr 2026 00:15:51 -0700 (PDT)", "From": "Emanuele Ghidoli <ghidoliemanuele@gmail.com>", "To": "Tom Rini <trini@konsulko.com>, Stefano Babic <sbabic@nabladev.com>,\n Fabio Estevam <festevam@gmail.com>,\n \"NXP i.MX U-Boot Team\" <uboot-imx@nxp.com>,\n Francesco Dolcini <francesco.dolcini@toradex.com>", "Cc": "Emanuele Ghidoli <emanuele.ghidoli@toradex.com>,\n \"Peng Fan\" <peng.fan@nxp.com>, \"Alice Guo\" <alice.guo@nxp.com>,\n \"Sumit Garg\" <sumit.garg@oss.qualcomm.com>, Simon Glass <sjg@chromium.org>,\n u-boot@lists.denx.de, Ernest Van Hoecke <ernest.vanhoecke@toradex.com>", "Subject": "[PATCH v2 2/3] board: toradex: add Toradex Verdin iMX95", "Date": "Fri, 17 Apr 2026 09:13:32 +0200", "Message-ID": "<20260417071546.1610330-3-ghidoliemanuele@gmail.com>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260417071546.1610330-1-ghidoliemanuele@gmail.com>", "References": "<20260417071546.1610330-1-ghidoliemanuele@gmail.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.39", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.103.8 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "From: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>\n\nAdd support for the Toradex Verdin iMX95.\n\nLink: https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx95\nLink: https://www.toradex.com/products/carrier-board/verdin-development-board-kit\nSigned-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>\nCo-developed-by: Ernest Van Hoecke <ernest.vanhoecke@toradex.com>\nSigned-off-by: Ernest Van Hoecke <ernest.vanhoecke@toradex.com>\nCo-developed-by: Francesco Dolcini <francesco.dolcini@toradex.com>\nSigned-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>\n---\n arch/arm/dts/imx95-verdin-dev.dtsi | 239 ++++\n .../arm/dts/imx95-verdin-wifi-dev-u-boot.dtsi | 112 ++\n arch/arm/dts/imx95-verdin-wifi-dev.dts | 21 +\n arch/arm/dts/imx95-verdin-wifi.dtsi | 50 +\n arch/arm/dts/imx95-verdin.dtsi | 1172 +++++++++++++++++\n arch/arm/mach-imx/imx9/Kconfig | 5 +\n board/toradex/verdin-imx95/Kconfig | 36 +\n board/toradex/verdin-imx95/MAINTAINERS | 13 +\n board/toradex/verdin-imx95/Makefile | 8 +\n board/toradex/verdin-imx95/spl.c | 75 ++\n board/toradex/verdin-imx95/verdin-imx95.c | 79 ++\n board/toradex/verdin-imx95/verdin-imx95.env | 20 +\n configs/verdin-imx95_defconfig | 183 +++\n doc/board/toradex/index.rst | 1 +\n doc/board/toradex/verdin-imx95.rst | 171 +++\n include/configs/verdin-imx95.h | 27 +\n 16 files changed, 2212 insertions(+)\n create mode 100644 arch/arm/dts/imx95-verdin-dev.dtsi\n create mode 100644 arch/arm/dts/imx95-verdin-wifi-dev-u-boot.dtsi\n create mode 100644 arch/arm/dts/imx95-verdin-wifi-dev.dts\n create mode 100644 arch/arm/dts/imx95-verdin-wifi.dtsi\n create mode 100644 arch/arm/dts/imx95-verdin.dtsi\n create mode 100644 board/toradex/verdin-imx95/Kconfig\n create mode 100644 board/toradex/verdin-imx95/MAINTAINERS\n create mode 100644 board/toradex/verdin-imx95/Makefile\n create mode 100644 board/toradex/verdin-imx95/spl.c\n create mode 100644 board/toradex/verdin-imx95/verdin-imx95.c\n create mode 100644 board/toradex/verdin-imx95/verdin-imx95.env\n create mode 100644 configs/verdin-imx95_defconfig\n create mode 100644 doc/board/toradex/verdin-imx95.rst\n create mode 100644 include/configs/verdin-imx95.h", "diff": "diff --git a/arch/arm/dts/imx95-verdin-dev.dtsi b/arch/arm/dts/imx95-verdin-dev.dtsi\nnew file mode 100644\nindex 000000000000..803480eef476\n--- /dev/null\n+++ b/arch/arm/dts/imx95-verdin-dev.dtsi\n@@ -0,0 +1,239 @@\n+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n+/*\n+ * Copyright (c) Toradex\n+ *\n+ * Common dtsi for Verdin iMX95 SoM on development carrier board\n+ *\n+ * https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx95\n+ * https://www.toradex.com/products/carrier-board/verdin-development-board-kit\n+ */\n+\n+/ {\n+\taliases {\n+\t\teeprom1 = &carrier_eeprom;\n+\t};\n+\n+\tsound {\n+\t\tcompatible = \"simple-audio-card\";\n+\t\tsimple-audio-card,bitclock-master = <&codec_dai>;\n+\t\tsimple-audio-card,format = \"i2s\";\n+\t\tsimple-audio-card,frame-master = <&codec_dai>;\n+\t\tsimple-audio-card,mclk-fs = <256>;\n+\t\tsimple-audio-card,name = \"verdin-nau8822\";\n+\t\tsimple-audio-card,routing =\n+\t\t\t\"Headphones\", \"LHP\",\n+\t\t\t\"Headphones\", \"RHP\",\n+\t\t\t\"Speaker\", \"LSPK\",\n+\t\t\t\"Speaker\", \"RSPK\",\n+\t\t\t\"Line Out\", \"AUXOUT1\",\n+\t\t\t\"Line Out\", \"AUXOUT2\",\n+\t\t\t\"LAUX\", \"Line In\",\n+\t\t\t\"RAUX\", \"Line In\",\n+\t\t\t\"LMICP\", \"Mic In\",\n+\t\t\t\"RMICP\", \"Mic In\";\n+\t\tsimple-audio-card,widgets =\n+\t\t\t\"Headphones\", \"Headphones\",\n+\t\t\t\"Line Out\", \"Line Out\",\n+\t\t\t\"Speaker\", \"Speaker\",\n+\t\t\t\"Microphone\", \"Mic In\",\n+\t\t\t\"Line\", \"Line In\";\n+\n+\t\tcodec_dai: simple-audio-card,codec {\n+\t\t\tclocks = <&scmi_clk IMX95_CLK_SAI3>;\n+\t\t\tsound-dai = <&nau8822_1a>;\n+\t\t};\n+\n+\t\tsimple-audio-card,cpu {\n+\t\t\tsound-dai = <&sai3>;\n+\t\t};\n+\t};\n+};\n+\n+/* Verdin ADC_1, ADC_2, ADC_3 and ADC_4 */\n+&adc1 {\n+\tstatus = \"okay\";\n+};\n+\n+/* Verdin ETH_1 (On-module PHY) */\n+&enetc_port0 {\n+\tstatus = \"okay\";\n+};\n+\n+/* Verdin ETH_2_RGMII */\n+&enetc_port1 {\n+\tphy-handle = <ðphy2>;\n+\tphy-mode = \"rgmii-id\";\n+\tstatus = \"okay\";\n+};\n+\n+/* Verdin QSPI_1 */\n+&flexspi1 {\n+\tstatus = \"okay\";\n+};\n+\n+&gpio1 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pinctrl_ctrl_sleep_moci>;\n+};\n+\n+&gpio2 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pinctrl_gpio1>,\n+\t\t <&pinctrl_gpio2>,\n+\t\t <&pinctrl_gpio3>;\n+};\n+\n+&gpio3 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pinctrl_gpio6>;\n+};\n+\n+&gpio4 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pinctrl_gpio5>;\n+};\n+\n+&gpio5 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pinctrl_gpio4>;\n+};\n+\n+/* Verdin I2C_3_HDMI */\n+&i3c2 {\n+\tstatus = \"okay\";\n+};\n+\n+/* Verdin I2C_2_DSI */\n+&lpi2c3 {\n+\tstatus = \"okay\";\n+};\n+\n+/* Verdin I2C_1 */\n+&lpi2c4 {\n+\tstatus = \"okay\";\n+\n+\tnau8822_1a: audio-codec@1a {\n+\t\tcompatible = \"nuvoton,nau8822\";\n+\t\treg = <0x1a>;\n+\t\tpinctrl-names = \"default\";\n+\t\tpinctrl-0 = <&pinctrl_sai3_mclk>;\n+\t\t#sound-dai-cells = <0>;\n+\t};\n+\n+\tcarrier_gpio_expander: gpio@21 {\n+\t\tcompatible = \"nxp,pcal6416\";\n+\t\treg = <0x21>;\n+\t\t#gpio-cells = <2>;\n+\t\tgpio-controller;\n+\t};\n+\n+\t/* Current measurement into module VCC */\n+\thwmon@40 {\n+\t\tcompatible = \"ti,ina219\";\n+\t\treg = <0x40>;\n+\t\tshunt-resistor = <10000>;\n+\t};\n+\n+\ttemperature-sensor@4f {\n+\t\tcompatible = \"ti,tmp75c\";\n+\t\treg = <0x4f>;\n+\t};\n+\n+\tcarrier_eeprom: eeprom@57 {\n+\t\tcompatible = \"st,24c02\", \"atmel,24c02\";\n+\t\treg = <0x57>;\n+\t\tpagesize = <16>;\n+\t};\n+};\n+\n+/* Verdin I2C_4_CSI */\n+&lpi2c5 {\n+\tstatus = \"okay\";\n+};\n+\n+/* Verdin UART_3, used as the Linux console */\n+&lpuart1 {\n+\tstatus = \"okay\";\n+};\n+\n+/* Verdin UART_4 */\n+&lpuart2 {\n+\tstatus = \"okay\";\n+};\n+\n+/* Verdin UART_1, connector X50 through RS485 transceiver */\n+&lpuart7 {\n+\trs485-rts-active-low;\n+\trs485-rx-during-tx;\n+\tlinux,rs485-enabled-at-boot-time;\n+\n+\tstatus = \"okay\";\n+};\n+\n+/* Verdin UART_2 */\n+&lpuart8 {\n+\tstatus = \"okay\";\n+};\n+\n+&netc_emdio {\n+\tethphy2: ethernet-phy@7 {\n+\t\tcompatible = \"ethernet-phy-ieee802.3-c22\";\n+\t\treg = <7>;\n+\t\tpinctrl-names = \"default\";\n+\t\tpinctrl-0 = <&pinctrl_eth2_rgmii_int>;\n+\t\tinterrupt-parent = <&gpio1>;\n+\t\tinterrupts = <12 IRQ_TYPE_LEVEL_LOW>;\n+\t\tmicrel,led-mode = <0>;\n+\t};\n+};\n+\n+/* Verdin PCIE_1 */\n+&pcie0 {\n+\tstatus = \"okay\";\n+};\n+\n+/* Verdin I2S_1 */\n+&sai3 {\n+\tstatus = \"okay\";\n+};\n+\n+/* Verdin PWM_1 */\n+&tpm4 {\n+\tstatus = \"okay\";\n+};\n+\n+/* Verdin PWM_2 */\n+&tpm5 {\n+\tstatus = \"okay\";\n+};\n+\n+/* Verdin PWM_3_DSI */\n+&tpm6 {\n+\tstatus = \"okay\";\n+};\n+\n+/* Verdin USB_1 */\n+&usb2 {\n+\tstatus = \"okay\";\n+};\n+\n+/* Verdin USB_2 */\n+&usb3 {\n+\tfsl,permanently-attached;\n+\n+\tstatus = \"okay\";\n+};\n+\n+&usb3_phy {\n+\tstatus = \"okay\";\n+};\n+\n+/* Verdin SD_1 */\n+&usdhc2 {\n+\tstatus = \"okay\";\n+};\n+\n+/* Verdin CTRL_WAKE1_MICO# */\n+&verdin_gpio_keys {\n+\tstatus = \"okay\";\n+};\ndiff --git a/arch/arm/dts/imx95-verdin-wifi-dev-u-boot.dtsi b/arch/arm/dts/imx95-verdin-wifi-dev-u-boot.dtsi\nnew file mode 100644\nindex 000000000000..83802156d523\n--- /dev/null\n+++ b/arch/arm/dts/imx95-verdin-wifi-dev-u-boot.dtsi\n@@ -0,0 +1,112 @@\n+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n+/* Copyright (c) Toradex */\n+\n+#include \"imx95-u-boot.dtsi\"\n+\n+/ {\n+\tsysinfo {\n+\t\tcompatible = \"toradex,sysinfo\";\n+\t};\n+};\n+\n+&{/binman/m33-oei-ddrfw/imx-lpddr/imx-lpddr-imem} {\n+\tfilename = \"lpddr4x_imem_v202409.bin\";\n+};\n+\n+&{/binman/m33-oei-ddrfw/imx-lpddr/imx-lpddr-dmem} {\n+\tfilename = \"lpddr4x_dmem_v202409.bin\";\n+};\n+\n+&{/binman/m33-oei-ddrfw/imx-lpddr-qb/imx-lpddr-imem-qb} {\n+\tfilename = \"lpddr4x_imem_qb_v202409.bin\";\n+};\n+\n+&{/binman/m33-oei-ddrfw/imx-lpddr-qb/imx-lpddr-dmem-qb} {\n+\tfilename = \"lpddr4x_dmem_qb_v202409.bin\";\n+};\n+\n+&gpio1 {\n+\treg = <0 0x47400000 0 0x1000>, <0 0x47400000 0 0x40>;\n+\tbootph-pre-ram;\n+\n+\tctrl-sleep-moci-hog {\n+\t\tbootph-pre-ram;\n+\t\tpinctrl-names = \"default\";\n+\t\tpinctrl-0 = <&pinctrl_ctrl_sleep_moci>;\n+\t\tgpio-hog;\n+\t\t/* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */\n+\t\tgpios = <14 GPIO_ACTIVE_HIGH>;\n+\t\tline-name = \"CTRL_SLEEP_MOCI#\";\n+\t\toutput-high;\n+\t};\n+};\n+\n+&som_gpio_expander {\n+\tbootph-pre-ram;\n+};\n+\n+&lpi2c2 {\n+\tbootph-pre-ram;\n+};\n+\n+&lpuart1 {\n+\tclocks = <&scmi_clk IMX95_CLK_LPUART1>, <&scmi_clk IMX95_CLK_LPUART1>;\n+\tclock-names = \"ipg\", \"per\";\n+\tbootph-pre-ram;\n+};\n+\n+&pinctrl_ctrl_sleep_moci {\n+\tbootph-pre-ram;\n+};\n+\n+&pinctrl_io_exp_int {\n+\tbootph-pre-ram;\n+};\n+\n+&pinctrl_lpi2c2 {\n+\tbootph-pre-ram;\n+};\n+\n+&pinctrl_lpi2c2_gpio {\n+\tbootph-pre-ram;\n+};\n+\n+&pinctrl_uart1 {\n+\tbootph-pre-ram;\n+};\n+\n+&pinctrl_usdhc1 {\n+\tbootph-pre-ram;\n+};\n+\n+&pinctrl_usdhc1_200mhz {\n+\tbootph-pre-ram;\n+};\n+\n+&som_gpio_expander {\n+\tbootph-pre-ram;\n+};\n+\n+&usb2 {\n+\t/delete-property/power-domains;\n+};\n+\n+&usb3 {\n+\tstatus = \"disabled\";\n+};\n+\n+&usb3_dwc3 {\n+\tstatus = \"disabled\";\n+};\n+\n+&usb_recov_ctrl {\n+\tbootph-pre-ram;\n+};\n+\n+&usdhc1 {\n+\tbootph-pre-ram;\n+};\n+\n+&wdog3 {\n+\tstatus = \"disabled\";\n+};\ndiff --git a/arch/arm/dts/imx95-verdin-wifi-dev.dts b/arch/arm/dts/imx95-verdin-wifi-dev.dts\nnew file mode 100644\nindex 000000000000..345d37247025\n--- /dev/null\n+++ b/arch/arm/dts/imx95-verdin-wifi-dev.dts\n@@ -0,0 +1,21 @@\n+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n+/*\n+ * Copyright (c) Toradex\n+ *\n+ * https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx95\n+ * https://www.toradex.com/products/carrier-board/verdin-development-board-kit\n+ */\n+\n+/dts-v1/;\n+\n+#include \"imx95-verdin.dtsi\"\n+#include \"imx95-verdin-wifi.dtsi\"\n+#include \"imx95-verdin-dev.dtsi\"\n+\n+/ {\n+\tmodel = \"Toradex Verdin iMX95 WB on Verdin Development Board\";\n+\tcompatible = \"toradex,verdin-imx95-wifi-dev\",\n+\t\t \"toradex,verdin-imx95-wifi\",\n+\t\t \"toradex,verdin-imx95\",\n+\t\t \"fsl,imx95\";\n+};\ndiff --git a/arch/arm/dts/imx95-verdin-wifi.dtsi b/arch/arm/dts/imx95-verdin-wifi.dtsi\nnew file mode 100644\nindex 000000000000..256c9ed04605\n--- /dev/null\n+++ b/arch/arm/dts/imx95-verdin-wifi.dtsi\n@@ -0,0 +1,50 @@\n+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n+/*\n+ * Copyright (c) Toradex\n+ *\n+ * Common dtsi for Verdin iMX95 SoM WB variant\n+ *\n+ * https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx95\n+ */\n+\n+/ {\n+\treg_wifi_en: regulator-wifi-en {\n+\t\tcompatible = \"regulator-fixed\";\n+\t\tpinctrl-names = \"default\";\n+\t\tpinctrl-0 = <&pinctrl_wifi_pwr_en>;\n+\t\t/* PMIC_EN_WIFI */\n+\t\tgpios = <&gpio1 11 GPIO_ACTIVE_HIGH>;\n+\t\tenable-active-high;\n+\t\tregulator-max-microvolt = <3300000>;\n+\t\tregulator-min-microvolt = <3300000>;\n+\t\tregulator-name = \"PDn_MAYA-W260\";\n+\t\tstartup-delay-us = <2000>;\n+\t};\n+};\n+\n+/* On-module Bluetooth */\n+&lpuart6 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pinctrl_bt_uart>;\n+\tuart-has-rtscts;\n+\n+\tstatus = \"okay\";\n+\n+\tsom_bt: bluetooth {\n+\t\tcompatible = \"nxp,88w8987-bt\";\n+\t\tfw-init-baudrate = <3000000>;\n+\t};\n+};\n+\n+/* On-module Wi-Fi */\n+&usdhc3 {\n+\tpinctrl-names = \"default\", \"state_100mhz\", \"state_200mhz\";\n+\tpinctrl-0 = <&pinctrl_usdhc3>;\n+\tpinctrl-1 = <&pinctrl_usdhc3>;\n+\tpinctrl-2 = <&pinctrl_usdhc3_200mhz>;\n+\tkeep-power-in-suspend;\n+\tnon-removable;\n+\tvmmc-supply = <®_wifi_en>;\n+\n+\tstatus = \"okay\";\n+};\ndiff --git a/arch/arm/dts/imx95-verdin.dtsi b/arch/arm/dts/imx95-verdin.dtsi\nnew file mode 100644\nindex 000000000000..29cd4b91a16c\n--- /dev/null\n+++ b/arch/arm/dts/imx95-verdin.dtsi\n@@ -0,0 +1,1172 @@\n+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n+/*\n+ * Copyright (c) Toradex\n+ *\n+ * Common dtsi for Verdin iMX95 SoM\n+ *\n+ * https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx95\n+ */\n+\n+#include <dt-bindings/net/ti-dp83867.h>\n+#include <dt-bindings/phy/phy-imx8-pcie.h>\n+#include \"imx95.dtsi\"\n+#include \"imx95-u-boot.dtsi\"\n+\n+/ {\n+\taliases {\n+\t\tcan0 = &flexcan1;\n+\t\tcan1 = &flexcan2;\n+\t\teeprom0 = &som_eeprom;\n+\t\tethernet0 = &enetc_port0;\n+\t\tethernet1 = &enetc_port1;\n+\t\ti2c0 = &lpi2c2;\n+\t\ti2c1 = &lpi2c4;\n+\t\ti2c2 = &lpi2c3;\n+\t\ti2c3 = &i3c2;\n+\t\ti2c4 = &lpi2c5;\n+\t\tmmc0 = &usdhc1;\n+\t\tmmc1 = &usdhc2;\n+\t\tmmc2 = &usdhc3;\n+\t\trtc0 = &rtc_i2c;\n+\t\trtc1 = &scmi_bbm;\n+\t\tserial0 = &lpuart7;\n+\t\tserial1 = &lpuart8;\n+\t\tserial2 = &lpuart1;\n+\t\tserial3 = &lpuart2;\n+\t\tserial4 = &lpuart6;\n+\t\tusb0 = &usb2;\n+\t\tusb1 = &usb3;\n+\t};\n+\n+\tchosen {\n+\t\tstdout-path = \"serial2:115200n8\";\n+\t};\n+\n+\tconnector {\n+\t\tcompatible = \"gpio-usb-b-connector\", \"usb-b-connector\";\n+\t\t/* Verdin USB_1_ID (SODIMM 161) */\n+\t\tid-gpios = <&som_gpio_expander 5 GPIO_ACTIVE_HIGH>;\n+\t\tlabel = \"USB_1\";\n+\t\tself-powered;\n+\t\tvbus-supply = <®_usb1_vbus>;\n+\n+\t\tport {\n+\t\t\tusb_dr_connector: endpoint {\n+\t\t\t\tremote-endpoint = <&usb1_id>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tverdin_gpio_keys: gpio-keys {\n+\t\tcompatible = \"gpio-keys\";\n+\t\tpinctrl-names = \"default\";\n+\t\tpinctrl-0 = <&pinctrl_ctrl_wake1_mico>;\n+\n+\t\tstatus = \"disabled\";\n+\n+\t\tverdin_key_wakeup: key-wakeup {\n+\t\t\t/* Verdin CTRL_WAKE1_MICO# (SODIMM 252) */\n+\t\t\tgpios = <&gpio1 10 GPIO_ACTIVE_LOW>;\n+\t\t\tlabel = \"Wake-Up\";\n+\t\t\tlinux,code = <KEY_WAKEUP>;\n+\t\t\twakeup-source;\n+\t\t};\n+\t};\n+\n+\treg_1p8v: regulator-1p8v {\n+\t\tcompatible = \"regulator-fixed\";\n+\t\tregulator-max-microvolt = <1800000>;\n+\t\tregulator-min-microvolt = <1800000>;\n+\t\tregulator-name = \"On-module +V1.8\";\n+\t};\n+\n+\t/*\n+\t * By default we enable CTRL_SLEEP_MOCI#, this is required to have\n+\t * peripherals on the carrier board powered.\n+\t * If more granularity or power saving is required this can be disabled\n+\t * in the carrier board device tree files.\n+\t */\n+\treg_force_sleep_moci: regulator-force-sleep-moci {\n+\t\tcompatible = \"regulator-fixed\";\n+\t\t/* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */\n+\t\tgpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;\n+\t\tenable-active-high;\n+\t\tregulator-always-on;\n+\t\tregulator-boot-on;\n+\t\tregulator-name = \"CTRL_SLEEP_MOCI#\";\n+\t};\n+\n+\treg_usb1_vbus: regulator-usb1-vbus {\n+\t\tcompatible = \"regulator-fixed\";\n+\t\t/* Verdin USB_1_EN (SODIMM 155) */\n+\t\tgpios = <&som_gpio_expander 7 GPIO_ACTIVE_HIGH>;\n+\t\tenable-active-high;\n+\t\tregulator-name = \"USB_1_EN\";\n+\t};\n+\n+\treg_usb2_vbus: regulator-usb2-vbus {\n+\t\tcompatible = \"regulator-fixed\";\n+\t\t/* Verdin USB_2_EN (SODIMM 185) */\n+\t\tgpios = <&som_gpio_expander 8 GPIO_ACTIVE_HIGH>;\n+\t\tenable-active-high;\n+\t\tregulator-name = \"USB_2_EN\";\n+\t};\n+\n+\treg_usdhc2_vqmmc: regulator-usdhc2-vqmmc {\n+\t\tcompatible = \"regulator-gpio\";\n+\t\tpinctrl-names = \"default\";\n+\t\tpinctrl-0 = <&pinctrl_usdhc2_vsel>;\n+\t\tgpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;\n+\t\tregulator-max-microvolt = <3300000>;\n+\t\tregulator-min-microvolt = <1800000>;\n+\t\tstates = <1800000 0x1>,\n+\t\t\t <3300000 0x0>;\n+\t\tregulator-name = \"PMIC_SD2_VSEL\";\n+\t};\n+\n+\treg_usdhc2_vmmc: regulator-vmmc-usdhc2 {\n+\t\tcompatible = \"regulator-fixed\";\n+\t\tpinctrl-names = \"default\";\n+\t\tpinctrl-0 = <&pinctrl_usdhc2_pwr_en>;\n+\t\t/* Verdin SD_1_PWR_EN (SODIMM 76) */\n+\t\tgpios = <&gpio3 7 GPIO_ACTIVE_HIGH>;\n+\t\tenable-active-high;\n+\t\toff-on-delay-us = <100000>;\n+\t\tregulator-max-microvolt = <3300000>;\n+\t\tregulator-min-microvolt = <3300000>;\n+\t\tregulator-name = \"SD_1_PWR_EN\";\n+\t\tstartup-delay-us = <20000>;\n+\t};\n+\n+\tcm7: remoteproc-cm7 {\n+\t\tcompatible = \"fsl,imx95-cm7\";\n+\t\tmbox-names = \"tx\", \"rx\", \"rxdb\";\n+\t\tmboxes = <&mu7 0 1\n+\t\t\t &mu7 1 1\n+\t\t\t &mu7 3 1>;\n+\t\tmemory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>,\n+\t\t\t\t<&vdev1vring0>, <&vdev1vring1>, <&rsc_table>, <&m7_reserved>;\n+\t};\n+\n+\treserved-memory {\n+\t\t#address-cells = <2>;\n+\t\t#size-cells = <2>;\n+\t\tranges;\n+\n+\t\tlinux_cma: linux,cma {\n+\t\t\tcompatible = \"shared-dma-pool\";\n+\t\t\treusable;\n+\t\t\tsize = <0 0x3c000000>;\n+\t\t\talloc-ranges = <0 0x80000000 0 0x7F000000>;\n+\t\t\tlinux,cma-default;\n+\t\t};\n+\n+\t\tm7_reserved: memory@80000000 {\n+\t\t\treg = <0 0x80000000 0 0x1000000>;\n+\t\t\tno-map;\n+\t\t};\n+\n+\t\tvdev0vring0: vdev0vring0@88000000 {\n+\t\t\treg = <0 0x88000000 0 0x8000>;\n+\t\t\tno-map;\n+\t\t};\n+\n+\t\tvdev0vring1: vdev0vring1@88008000 {\n+\t\t\treg = <0 0x88008000 0 0x8000>;\n+\t\t\tno-map;\n+\t\t};\n+\n+\t\tvdev1vring0: vdev1vring0@88010000 {\n+\t\t\treg = <0 0x88010000 0 0x8000>;\n+\t\t\tno-map;\n+\t\t};\n+\n+\t\tvdev1vring1: vdev1vring1@88018000 {\n+\t\t\treg = <0 0x88018000 0 0x8000>;\n+\t\t\tno-map;\n+\t\t};\n+\n+\t\tvdevbuffer: vdevbuffer@88020000 {\n+\t\t\tcompatible = \"shared-dma-pool\";\n+\t\t\treg = <0 0x88020000 0 0x100000>;\n+\t\t\tno-map;\n+\t\t};\n+\n+\t\trsc_table: rsc-table@88220000 {\n+\t\t\treg = <0 0x88220000 0 0x1000>;\n+\t\t\tno-map;\n+\t\t};\n+\t};\n+};\n+\n+/* Verdin ADC_1, ADC_2, ADC_3 and ADC_4 */\n+&adc1 {\n+\tvref-supply = <®_1p8v>;\n+};\n+\n+/* Verdin ETH_1 (On-module PHY) */\n+&enetc_port0 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pinctrl_enetc0>;\n+\tphy-handle = <ðphy1>;\n+\tphy-mode = \"rgmii-id\";\n+};\n+\n+/* Verdin ETH_2_RGMII */\n+&enetc_port1 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pinctrl_enetc1>;\n+};\n+\n+/* Verdin CAN_1 */\n+&flexcan1 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pinctrl_flexcan1>;\n+};\n+\n+/* Verdin CAN_2 */\n+&flexcan2 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pinctrl_flexcan2>;\n+};\n+\n+/* Verdin QSPI_1 */\n+&flexspi1 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pinctrl_flexspi1>;\n+};\n+\n+&gpio1 {\n+\tgpio-line-names =\n+\t\t\"\", /* 0 */\n+\t\t\"\",\n+\t\t\"\",\n+\t\t\"\",\n+\t\t\"SODIMM_147\",\n+\t\t\"SODIMM_149\",\n+\t\t\"SODIMM_151\",\n+\t\t\"SODIMM_153\",\n+\t\t\"SODIMM_20\",\n+\t\t\"SODIMM_22\",\n+\t\t\"SODIMM_252\", /* 10 */\n+\t\t\"\",\n+\t\t\"SODIMM_189\",\n+\t\t\"IO_EXP_INT\",\n+\t\t\"SODIMM_256\",\n+\t\t\"\";\n+\n+\tstatus = \"okay\";\n+};\n+\n+&gpio2 {\n+\tgpio-line-names =\n+\t\t\"SODIMM_206\", /* 0 */\n+\t\t\"SODIMM_198\",\n+\t\t\"SODIMM_200\",\n+\t\t\"SODIMM_196\",\n+\t\t\"\",\n+\t\t\"SODIMM_15\",\n+\t\t\"SODIMM_16\",\n+\t\t\"\",\n+\t\t\"SODIMM_131\",\n+\t\t\"SODIMM_129\",\n+\t\t\"SODIMM_135\", /* 10 */\n+\t\t\"SODIMM_133\",\n+\t\t\"SODIMM_139\",\n+\t\t\"SODIMM_137\",\n+\t\t\"SODIMM_143\",\n+\t\t\"SODIMM_141\",\n+\t\t\"SODIMM_30\",\n+\t\t\"SODIMM_38\",\n+\t\t\"SODIMM_208\",\n+\t\t\"SODIMM_19\",\n+\t\t\"SODIMM_36\", /* 20 */\n+\t\t\"SODIMM_34\",\n+\t\t\"SODIMM_93\",\n+\t\t\"SODIMM_95\",\n+\t\t\"SODIMM_210\",\n+\t\t\"SODIMM_24\",\n+\t\t\"SODIMM_32\",\n+\t\t\"SODIMM_26\",\n+\t\t\"SODIMM_53\",\n+\t\t\"SODIMM_55\",\n+\t\t\"SODIMM_12\", /* 30 */\n+\t\t\"SODIMM_14\";\n+};\n+\n+&gpio3 {\n+\tgpio-line-names =\n+\t\t\"SODIMM_84\", /* 0 */\n+\t\t\"SODIMM_78\",\n+\t\t\"SODIMM_74\",\n+\t\t\"SODIMM_80\",\n+\t\t\"SODIMM_82\",\n+\t\t\"SODIMM_70\",\n+\t\t\"SODIMM_72\",\n+\t\t\"SODIMM_76\",\n+\t\t\"\",\n+\t\t\"\",\n+\t\t\"\", /* 10 */\n+\t\t\"\",\n+\t\t\"\",\n+\t\t\"\",\n+\t\t\"\",\n+\t\t\"\",\n+\t\t\"\",\n+\t\t\"\",\n+\t\t\"\",\n+\t\t\"PMIC_SD2_VSEL\",\n+\t\t\"\", /* 20 */\n+\t\t\"\",\n+\t\t\"\",\n+\t\t\"\",\n+\t\t\"\",\n+\t\t\"\",\n+\t\t\"SODIMM_91\",\n+\t\t\"SODIMM_218\",\n+\t\t\"\",\n+\t\t\"\",\n+\t\t\"\", /* 30 */\n+\t\t\"\";\n+};\n+\n+&gpio4 {\n+\tgpio-line-names =\n+\t\t\"SODIMM_59\", /* 0 */\n+\t\t\"SODIMM_57\",\n+\t\t\"\",\n+\t\t\"\",\n+\t\t\"\",\n+\t\t\"\",\n+\t\t\"\",\n+\t\t\"\",\n+\t\t\"\",\n+\t\t\"\",\n+\t\t\"\", /* 10 */\n+\t\t\"\",\n+\t\t\"\",\n+\t\t\"\",\n+\t\t\"SODIMM_193\",\n+\t\t\"SODIMM_191\",\n+\t\t\"SODIMM_215\",\n+\t\t\"SODIMM_217\",\n+\t\t\"SODIMM_219\",\n+\t\t\"SODIMM_221\",\n+\t\t\"SODIMM_211\", /* 20 */\n+\t\t\"SODIMM_213\",\n+\t\t\"SODIMM_199\",\n+\t\t\"SODIMM_197\",\n+\t\t\"SODIMM_201\",\n+\t\t\"SODIMM_203\",\n+\t\t\"SODIMM_205\",\n+\t\t\"SODIMM_207\",\n+\t\t\"SODIMM_216\",\n+\t\t\"SODIMM_202\";\n+};\n+\n+&gpio5 {\n+\tgpio-line-names =\n+\t\t\"SODIMM_56\", /* 0 */\n+\t\t\"SODIMM_58\",\n+\t\t\"SODIMM_60\",\n+\t\t\"SODIMM_62\",\n+\t\t\"SODIMM_46\",\n+\t\t\"SODIMM_44\",\n+\t\t\"SODIMM_42\",\n+\t\t\"SODIMM_48\",\n+\t\t\"SODIMM_66\",\n+\t\t\"SODIMM_52\",\n+\t\t\"SODIMM_54\", /* 10 */\n+\t\t\"SODIMM_64\",\n+\t\t\"SODIMM_212\",\n+\t\t\"\",\n+\t\t\"\",\n+\t\t\"\",\n+\t\t\"\",\n+\t\t\"\";\n+};\n+\n+/* Verdin I2C_3_HDMI */\n+&i3c2 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pinctrl_i3c2>;\n+\ti2c-scl-hz = <400000>;\n+};\n+\n+/* CTRL_I2C (On-module I2C) */\n+&lpi2c2 {\n+\tpinctrl-names = \"default\", \"gpio\";\n+\tpinctrl-0 = <&pinctrl_lpi2c2>, <&pinctrl_io_exp_int>;\n+\tpinctrl-1 = <&pinctrl_lpi2c2_gpio>, <&pinctrl_io_exp_int>;\n+\tclock-frequency = <400000>;\n+\tscl-gpios = <&gpio1 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n+\tsda-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n+\tsingle-master;\n+\n+\tstatus = \"okay\";\n+\n+\tsom_gpio_expander: gpio@20 {\n+\t\tcompatible = \"nxp,pcal6416\";\n+\t\treg = <0x20>;\n+\t\t#interrupt-cells = <2>;\n+\t\tinterrupt-controller;\n+\t\tinterrupt-parent = <&gpio1>;\n+\t\tinterrupts = <13 IRQ_TYPE_LEVEL_LOW>;\n+\t\t#gpio-cells = <2>;\n+\t\tgpio-controller;\n+\n+\t\tgpio-line-names =\n+\t\t\t\"SODIMM_220\", /* 0 */\n+\t\t\t\"SODIMM_222\",\n+\t\t\t\"SODIMM_17\",\n+\t\t\t\"SODIMM_21\",\n+\t\t\t\"SODIMM_244\",\n+\t\t\t\"SODIMM_161\",\n+\t\t\t\"SODIMM_157\",\n+\t\t\t\"SODIMM_155\",\n+\t\t\t\"SODIMM_185\",\n+\t\t\t\"SODIMM_187\",\n+\t\t\t\"USB_RECOV_CTRL#\", /* 10 */\n+\t\t\t\"ENET1_INT#\",\n+\t\t\t\"TPM_INT#\",\n+\t\t\t\"TPM_CS#\",\n+\t\t\t\"\",\n+\t\t\t\"\";\n+\n+\t\t/*\n+\t\t * Switch USB to default position:\n+\t\t * - SoC USB2 -> Verdin USB_1\n+\t\t * - SoC USB1 -> Verdin USB_2\n+\t\t * Reset configuration:\n+\t\t * - SoC USB1 -> Verdin USB_1 (USB recovery)\n+\t\t * - SoC USB2 not connected\n+\t\t */\n+\t\tusb_recov_ctrl: usb-recov-ctrl-hog {\n+\t\t\tgpio-hog;\n+\t\t\tgpios = <10 GPIO_ACTIVE_HIGH>;\n+\t\t\tline-name = \"USB_RECOV_CTRL#\";\n+\t\t\toutput-high;\n+\t\t};\n+\t};\n+\n+\trtc_i2c: rtc@32 {\n+\t\tcompatible = \"epson,rx8130\";\n+\t\treg = <0x32>;\n+\t};\n+\n+\ttemperature-sensor@48 {\n+\t\tcompatible = \"ti,tmp1075\";\n+\t\treg = <0x48>;\n+\t};\n+\n+\tsom_eeprom: eeprom@50 {\n+\t\tcompatible = \"st,24c02\", \"atmel,24c02\";\n+\t\treg = <0x50>;\n+\t\tpagesize = <16>;\n+\t};\n+};\n+\n+/* Verdin I2C_2_DSI */\n+&lpi2c3 {\n+\tpinctrl-names = \"default\", \"gpio\";\n+\tpinctrl-0 = <&pinctrl_lpi2c3>;\n+\tpinctrl-1 = <&pinctrl_lpi2c3_gpio>;\n+\tclock-frequency = <100000>;\n+\tscl-gpios = <&gpio2 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n+\tsda-gpios = <&gpio2 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n+\tsingle-master;\n+};\n+\n+/* Verdin I2C_1 */\n+&lpi2c4 {\n+\tpinctrl-names = \"default\", \"gpio\";\n+\tpinctrl-0 = <&pinctrl_lpi2c4>;\n+\tpinctrl-1 = <&pinctrl_lpi2c4_gpio>;\n+\tclock-frequency = <100000>;\n+\tscl-gpios = <&gpio2 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n+\tsda-gpios = <&gpio2 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n+\tsingle-master;\n+};\n+\n+/* Verdin I2C_4_CSI */\n+&lpi2c5 {\n+\tpinctrl-names = \"default\", \"gpio\";\n+\tpinctrl-0 = <&pinctrl_lpi2c5>;\n+\tpinctrl-1 = <&pinctrl_lpi2c5_gpio>;\n+\tclock-frequency = <100000>;\n+\tscl-gpios = <&gpio2 23 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n+\tsda-gpios = <&gpio2 22 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n+\tsingle-master;\n+};\n+\n+/* Verdin SPI_1 */\n+&lpspi6 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pinctrl_lpspi6>, <&pinctrl_spi1_cs>;\n+\tcs-gpios = <&gpio4 29 GPIO_ACTIVE_LOW>,\n+\t\t <&som_gpio_expander 13 GPIO_ACTIVE_LOW>;\n+\n+\tstatus = \"okay\";\n+\n+\tsom_tpm: tpm@1 {\n+\t\tcompatible = \"infineon,slb9670\", \"tcg,tpm_tis-spi\";\n+\t\treg = <0x1>;\n+\t\tinterrupt-parent = <&som_gpio_expander>;\n+\t\tinterrupts = <12 IRQ_TYPE_EDGE_FALLING>;\n+\t\t/*\n+\t\t * Maximum TPM-supported speed is 18.5 MHz, limited to 12 MHz\n+\t\t * here as lpspi6's per-clock (twice the max speed) is 24 MHz\n+\t\t */\n+\t\tspi-max-frequency = <12000000>;\n+\t};\n+};\n+\n+/* Verdin UART_3, used as the Linux console */\n+&lpuart1 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pinctrl_uart1>;\n+};\n+\n+/* Verdin UART_4 */\n+&lpuart2 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pinctrl_uart2>;\n+};\n+\n+/* Verdin UART_1 */\n+&lpuart7 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pinctrl_uart7>;\n+\tuart-has-rtscts;\n+};\n+\n+/* Verdin UART_2 */\n+&lpuart8 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pinctrl_uart8>, <&pinctrl_uart8_cts>, <&pinctrl_uart8_rts>;\n+\tuart-has-rtscts;\n+};\n+\n+&mu7 {\n+\tstatus = \"okay\";\n+};\n+\n+&netc_blk_ctrl {\n+\tstatus = \"okay\";\n+};\n+\n+&netc_bus0 {\n+\tmsi-map = <0x0 &its 0x60 0x1>,\t//ENETC0 PF\n+\t\t <0x10 &its 0x61 0x1>, //ENETC0 VF0\n+\t\t <0x20 &its 0x62 0x1>, //ENETC0 VF1\n+\t\t <0x40 &its 0x63 0x1>, //ENETC1 PF\n+\t\t <0x50 &its 0x65 0x1>, //ENETC1 VF0\n+\t\t <0x60 &its 0x66 0x1>, //ENETC1 VF1\n+\t\t <0x80 &its 0x64 0x1>, //ENETC2 PF\n+\t\t <0xc0 &its 0x67 0x1>; //NETC Timer\n+\tiommu-map = <0x0 &smmu 0x20 0x1>,\n+\t\t <0x10 &smmu 0x21 0x1>,\n+\t\t <0x20 &smmu 0x22 0x1>,\n+\t\t <0x40 &smmu 0x23 0x1>,\n+\t\t <0x50 &smmu 0x25 0x1>,\n+\t\t <0x60 &smmu 0x26 0x1>,\n+\t\t <0x80 &smmu 0x24 0x1>,\n+\t\t <0xc0 &smmu 0x27 0x1>;\n+};\n+\n+/* Verdin ETH_2_RGMII_MDIO, shared between all ethernet ports */\n+&netc_emdio {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pinctrl_emdio>;\n+\n+\tstatus = \"okay\";\n+\n+\tethphy1: ethernet-phy@0 {\n+\t\treg = <0>;\n+\t\tinterrupt-parent = <&som_gpio_expander>;\n+\t\tinterrupts = <11 IRQ_TYPE_EDGE_FALLING>;\n+\t\tti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;\n+\t\tti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;\n+\t};\n+};\n+\n+&netc_timer {\n+\tstatus = \"okay\";\n+};\n+\n+&netcmix_blk_ctrl {\n+\tstatus = \"okay\";\n+};\n+\n+/* Verdin PCIE_1 */\n+&pcie0 {\n+\t/* PCIE_1_RESET# (SODIMM 244) */\n+\treset-gpios = <&som_gpio_expander 4 GPIO_ACTIVE_LOW>;\n+};\n+\n+/* Verdin I2S_1 */\n+&sai3 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pinctrl_sai3>;\n+\tassigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>,\n+\t\t\t <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>,\n+\t\t\t <&scmi_clk IMX95_CLK_AUDIOPLL1>,\n+\t\t\t <&scmi_clk IMX95_CLK_AUDIOPLL2>,\n+\t\t\t <&scmi_clk IMX95_CLK_SAI3>;\n+\tassigned-clock-parents = <0>, <0>, <0>, <0>,\n+\t\t\t\t <&scmi_clk IMX95_CLK_AUDIOPLL1>;\n+\tassigned-clock-rates = <3932160000>,\n+\t\t\t <3612672000>, <393216000>,\n+\t\t\t <361267200>, <12288000>;\n+\t#sound-dai-cells = <0>;\n+\tfsl,sai-mclk-direction-output;\n+};\n+\n+&scmi_bbm {\n+\tlinux,code = <KEY_POWER>;\n+};\n+\n+&thermal_zones {\n+\t/* PF09 Main PMIC */\n+\tpf09-thermal {\n+\t\tpolling-delay = <2000>;\n+\t\tpolling-delay-passive = <250>;\n+\t\tthermal-sensors = <&scmi_sensor 2>;\n+\n+\t\ttrips {\n+\t\t\ttrip0 {\n+\t\t\t\thysteresis = <2000>;\n+\t\t\t\ttemperature = <155000>;\n+\t\t\t\ttype = \"critical\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t/* PF53 VDD_ARM PMIC */\n+\tpf53-arm-thermal {\n+\t\tpolling-delay = <2000>;\n+\t\tpolling-delay-passive = <250>;\n+\t\tthermal-sensors = <&scmi_sensor 4>;\n+\n+\t\ttrips {\n+\t\t\ttrip0 {\n+\t\t\t\thysteresis = <2000>;\n+\t\t\t\ttemperature = <155000>;\n+\t\t\t\ttype = \"critical\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t/* PF53 VDD_SOC PMIC */\n+\tpf53-soc-thermal {\n+\t\tpolling-delay = <2000>;\n+\t\tpolling-delay-passive = <250>;\n+\t\tthermal-sensors = <&scmi_sensor 3>;\n+\n+\t\ttrips {\n+\t\t\ttrip0 {\n+\t\t\t\thysteresis = <2000>;\n+\t\t\t\ttemperature = <155000>;\n+\t\t\t\ttype = \"critical\";\n+\t\t\t};\n+\t\t};\n+\t};\n+};\n+\n+/* Verdin PWM_1 */\n+&tpm4 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pinctrl_tpm4>;\n+};\n+\n+/* Verdin PWM_2 */\n+&tpm5 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pinctrl_tpm5>;\n+};\n+\n+/* Verdin PWM_3_DSI */\n+&tpm6 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pinctrl_tpm6>;\n+};\n+\n+/* Verdin USB_1 */\n+&usb2 {\n+\tdr_mode = \"otg\";\n+\tadp-disable;\n+\thnp-disable;\n+\tsrp-disable;\n+\tusb-role-switch;\n+\tvbus-supply = <®_usb1_vbus>;\n+\n+\tport {\n+\t\tusb1_id: endpoint {\n+\t\t\tremote-endpoint = <&usb_dr_connector>;\n+\t\t};\n+\t};\n+};\n+\n+/* Verdin USB_2 */\n+&usb3 {\n+\tfsl,disable-port-power-control;\n+};\n+\n+&usb3_dwc3 {\n+\tdr_mode = \"host\";\n+};\n+\n+&usb3_phy {\n+\tvbus-supply = <®_usb2_vbus>;\n+};\n+\n+/* On-module eMMC */\n+&usdhc1 {\n+\tpinctrl-names = \"default\", \"state_100mhz\", \"state_200mhz\";\n+\tpinctrl-0 = <&pinctrl_usdhc1>;\n+\tpinctrl-1 = <&pinctrl_usdhc1>;\n+\tpinctrl-2 = <&pinctrl_usdhc1_200mhz>;\n+\tbus-width = <8>;\n+\tnon-removable;\n+\tno-sdio;\n+\tno-sd;\n+\n+\tstatus = \"okay\";\n+};\n+\n+/* Verdin SD_1 */\n+&usdhc2 {\n+\tpinctrl-names = \"default\", \"state_100mhz\", \"state_200mhz\", \"sleep\";\n+\tpinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_cd>;\n+\tpinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_cd>;\n+\tpinctrl-2 = <&pinctrl_usdhc2_200mhz>,<&pinctrl_usdhc2_cd>;\n+\tpinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_cd>;\n+\tcd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;\n+\tvmmc-supply = <®_usdhc2_vmmc>;\n+\tvqmmc-supply = <®_usdhc2_vqmmc>;\n+};\n+\n+&wdog3 {\n+\tfsl,ext-reset-output;\n+\n+\tstatus = \"okay\";\n+};\n+\n+&scmi_iomuxc {\n+\t/* On-module Bluetooth on WB SKUs, module-specific UART otherwise */\n+\tpinctrl_bt_uart: btuartgrp {\n+\t\tfsl,pins = <IMX95_PAD_GPIO_IO04__LPUART6_TX\t0x31e>, /* WiFi_UART_SoC_TXD */\n+\t\t\t <IMX95_PAD_GPIO_IO33__LPUART6_RX\t0x31e>, /* WiFi_UART_SoC_RXD */\n+\t\t\t <IMX95_PAD_GPIO_IO34__LPUART6_CTS_B\t0x31e>, /* WiFi_UART_SoC_CTS */\n+\t\t\t <IMX95_PAD_GPIO_IO07__LPUART6_RTS_B\t0x31e>; /* WiFi_UART_SoC_RTS */\n+\t};\n+\n+\t/* Verdin CSI_1_MCLK */\n+\tpinctrl_csi1_mclk: csi1mclkgrp {\n+\t\tfsl,pins = <IMX95_PAD_CCM_CLKO1__CCMSRCGPCMIX_TOP_CLKO_1\t0x51e>; /* SODIMM 91 */\n+\t};\n+\n+\t/* Verdin CTRL_SLEEP_MOCI# */\n+\tpinctrl_ctrl_sleep_moci: ctrlsleepmocigrp {\n+\t\tfsl,pins = <IMX95_PAD_SAI1_RXD0__AONMIX_TOP_GPIO1_IO_BIT14\t0x51e>; /* SODIMM 256 */\n+\t};\n+\n+\t/* Verdin CTRL_WAKE1_MICO# */\n+\tpinctrl_ctrl_wake1_mico: ctrlwake1micogrp {\n+\t\tfsl,pins = <IMX95_PAD_PDM_BIT_STREAM1__AONMIX_TOP_GPIO1_IO_BIT10\t0x31e>; /* SODIMM 252 */\n+\t};\n+\n+\t/* Verdin ETH_2_RGMII_MDIO, shared between all ethernet ports */\n+\tpinctrl_emdio: emdiogrp {\n+\t\tfsl,pins = <IMX95_PAD_ENET2_MDC__NETCMIX_TOP_NETC_MDC\t0x50e>, /* ENET2_MDC, SODIMM 193 */\n+\t\t\t <IMX95_PAD_ENET2_MDIO__NETCMIX_TOP_NETC_MDIO\t0x90e>; /* ENET2_MDIO, SODIMM 191 */\n+\t};\n+\n+\t/* Verdin ETH_1 (On-module PHY) */\n+\tpinctrl_enetc0: enetc0grp {\n+\t\tfsl,pins = <IMX95_PAD_ENET1_TX_CTL__NETCMIX_TOP_ETH0_RGMII_TX_CTL\t0x57e>, /* ENET1_TX_CTL */\n+\t\t\t <IMX95_PAD_ENET1_TXC__NETCMIX_TOP_ETH0_RGMII_TX_CLK\t\t0x58e>, /* ENET1_TXC */\n+\t\t\t <IMX95_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RGMII_TD0\t\t0x50e>, /* ENET1_TDO */\n+\t\t\t <IMX95_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RGMII_TD1\t\t0x50e>, /* ENET1_TD1 */\n+\t\t\t <IMX95_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RGMII_TD2\t\t0x50e>, /* ENET1_TD2 */\n+\t\t\t <IMX95_PAD_ENET1_TD3__NETCMIX_TOP_ETH0_RGMII_TD3\t\t0x50e>, /* ENET1_TD3 */\n+\t\t\t <IMX95_PAD_ENET1_RX_CTL__NETCMIX_TOP_ETH0_RGMII_RX_CTL\t0x57e>, /* ENET1_RX_CTL */\n+\t\t\t <IMX95_PAD_ENET1_RXC__NETCMIX_TOP_ETH0_RGMII_RX_CLK\t\t0x58e>, /* ENET1_RXC */\n+\t\t\t <IMX95_PAD_ENET1_RD0__NETCMIX_TOP_ETH0_RGMII_RD0\t\t0x57e>, /* ENET1_RD0 */\n+\t\t\t <IMX95_PAD_ENET1_RD1__NETCMIX_TOP_ETH0_RGMII_RD1\t\t0x57e>, /* ENET1_RD1 */\n+\t\t\t <IMX95_PAD_ENET1_RD2__NETCMIX_TOP_ETH0_RGMII_RD2\t\t0x57e>, /* ENET1_RD2 */\n+\t\t\t <IMX95_PAD_ENET1_RD3__NETCMIX_TOP_ETH0_RGMII_RD3\t\t0x57e>; /* ENET1_RD3 */\n+\t};\n+\n+\t/* Verdin ETH_2_RGMII */\n+\tpinctrl_enetc1: enetc1grp {\n+\t\tfsl,pins = <IMX95_PAD_ENET2_TX_CTL__NETCMIX_TOP_ETH1_RGMII_TX_CTL\t0x57e>, /* ENET2_TX_CTL */\n+\t\t\t <IMX95_PAD_ENET2_TXC__NETCMIX_TOP_ETH1_RGMII_TX_CLK\t\t0x58e>, /* ENET2_TXC */\n+\t\t\t <IMX95_PAD_ENET2_TD0__NETCMIX_TOP_ETH1_RGMII_TD0\t\t0x50e>, /* ENET2_TD0 */\n+\t\t\t <IMX95_PAD_ENET2_TD1__NETCMIX_TOP_ETH1_RGMII_TD1\t\t0x50e>, /* ENET2_TD1 */\n+\t\t\t <IMX95_PAD_ENET2_TD2__NETCMIX_TOP_ETH1_RGMII_TD2\t\t0x50e>, /* ENET2_TD2 */\n+\t\t\t <IMX95_PAD_ENET2_TD3__NETCMIX_TOP_ETH1_RGMII_TD3\t\t0x50e>, /* ENET2_TD3 */\n+\t\t\t <IMX95_PAD_ENET2_RX_CTL__NETCMIX_TOP_ETH1_RGMII_RX_CTL\t0x57e>, /* ENET2_RX_CTL */\n+\t\t\t <IMX95_PAD_ENET2_RXC__NETCMIX_TOP_ETH1_RGMII_RX_CLK\t\t0x58e>, /* ENET2_RXC */\n+\t\t\t <IMX95_PAD_ENET2_RD0__NETCMIX_TOP_ETH1_RGMII_RD0\t\t0x57e>, /* ENET2_RD0 */\n+\t\t\t <IMX95_PAD_ENET2_RD1__NETCMIX_TOP_ETH1_RGMII_RD1\t\t0x57e>, /* ENET2_RD1 */\n+\t\t\t <IMX95_PAD_ENET2_RD2__NETCMIX_TOP_ETH1_RGMII_RD2\t\t0x57e>, /* ENET2_RD2 */\n+\t\t\t <IMX95_PAD_ENET2_RD3__NETCMIX_TOP_ETH1_RGMII_RD3\t\t0x57e>; /* ENET2_RD3 */\n+\t};\n+\n+\t/* Verdin ETH_2_RGMII_INT# */\n+\tpinctrl_eth2_rgmii_int: eth2rgmiiintgrp {\n+\t\tfsl,pins = <IMX95_PAD_SAI1_TXC__AONMIX_TOP_GPIO1_IO_BIT12\t0x31e>; /* SODIMM 189 */\n+\t};\n+\n+\t/* Verdin CAN_1 */\n+\tpinctrl_flexcan1: flexcan1grp {\n+\t\tfsl,pins = <IMX95_PAD_PDM_CLK__AONMIX_TOP_CAN1_TX\t\t0x39e>, /* SODIMM 20 */\n+\t\t\t <IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_CAN1_RX\t0x39e>; /* SODIMM 22 */\n+\t};\n+\n+\t/* Verdin CAN_2 */\n+\tpinctrl_flexcan2: flexcan2grp {\n+\t\tfsl,pins = <IMX95_PAD_GPIO_IO25__CAN2_TX\t0x39e>, /* SODIMM 24 */\n+\t\t\t <IMX95_PAD_GPIO_IO27__CAN2_RX\t0x39e>; /* SODIMM 26 */\n+\t};\n+\n+\t/* Verdin QSPI_1 */\n+\tpinctrl_flexspi1: flexspi1grp {\n+\t\tfsl,pins = <IMX95_PAD_XSPI1_SS0_B__FLEXSPI1_A_SS0_B\t0x3fe>, /* SODIMM 54 */\n+\t\t\t <IMX95_PAD_XSPI1_SS1_B__FLEXSPI1_A_SS1_B\t0x3fe>, /* SODIMM 64 */\n+\t\t\t <IMX95_PAD_XSPI1_SCLK__XSPI_CLK\t\t0x3fe>, /* SODIMM 52 */\n+\t\t\t <IMX95_PAD_XSPI1_DATA0__XSPI_DATA_BIT0\t0x3fe>, /* SODIMM 56 */\n+\t\t\t <IMX95_PAD_XSPI1_DATA1__XSPI_DATA_BIT1\t0x3fe>, /* SODIMM 58 */\n+\t\t\t <IMX95_PAD_XSPI1_DATA2__XSPI_DATA_BIT2\t0x3fe>, /* SODIMM 60 */\n+\t\t\t <IMX95_PAD_XSPI1_DATA3__XSPI_DATA_BIT3\t0x3fe>, /* SODIMM 62 */\n+\t\t\t <IMX95_PAD_XSPI1_DQS__XSPI_DQS\t\t0x3fe>; /* SODIMM 66 */\n+\t};\n+\n+\t/* Verdin GPIO_1 */\n+\tpinctrl_gpio1: gpio1grp {\n+\t\tfsl,pins = <IMX95_PAD_GPIO_IO00__GPIO2_IO_BIT0\t0x51e>; /* SODIMM 206 */\n+\t};\n+\n+\t/* Verdin GPIO_2 */\n+\tpinctrl_gpio2: gpio2grp {\n+\t\tfsl,pins = <IMX95_PAD_GPIO_IO18__GPIO2_IO_BIT18\t0x51e>; /* SODIMM 208 */\n+\t};\n+\n+\t/* Verdin GPIO_3 */\n+\tpinctrl_gpio3: gpio3grp {\n+\t\tfsl,pins = <IMX95_PAD_GPIO_IO24__GPIO2_IO_BIT24\t0x51e>; /* SODIMM 210 */\n+\t};\n+\n+\t/* Verdin GPIO_4 */\n+\tpinctrl_gpio4: gpio4grp {\n+\t\tfsl,pins = <IMX95_PAD_GPIO_IO32__GPIO5_IO_BIT12\t0x51e>; /* SODIMM 212 */\n+\t};\n+\n+\t/* Verdin GPIO_5_CSI */\n+\tpinctrl_gpio5: gpio5grp {\n+\t\tfsl,pins = <IMX95_PAD_CCM_CLKO3__GPIO4_IO_BIT28\t0x51e>; /* SODIMM 216 */\n+\t};\n+\n+\t/* Verdin GPIO_6_CSI */\n+\tpinctrl_gpio6: gpio6grp {\n+\t\tfsl,pins = <IMX95_PAD_CCM_CLKO2__GPIO3_IO_BIT27\t0x51e>; /* SODIMM 218 */\n+\t};\n+\n+\t/* Verdin I2S_2_BCLK as GPIO (conflict with Verdin I2S_2) */\n+\tpinctrl_i2s_2_bclk_gpio: i2s2bclkgpiogrp {\n+\t\tfsl,pins = <IMX95_PAD_XSPI1_DATA6__GPIO5_IO_BIT6\t0x51e>; /* SODIMM 42 */\n+\t};\n+\n+\t/* Verdin I2S_2_D_IN as GPIO (conflict with Verdin I2S_2) */\n+\tpinctrl_i2s_2_d_in_gpio: i2s2dingpiogrp {\n+\t\tfsl,pins = <IMX95_PAD_XSPI1_DATA7__GPIO5_IO_BIT7\t0x31e>; /* SODIMM 48 */\n+\t};\n+\n+\t/* Verdin I2S_2_D_OUT as GPIO (conflict with Verdin I2S_2) */\n+\tpinctrl_i2s_2_d_out_gpio: i2s2doutgpiogrp {\n+\t\tfsl,pins = <IMX95_PAD_XSPI1_DATA4__GPIO5_IO_BIT4\t0x51e>; /* SODIMM 46 */\n+\t};\n+\n+\t/* Verdin I2S_2_SYNC as GPIO (conflict with Verdin I2S_2) */\n+\tpinctrl_i2s_2_sync_gpio: i2s2syncgpiogrp {\n+\t\tfsl,pins = <IMX95_PAD_XSPI1_DATA5__GPIO5_IO_BIT5\t0x51e>; /* SODIMM 44 */\n+\t};\n+\n+\t/* Verdin I2C_3_HDMI */\n+\tpinctrl_i3c2: i3c2cgrp {\n+\t\tfsl,pins = <IMX95_PAD_ENET1_MDC__I3C2_SCL\t0x40001186>, /* SODIMM 59 */\n+\t\t\t <IMX95_PAD_ENET1_MDIO__I3C2_SDA\t0x40001186>; /* SODIMM 57 */\n+\t};\n+\n+\tpinctrl_io_exp_int: ioexpintgrp {\n+\t\tfsl,pins = <IMX95_PAD_SAI1_TXD0__AONMIX_TOP_GPIO1_IO_BIT13\t0x31e>; /* IO_EXP_INT */\n+\t};\n+\n+\t/* CTRL_I2C (On-module I2C) */\n+\tpinctrl_lpi2c2_gpio: lpi2c2gpiogrp {\n+\t\tfsl,pins = <IMX95_PAD_I2C2_SCL__AONMIX_TOP_GPIO1_IO_BIT2\t0x40001b9e>, /* CTRL_I2C_SCL */\n+\t\t\t <IMX95_PAD_I2C2_SDA__AONMIX_TOP_GPIO1_IO_BIT3\t0x40001b9e>; /* CTRL_I2C_SDA */\n+\t};\n+\n+\tpinctrl_lpi2c2: lpi2c2grp {\n+\t\tfsl,pins = <IMX95_PAD_I2C2_SCL__AONMIX_TOP_LPI2C2_SCL\t0x40001b9e>, /* CTRL_I2C_SCL */\n+\t\t\t <IMX95_PAD_I2C2_SDA__AONMIX_TOP_LPI2C2_SDA\t0x40001b9e>; /* CTRL_I2C_SDA */\n+\t};\n+\n+\t/* Verdin I2C_2_DSI */\n+\tpinctrl_lpi2c3_gpio: lpi2c3gpiogrp {\n+\t\tfsl,pins = <IMX95_PAD_GPIO_IO28__GPIO2_IO_BIT28\t0x40001b9e>, /* SODIMM 53 */\n+\t\t\t <IMX95_PAD_GPIO_IO29__GPIO2_IO_BIT29\t0x40001b9e>; /* SODIMM 55 */\n+\t};\n+\n+\tpinctrl_lpi2c3: lpi2c3grp {\n+\t\tfsl,pins = <IMX95_PAD_GPIO_IO28__LPI2C3_SDA\t0x40001b9e>, /* SODIMM 53 */\n+\t\t\t <IMX95_PAD_GPIO_IO29__LPI2C3_SCL\t0x40001b9e>; /* SODIMM 55 */\n+\t};\n+\n+\t/* Verdin I2C_1 */\n+\tpinctrl_lpi2c4_gpio: lpi2c4gpiogrp {\n+\t\tfsl,pins = <IMX95_PAD_GPIO_IO31__GPIO2_IO_BIT31\t0x40001b9e>, /* SODIMM 14 */\n+\t\t\t <IMX95_PAD_GPIO_IO30__GPIO2_IO_BIT30\t0x40001b9e>; /* SODIMM 12 */\n+\t};\n+\n+\tpinctrl_lpi2c4: lpi2c4grp {\n+\t\tfsl,pins = <IMX95_PAD_GPIO_IO31__LPI2C4_SCL\t0x40001b9e>, /* SODIMM 14 */\n+\t\t\t <IMX95_PAD_GPIO_IO30__LPI2C4_SDA\t0x40001b9e>; /* SODIMM 12 */\n+\t};\n+\n+\t/* Verdin I2C_4_CSI */\n+\tpinctrl_lpi2c5_gpio: lpi2c5gpiogrp {\n+\t\tfsl,pins = <IMX95_PAD_GPIO_IO22__GPIO2_IO_BIT22\t0x40001b9e>, /* SODIMM 93 */\n+\t\t\t <IMX95_PAD_GPIO_IO23__GPIO2_IO_BIT23\t0x40001b9e>; /* SODIMM 95 */\n+\t};\n+\n+\tpinctrl_lpi2c5: lpi2c5grp {\n+\t\tfsl,pins = <IMX95_PAD_GPIO_IO22__LPI2C5_SDA\t0x40001b9e>, /* SODIMM 93 */\n+\t\t\t <IMX95_PAD_GPIO_IO23__LPI2C5_SCL\t0x40001b9e>; /* SODIMM 95 */\n+\t};\n+\n+\t/* Verdin SPI_1 */\n+\tpinctrl_lpspi6: lpspi6grp {\n+\t\tfsl,pins = <IMX95_PAD_GPIO_IO01__LPSPI6_SIN\t0x3fe>, /* SODIMM 198 */\n+\t\t\t <IMX95_PAD_GPIO_IO02__LPSPI6_SOUT\t0x3fe>, /* SODIMM 200 */\n+\t\t\t <IMX95_PAD_GPIO_IO03__LPSPI6_SCK\t0x3fe>; /* SODIMM 196 */\n+\t};\n+\n+\t/* Verdin QSPI_1_CLK as GPIO (conflict with Verdin QSPI_1 interface) */\n+\tpinctrl_qspi1_clk_gpio: qspi1clkgpiogrp {\n+\t\tfsl,pins = <IMX95_PAD_XSPI1_SCLK__GPIO5_IO_BIT9\t\t0x11e>; /* SODIMM 52 */\n+\t};\n+\n+\t/* Verdin QSPI_1_CS2# as GPIO (conflict with Verdin QSPI_1 interface) */\n+\tpinctrl_qspi1_cs2_gpio: qspi1cs2gpiogrp {\n+\t\tfsl,pins = <IMX95_PAD_XSPI1_SS1_B__GPIO5_IO_BIT11\t0x11e>; /* SODIMM 64 */\n+\t};\n+\n+\t/* Verdin QSPI_1_CS# as GPIO (conflict with Verdin QSPI_1 interface) */\n+\tpinctrl_qspi1_cs_gpio: qspi1csgpiogrp {\n+\t\tfsl,pins = <IMX95_PAD_XSPI1_SS0_B__GPIO5_IO_BIT10\t0x11e>; /* SODIMM 54 */\n+\t};\n+\n+\t/* Verdin QSPI_1_DQS as GPIO (conflict with Verdin QSPI_1 interface) */\n+\tpinctrl_qspi1_dqs_gpio: qspi1dqsgpiogrp {\n+\t\tfsl,pins = <IMX95_PAD_XSPI1_DQS__GPIO5_IO_BIT8\t\t0x11e>; /* SODIMM 66 */\n+\t};\n+\n+\t/* Verdin QSPI_1_IO0 as GPIO (conflict with Verdin QSPI_1 interface) */\n+\tpinctrl_qspi1_io0_gpio: qspi1io0gpiogrp {\n+\t\tfsl,pins = <IMX95_PAD_XSPI1_DATA0__GPIO5_IO_BIT0\t0x119e>; /* SODIMM 56 */\n+\t};\n+\n+\t/* Verdin QSPI_1_IO1 as GPIO (conflict with Verdin QSPI_1 interface) */\n+\tpinctrl_qspi1_io1_gpio: qspi1io1gpiogrp {\n+\t\tfsl,pins = <IMX95_PAD_XSPI1_DATA1__GPIO5_IO_BIT1\t0x119e>; /* SODIMM 58 */\n+\t};\n+\n+\t/* Verdin QSPI_1_IO2 as GPIO (conflict with Verdin QSPI_1 interface) */\n+\tpinctrl_qspi1_io2_gpio: qspi1io2gpiogrp {\n+\t\tfsl,pins = <IMX95_PAD_XSPI1_DATA2__GPIO5_IO_BIT2\t0x11e>; /* SODIMM 60 */\n+\t};\n+\n+\t/* Verdin QSPI_1_IO3 as GPIO (conflict with Verdin QSPI_1 interface) */\n+\tpinctrl_qspi1_io3_gpio: qspi1io3gpiogrp {\n+\t\tfsl,pins = <IMX95_PAD_XSPI1_DATA3__GPIO5_IO_BIT3\t0x11e>; /* SODIMM 62 */\n+\t};\n+\n+\t/* Verdin I2S_1 */\n+\tpinctrl_sai3: sai3grp {\n+\t\tfsl,pins = <IMX95_PAD_GPIO_IO16__SAI3_TX_BCLK\t\t0x11e>, /* SODIMM 30 */\n+\t\t\t <IMX95_PAD_GPIO_IO20__SAI3_RX_DATA_BIT0\t0x11e>, /* SODIMM 36 */\n+\t\t\t <IMX95_PAD_GPIO_IO21__SAI3_TX_DATA_BIT0\t0x11e>, /* SODIMM 34 */\n+\t\t\t <IMX95_PAD_GPIO_IO26__SAI3_TX_SYNC\t\t0x11e>; /* SODIMM 32 */\n+\t};\n+\n+\t/* Verdin I2S_1_MCLK */\n+\tpinctrl_sai3_mclk: sai3mclkgrp {\n+\t\tfsl,pins = <IMX95_PAD_GPIO_IO17__SAI3_MCLK\t0x31e>; /* SODIMM 38 */\n+\t};\n+\n+\t/* Verdin I2S_2 */\n+\tpinctrl_sai5: sai5grp {\n+\t\tfsl,pins = <IMX95_PAD_XSPI1_DATA4__SAI5_TX_DATA_BIT0\t0x11e>, /* SODIMM 46 */\n+\t\t\t <IMX95_PAD_XSPI1_DATA5__SAI5_TX_SYNC\t\t0x11e>, /* SODIMM 44 */\n+\t\t\t <IMX95_PAD_XSPI1_DATA6__SAI5_TX_BCLK\t\t0x11e>, /* SODIMM 42 */\n+\t\t\t <IMX95_PAD_XSPI1_DATA7__SAI5_RX_DATA_BIT0\t0x11e>; /* SODIMM 48 */\n+\t};\n+\n+\t/* Verdin SPI_1_CS */\n+\tpinctrl_spi1_cs: spi1csgrp {\n+\t\tfsl,pins = <IMX95_PAD_CCM_CLKO4__GPIO4_IO_BIT29\t0x3fe>; /* SODIMM 202 */\n+\t};\n+\n+\t/* Verdin PWM_1 */\n+\tpinctrl_tpm4: tpm4grp {\n+\t\tfsl,pins = <IMX95_PAD_GPIO_IO05__TPM4_CH0\t0x11e>; /* SODIMM 15 */\n+\t};\n+\n+\t/* Verdin PWM_2 */\n+\tpinctrl_tpm5: tpm5grp {\n+\t\tfsl,pins = <IMX95_PAD_GPIO_IO06__TPM5_CH0\t0x11e>; /* SODIMM 16 */\n+\t};\n+\n+\t/* Verdin PWM_3_DSI as GPIO */\n+\tpinctrl_tpm6_gpio: tpm6gpiogrp {\n+\t\tfsl,pins = <IMX95_PAD_GPIO_IO19__GPIO2_IO_BIT19\t0x51e>; /* SODIMM 19 */\n+\t};\n+\n+\t/* Verdin PWM_3_DSI */\n+\tpinctrl_tpm6: tpm6grp {\n+\t\tfsl,pins = <IMX95_PAD_GPIO_IO19__TPM6_CH2\t0x11e>; /* SODIMM 19 */\n+\t};\n+\n+\t/* Verdin UART_3, used as the Linux Console */\n+\tpinctrl_uart1: uart1grp {\n+\t\tfsl,pins = <IMX95_PAD_UART1_RXD__AONMIX_TOP_LPUART1_RX\t0x31e>, /* SODIMM 147 */\n+\t\t\t <IMX95_PAD_UART1_TXD__AONMIX_TOP_LPUART1_TX\t0x31e>; /* SODIMM 149 */\n+\t};\n+\n+\t/* Verdin UART_4 */\n+\tpinctrl_uart2: uart2grp {\n+\t\tfsl,pins = <IMX95_PAD_UART2_RXD__AONMIX_TOP_LPUART2_RX\t0x31e>, /* SODIMM 151 */\n+\t\t\t <IMX95_PAD_UART2_TXD__AONMIX_TOP_LPUART2_TX\t0x31e>; /* SODIMM 153 */\n+\t};\n+\n+\t/* Verdin UART_1 */\n+\tpinctrl_uart7: uart7grp {\n+\t\tfsl,pins = <IMX95_PAD_GPIO_IO08__LPUART7_TX\t0x31e>, /* SODIMM 131 */\n+\t\t\t <IMX95_PAD_GPIO_IO09__LPUART7_RX\t0x31e>, /* SODIMM 129 */\n+\t\t\t <IMX95_PAD_GPIO_IO10__LPUART7_CTS_B\t0x31e>, /* SODIMM 135 */\n+\t\t\t <IMX95_PAD_GPIO_IO11__LPUART7_RTS_B\t0x31e>; /* SODIMM 133 */\n+\t};\n+\n+\t/* Verdin UART_2 CTS */\n+\tpinctrl_uart8_cts: uart8ctsgrp {\n+\t\tfsl,pins = <IMX95_PAD_GPIO_IO14__LPUART8_CTS_B\t0x31e>; /* SODIMM 143 */\n+\t};\n+\n+\t/* Verdin UART_2 RTS */\n+\tpinctrl_uart8_rts: uart8rtsgrp {\n+\t\tfsl,pins = <IMX95_PAD_GPIO_IO15__LPUART8_RTS_B\t0x31e>; /* SODIMM 141 */\n+\t};\n+\n+\t/* Verdin UART_2 RX/TX */\n+\tpinctrl_uart8: uart8grp {\n+\t\tfsl,pins = <IMX95_PAD_GPIO_IO12__LPUART8_TX\t0x31e>, /* SODIMM 139 */\n+\t\t\t <IMX95_PAD_GPIO_IO13__LPUART8_RX\t0x31e>; /* SODIMM 137 */\n+\t};\n+\n+\t/* On-module eMMC */\n+\tpinctrl_usdhc1: usdhc1grp {\n+\t\tfsl,pins = <IMX95_PAD_SD1_CLK__USDHC1_CLK\t0x158e>, /* SD1_CLK */\n+\t\t\t <IMX95_PAD_SD1_CMD__USDHC1_CMD\t0x138e>, /* SD1_CMD */\n+\t\t\t <IMX95_PAD_SD1_DATA0__USDHC1_DATA0\t0x138e>, /* SD1_DATA0 */\n+\t\t\t <IMX95_PAD_SD1_DATA1__USDHC1_DATA1\t0x138e>, /* SD1_DATA1 */\n+\t\t\t <IMX95_PAD_SD1_DATA2__USDHC1_DATA2\t0x138e>, /* SD1_DATA2 */\n+\t\t\t <IMX95_PAD_SD1_DATA3__USDHC1_DATA3\t0x138e>, /* SD1_DATA3 */\n+\t\t\t <IMX95_PAD_SD1_DATA4__USDHC1_DATA4\t0x138e>, /* SD1_DATA4 */\n+\t\t\t <IMX95_PAD_SD1_DATA5__USDHC1_DATA5\t0x138e>, /* SD1_DATA5 */\n+\t\t\t <IMX95_PAD_SD1_DATA6__USDHC1_DATA6\t0x138e>, /* SD1_DATA6 */\n+\t\t\t <IMX95_PAD_SD1_DATA7__USDHC1_DATA7\t0x138e>, /* SD1_DATA7 */\n+\t\t\t <IMX95_PAD_SD1_STROBE__USDHC1_STROBE\t0x158e>; /* SD1_STROBE */\n+\t};\n+\n+\tpinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {\n+\t\tfsl,pins = <IMX95_PAD_SD1_CLK__USDHC1_CLK\t0x15fe>, /* SD1_CLK */\n+\t\t\t <IMX95_PAD_SD1_CMD__USDHC1_CMD\t0x13fe>, /* SD1_CMD */\n+\t\t\t <IMX95_PAD_SD1_DATA0__USDHC1_DATA0\t0x13fe>, /* SD1_DATA0 */\n+\t\t\t <IMX95_PAD_SD1_DATA1__USDHC1_DATA1\t0x13fe>, /* SD1_DATA1 */\n+\t\t\t <IMX95_PAD_SD1_DATA2__USDHC1_DATA2\t0x13fe>, /* SD1_DATA2 */\n+\t\t\t <IMX95_PAD_SD1_DATA3__USDHC1_DATA3\t0x13fe>, /* SD1_DATA3 */\n+\t\t\t <IMX95_PAD_SD1_DATA4__USDHC1_DATA4\t0x13fe>, /* SD1_DATA4 */\n+\t\t\t <IMX95_PAD_SD1_DATA5__USDHC1_DATA5\t0x13fe>, /* SD1_DATA5 */\n+\t\t\t <IMX95_PAD_SD1_DATA6__USDHC1_DATA6\t0x13fe>, /* SD1_DATA6 */\n+\t\t\t <IMX95_PAD_SD1_DATA7__USDHC1_DATA7\t0x13fe>, /* SD1_DATA7 */\n+\t\t\t <IMX95_PAD_SD1_STROBE__USDHC1_STROBE\t0x15fe>; /* SD1_STROBE */\n+\t};\n+\n+\t/* Verdin SD_1 */\n+\tpinctrl_usdhc2: usdhc2grp {\n+\t\tfsl,pins = <IMX95_PAD_SD2_CLK__USDHC2_CLK\t0x158e>, /* SODIMM 78 */\n+\t\t\t <IMX95_PAD_SD2_CMD__USDHC2_CMD\t0x138e>, /* SODIMM 74 */\n+\t\t\t <IMX95_PAD_SD2_DATA0__USDHC2_DATA0\t0x138e>, /* SODIMM 80 */\n+\t\t\t <IMX95_PAD_SD2_DATA1__USDHC2_DATA1\t0x138e>, /* SODIMM 82 */\n+\t\t\t <IMX95_PAD_SD2_DATA2__USDHC2_DATA2\t0x138e>, /* SODIMM 70 */\n+\t\t\t <IMX95_PAD_SD2_DATA3__USDHC2_DATA3\t0x138e>; /* SODIMM 72 */\n+\t};\n+\n+\tpinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {\n+\t\tfsl,pins = <IMX95_PAD_SD2_CLK__USDHC2_CLK\t0x15fe>, /* SODIMM 78 */\n+\t\t\t <IMX95_PAD_SD2_CMD__USDHC2_CMD\t0x13fe>, /* SODIMM 74 */\n+\t\t\t <IMX95_PAD_SD2_DATA0__USDHC2_DATA0\t0x13fe>, /* SODIMM 80 */\n+\t\t\t <IMX95_PAD_SD2_DATA1__USDHC2_DATA1\t0x13fe>, /* SODIMM 82 */\n+\t\t\t <IMX95_PAD_SD2_DATA2__USDHC2_DATA2\t0x13fe>, /* SODIMM 70 */\n+\t\t\t <IMX95_PAD_SD2_DATA3__USDHC2_DATA3\t0x13fe>; /* SODIMM 72 */\n+\t};\n+\n+\tpinctrl_usdhc2_sleep: usdhc2-sleepgrp {\n+\t\tfsl,pins = <IMX95_PAD_SD2_CLK__USDHC2_CLK\t0x400>, /* SODIMM 78 */\n+\t\t\t <IMX95_PAD_SD2_CMD__USDHC2_CMD\t0x400>, /* SODIMM 74 */\n+\t\t\t <IMX95_PAD_SD2_DATA0__USDHC2_DATA0\t0x400>, /* SODIMM 80 */\n+\t\t\t <IMX95_PAD_SD2_DATA1__USDHC2_DATA1\t0x400>, /* SODIMM 82 */\n+\t\t\t <IMX95_PAD_SD2_DATA2__USDHC2_DATA2\t0x400>, /* SODIMM 70 */\n+\t\t\t <IMX95_PAD_SD2_DATA3__USDHC2_DATA3\t0x400>; /* SODIMM 72 */\n+\t};\n+\n+\t/* Verdin SD_1_CD# */\n+\tpinctrl_usdhc2_cd: usdhc2-cdgrp {\n+\t\tfsl,pins = <IMX95_PAD_SD2_CD_B__GPIO3_IO_BIT0\t0x1100>; /* SODIMM 84 */\n+\t};\n+\n+\t/* Verdin SD_1_PWR_EN */\n+\tpinctrl_usdhc2_pwr_en: usdhc2-pwrengrp {\n+\t\tfsl,pins = <IMX95_PAD_SD2_RESET_B__GPIO3_IO_BIT7\t0x11e>; /* SODIMM 76 */\n+\t};\n+\n+\tpinctrl_usdhc2_vsel: usdhc2-vselgrp {\n+\t\tfsl,pins = <IMX95_PAD_SD2_VSELECT__GPIO3_IO_BIT19\t0x4>; /* PMIC_SD2_VSEL */\n+\t};\n+\n+\t/* On-module Wi-Fi on WB SKUs, module-specific SDIO otherwise */\n+\tpinctrl_usdhc3: usdhc3grp {\n+\t\tfsl,pins = <IMX95_PAD_SD3_CLK__USDHC3_CLK\t0x158e>, /* SD3_CLK */\n+\t\t\t <IMX95_PAD_SD3_CMD__USDHC3_CMD\t0x138e>, /* SD3_CMD */\n+\t\t\t <IMX95_PAD_SD3_DATA0__USDHC3_DATA0\t0x138e>, /* SD3_DATA0 */\n+\t\t\t <IMX95_PAD_SD3_DATA1__USDHC3_DATA1\t0x138e>, /* SD3_DATA1 */\n+\t\t\t <IMX95_PAD_SD3_DATA2__USDHC3_DATA2\t0x138e>, /* SD3_DATA2 */\n+\t\t\t <IMX95_PAD_SD3_DATA3__USDHC3_DATA3\t0x138e>; /* SD3_DATA3 */\n+\t};\n+\n+\tpinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {\n+\t\tfsl,pins = <IMX95_PAD_SD3_CLK__USDHC3_CLK\t0x15fe>, /* SD3_CLK */\n+\t\t\t <IMX95_PAD_SD3_CMD__USDHC3_CMD\t0x13fe>, /* SD3_CMD */\n+\t\t\t <IMX95_PAD_SD3_DATA0__USDHC3_DATA0\t0x13fe>, /* SD3_DATA1 */\n+\t\t\t <IMX95_PAD_SD3_DATA1__USDHC3_DATA1\t0x13fe>, /* SD3_DATA2 */\n+\t\t\t <IMX95_PAD_SD3_DATA2__USDHC3_DATA2\t0x13fe>, /* SD3_DATA3 */\n+\t\t\t <IMX95_PAD_SD3_DATA3__USDHC3_DATA3\t0x13fe>; /* SD3_DATA4 */\n+\t};\n+\n+\tpinctrl_wifi_pwr_en: wifipwrengrp {\n+\t\tfsl,pins = <IMX95_PAD_SAI1_TXFS__AONMIX_TOP_GPIO1_IO_BIT11\t0x51e>; /* PMIC_EN_WIFI */\n+\t};\n+};\ndiff --git a/arch/arm/mach-imx/imx9/Kconfig b/arch/arm/mach-imx/imx9/Kconfig\nindex 2308457df23e..27e887213a8c 100644\n--- a/arch/arm/mach-imx/imx9/Kconfig\n+++ b/arch/arm/mach-imx/imx9/Kconfig\n@@ -171,6 +171,10 @@ config TARGET_TORADEX_SMARC_IMX95\n \tselect IMX95\n \timply OF_UPSTREAM\n \n+config TARGET_VERDIN_IMX95\n+\tbool \"Support Toradex Verdin iMX95 module\"\n+\tselect IMX95\n+\n config TARGET_IMX952_EVK\n \tbool \"imx952_evk\"\n \tselect IMX_SM_CPU\n@@ -195,6 +199,7 @@ source \"board/variscite/imx93_var_som/Kconfig\"\n source \"board/nxp/imx94_evk/Kconfig\"\n source \"board/nxp/imx95_evk/Kconfig\"\n source \"board/toradex/smarc-imx95/Kconfig\"\n+source \"board/toradex/verdin-imx95/Kconfig\"\n source \"board/nxp/imx952_evk/Kconfig\"\n \n endif\ndiff --git a/board/toradex/verdin-imx95/Kconfig b/board/toradex/verdin-imx95/Kconfig\nnew file mode 100644\nindex 000000000000..ef4206c343c0\n--- /dev/null\n+++ b/board/toradex/verdin-imx95/Kconfig\n@@ -0,0 +1,36 @@\n+if TARGET_VERDIN_IMX95\n+\n+config SYS_BOARD\n+\tdefault \"verdin-imx95\"\n+\n+config SYS_VENDOR\n+\tdefault \"toradex\"\n+\n+config SYS_CONFIG_NAME\n+\tdefault \"verdin-imx95\"\n+\n+config TDX_CFG_BLOCK\n+\tdefault y\n+\n+config TDX_CFG_BLOCK_2ND_ETHADDR\n+\tdefault y\n+\n+config TDX_CFG_BLOCK_DEV\n+\tdefault \"0\"\n+\n+# Toradex config block in eMMC, at the end of 1st \"boot sector\"\n+config TDX_CFG_BLOCK_OFFSET\n+\tdefault \"-512\"\n+\n+config TDX_CFG_BLOCK_PART\n+\tdefault \"1\"\n+\n+config TDX_HAVE_EEPROM_EXTRA\n+\tdefault y\n+\n+config TDX_HAVE_MMC\n+\tdefault y\n+\n+source \"board/toradex/common/Kconfig\"\n+\n+endif\ndiff --git a/board/toradex/verdin-imx95/MAINTAINERS b/board/toradex/verdin-imx95/MAINTAINERS\nnew file mode 100644\nindex 000000000000..d19ee3ebfe5d\n--- /dev/null\n+++ b/board/toradex/verdin-imx95/MAINTAINERS\n@@ -0,0 +1,13 @@\n+Verdin iMX95\n+F:\tarch/arm/dts/imx95-verdin.dtsi\n+F:\tarch/arm/dts/imx95-verdin-dev.dtsi\n+F:\tarch/arm/dts/imx95-verdin-wifi.dtsi\n+F:\tarch/arm/dts/imx95-verdin-wifi-dev.dts\n+F:\tarch/arm/dts/imx95-verdin-wifi-dev-u-boot.dtsi\n+F:\tboard/toradex/verdin-imx95/\n+F:\tconfigs/verdin-imx95_defconfig\n+F:\tdoc/board/toradex/verdin-imx95.rst\n+F:\tinclude/configs/verdin-imx95.h\n+M:\tFrancesco Dolcini <francesco.dolcini@toradex.com>\n+S:\tMaintained\n+W:\thttps://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx95\ndiff --git a/board/toradex/verdin-imx95/Makefile b/board/toradex/verdin-imx95/Makefile\nnew file mode 100644\nindex 000000000000..bc1b6811bbec\n--- /dev/null\n+++ b/board/toradex/verdin-imx95/Makefile\n@@ -0,0 +1,8 @@\n+# SPDX-License-Identifier: GPL-2.0-or-later\n+# Copyright (c) Toradex\n+\n+obj-y += verdin-imx95.o\n+\n+ifdef CONFIG_SPL_BUILD\n+obj-y += spl.o\n+endif\ndiff --git a/board/toradex/verdin-imx95/spl.c b/board/toradex/verdin-imx95/spl.c\nnew file mode 100644\nindex 000000000000..9f501c11c1d8\n--- /dev/null\n+++ b/board/toradex/verdin-imx95/spl.c\n@@ -0,0 +1,75 @@\n+// SPDX-License-Identifier: GPL-2.0-or-later\n+/* Copyright (c) Toradex */\n+\n+#include <asm/arch/clock.h>\n+#include <asm/arch/mu.h>\n+#include <asm/arch/sys_proto.h>\n+#include <asm/mach-imx/boot_mode.h>\n+#include <asm/mach-imx/ele_api.h>\n+#include <asm/sections.h>\n+#include <asm/global_data.h>\n+#include <clk.h>\n+#include <dm/uclass.h>\n+#include <hang.h>\n+#include <i2c.h>\n+#include <init.h>\n+#include <spl.h>\n+\n+DECLARE_GLOBAL_DATA_PTR;\n+\n+int spl_board_boot_device(enum boot_device boot_dev_spl)\n+{\n+\tswitch (boot_dev_spl) {\n+\tcase SD1_BOOT:\n+\tcase MMC1_BOOT:\n+\t\treturn BOOT_DEVICE_MMC1;\n+\tcase SD2_BOOT:\n+\tcase MMC2_BOOT:\n+\t\treturn BOOT_DEVICE_MMC2;\n+\tcase USB_BOOT:\n+\t\treturn BOOT_DEVICE_BOARD;\n+\tdefault:\n+\t\treturn BOOT_DEVICE_NONE;\n+\t}\n+}\n+\n+void spl_board_init(void)\n+{\n+\tint ret;\n+\n+\tret = ele_start_rng();\n+\tif (ret)\n+\t\tprintf(\"Fail to start RNG: %d\\n\", ret);\n+}\n+\n+void board_init_f(ulong dummy)\n+{\n+\tint ret;\n+\n+\t/* Clear the BSS. */\n+\tmemset(__bss_start, 0, __bss_end - __bss_start);\n+\n+\tif (IS_ENABLED(CONFIG_SPL_RECOVER_DATA_SECTION))\n+\t\tspl_save_restore_data();\n+\n+\ttimer_init();\n+\n+\t/* Need dm_init() to run before any SCMI calls */\n+\tspl_early_init();\n+\n+\t/* Need to enable SCMI drivers and ELE driver before console */\n+\tret = imx9_probe_mu();\n+\tif (ret)\n+\t\thang(); /* MU not probed, nothing can be outputed, hang */\n+\n+\tarch_cpu_init();\n+\n+\tpreloader_console_init();\n+\n+\tdebug(\"SOC: 0x%x\\n\", gd->arch.soc_rev);\n+\tdebug(\"LC: 0x%x\\n\", gd->arch.lifecycle);\n+\n+\tget_reset_reason(true, false);\n+\n+\tboard_init_r(NULL, 0);\n+}\ndiff --git a/board/toradex/verdin-imx95/verdin-imx95.c b/board/toradex/verdin-imx95/verdin-imx95.c\nnew file mode 100644\nindex 000000000000..36e41ec3ad4a\n--- /dev/null\n+++ b/board/toradex/verdin-imx95/verdin-imx95.c\n@@ -0,0 +1,79 @@\n+// SPDX-License-Identifier: GPL-2.0-or-later\n+/* Copyright (c) Toradex */\n+\n+#include <asm/arch/clock.h>\n+#include <asm/arch/sys_proto.h>\n+#include <env.h>\n+#include <errno.h>\n+#include <fdt_support.h>\n+#include <init.h>\n+#include <stdio.h>\n+#include <string.h>\n+\n+#include \"../common/tdx-cfg-block.h\"\n+#include \"../common/tdx-common.h\"\n+\n+DECLARE_GLOBAL_DATA_PTR;\n+\n+static void select_dt_from_module_version(void)\n+{\n+\tchar variant[32];\n+\tchar *env_variant = env_get(\"variant\");\n+\tbool is_wifi = false;\n+\n+\tif (IS_ENABLED(CONFIG_TDX_CFG_BLOCK)) {\n+\t\t/*\n+\t\t * If we have a valid config block and it says we are a\n+\t\t * module with Wi-Fi/Bluetooth make sure we use the -wifi\n+\t\t * device tree.\n+\t\t */\n+\t\tis_wifi = (tdx_hw_tag.prodid == VERDIN_IMX95H_8G_WIFI_BT_IT);\n+\t}\n+\n+\tif (is_wifi)\n+\t\tstrlcpy(&variant[0], \"wifi\", sizeof(variant));\n+\telse\n+\t\tstrlcpy(&variant[0], \"nonwifi\", sizeof(variant));\n+\n+\tif (!env_variant || strcmp(variant, env_variant)) {\n+\t\tprintf(\"Setting variant to %s\\n\", variant);\n+\t\tenv_set(\"variant\", variant);\n+\t}\n+}\n+\n+int board_late_init(void)\n+{\n+\tselect_dt_from_module_version();\n+\n+\treturn 0;\n+}\n+\n+static const struct ram_alias_check ram_alias_checks[] = {\n+\t{ (void *)(PHYS_SDRAM + SZ_8G), (void *)(PHYS_SDRAM), SZ_16G },\n+\t{ (void *)(PHYS_SDRAM + SZ_4G), (void *)(PHYS_SDRAM), SZ_8G },\n+\t{ (void *)(PHYS_SDRAM + SZ_2G), (void *)(PHYS_SDRAM), SZ_4G },\n+\t{ (void *)(PHYS_SDRAM + SZ_1G), (void *)(PHYS_SDRAM), SZ_2G },\n+\t{ NULL }\n+};\n+\n+int board_phys_sdram_size(phys_size_t *size)\n+{\n+\tphys_size_t sz;\n+\n+\tsz = probe_ram_size_by_alias(ram_alias_checks);\n+\tif (!sz) {\n+\t\tputs(\"## WARNING: Less than 2GB RAM detected\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\t*size = sz - PHYS_SDRAM_FW_RSVD;\n+\n+\treturn 0;\n+}\n+\n+#if IS_ENABLED(CONFIG_OF_LIBFDT) && IS_ENABLED(CONFIG_OF_BOARD_SETUP)\n+int ft_board_setup(void *blob, struct bd_info *bd)\n+{\n+\treturn ft_common_board_setup(blob, bd);\n+}\n+#endif\ndiff --git a/board/toradex/verdin-imx95/verdin-imx95.env b/board/toradex/verdin-imx95/verdin-imx95.env\nnew file mode 100644\nindex 000000000000..5ca6cb18aaaa\n--- /dev/null\n+++ b/board/toradex/verdin-imx95/verdin-imx95.env\n@@ -0,0 +1,20 @@\n+boot_scripts=boot.scr\n+boot_script_dhcp=boot.scr\n+boot_targets=mmc1 mmc0 dhcp\n+console=ttyLP2\n+fdt_board=dev\n+fdt_addr=0x9c400000\n+fdt_addr_r=0x9c400000\n+kernel_addr_r=CONFIG_SYS_LOAD_ADDR\n+kernel_comp_addr_r=0x94400000\n+kernel_comp_size=0x8000000\n+ramdisk_addr_r=0x9c800000\n+scriptaddr=0x9c600000\n+\n+update_uboot=\n+\t\taskenv confirm Did you load flash.bin (y/N)?;\n+\t\tif test \"$confirm\" = y; then\n+\t\t\tsetexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt\n+\t\t\t${blkcnt} / 0x200; mmc dev 0 1; mmc write ${loadaddr} 0x0\n+\t\t\t${blkcnt};\n+\t\tfi\ndiff --git a/configs/verdin-imx95_defconfig b/configs/verdin-imx95_defconfig\nnew file mode 100644\nindex 000000000000..6dbf921e64be\n--- /dev/null\n+++ b/configs/verdin-imx95_defconfig\n@@ -0,0 +1,183 @@\n+CONFIG_ARM=y\n+CONFIG_ARCH_IMX9=y\n+CONFIG_TEXT_BASE=0x90200000\n+CONFIG_SYS_MALLOC_LEN=0x2000000\n+CONFIG_SYS_MALLOC_F_LEN=0x10000\n+CONFIG_SPL_GPIO=y\n+CONFIG_SPL_LIBCOMMON_SUPPORT=y\n+CONFIG_SPL_LIBGENERIC_SUPPORT=y\n+CONFIG_NR_DRAM_BANKS=3\n+CONFIG_ENV_SIZE=0x2000\n+CONFIG_ENV_OFFSET=0xFFFFDE00\n+CONFIG_DM_GPIO=y\n+CONFIG_DEFAULT_DEVICE_TREE=\"imx95-verdin-wifi-dev\"\n+CONFIG_TARGET_VERDIN_IMX95=y\n+CONFIG_OF_LIBFDT_OVERLAY=y\n+CONFIG_SYS_MONITOR_LEN=524288\n+CONFIG_SPL_MMC=y\n+CONFIG_SPL_SERIAL=y\n+CONFIG_SPL_DRIVERS_MISC=y\n+CONFIG_SPL_STACK=0x204d6000\n+CONFIG_SPL_TEXT_BASE=0x20480000\n+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y\n+CONFIG_SPL_BSS_START_ADDR=0x204d6000\n+CONFIG_SPL_BSS_MAX_SIZE=0x2000\n+CONFIG_SYS_LOAD_ADDR=0x90400000\n+CONFIG_WATCHDOG_TIMEOUT_MSECS=30000\n+CONFIG_SPL=y\n+CONFIG_SPL_RECOVER_DATA_SECTION=y\n+CONFIG_PCI=y\n+CONFIG_SYS_MEMTEST_START=0x90000000\n+CONFIG_SYS_MEMTEST_END=0xA0000000\n+CONFIG_REMAKE_ELF=y\n+CONFIG_FIT=y\n+CONFIG_FIT_VERBOSE=y\n+CONFIG_BOOTSTD_FULL=y\n+CONFIG_BOOTDELAY=1\n+CONFIG_OF_SYSTEM_SETUP=y\n+CONFIG_BOOTCOMMAND=\"bootflow scan -b\"\n+CONFIG_USE_PREBOOT=y\n+CONFIG_PREBOOT=\"test -n \\\"${fdtfile}\\\" || setenv fdtfile imx95-verdin-${variant}-${fdt_board}.dtb\"\n+CONFIG_SYS_CBSIZE=2048\n+CONFIG_SYS_PBSIZE=2074\n+CONFIG_LOG=y\n+# CONFIG_DISPLAY_BOARDINFO is not set\n+CONFIG_DISPLAY_BOARDINFO_LATE=y\n+# CONFIG_BOARD_INIT is not set\n+CONFIG_BOARD_LATE_INIT=y\n+CONFIG_SPL_MAX_SIZE=0x30000\n+CONFIG_SPL_BOARD_INIT=y\n+CONFIG_SPL_LOAD_IMX_CONTAINER=y\n+CONFIG_IMX_CONTAINER_CFG=\"arch/arm/mach-imx/imx9/scmi/container.cfg\"\n+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set\n+CONFIG_SPL_HAVE_INIT_STACK=y\n+CONFIG_SPL_SYS_MALLOC=y\n+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y\n+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x93200000\n+CONFIG_SPL_SYS_MALLOC_SIZE=0x80000\n+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y\n+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040\n+CONFIG_SPL_I2C=y\n+CONFIG_SPL_DM_MAILBOX=y\n+CONFIG_SPL_POWER_DOMAIN=y\n+CONFIG_SPL_THERMAL=y\n+CONFIG_SPL_WATCHDOG=y\n+CONFIG_SYS_PROMPT=\"Verdin iMX95 # \"\n+CONFIG_CMD_ASKENV=y\n+CONFIG_CRC32_VERIFY=y\n+CONFIG_CMD_MD5SUM=y\n+CONFIG_MD5SUM_VERIFY=y\n+CONFIG_CMD_MEMTEST=y\n+CONFIG_CMD_CLK=y\n+CONFIG_CMD_FUSE=y\n+CONFIG_CMD_GPIO=y\n+CONFIG_CMD_I2C=y\n+CONFIG_CMD_MMC=y\n+CONFIG_CMD_PCI=y\n+CONFIG_CMD_READ=y\n+CONFIG_CMD_REMOTEPROC=y\n+CONFIG_CMD_USB=y\n+CONFIG_CMD_USB_SDP=y\n+CONFIG_CMD_USB_MASS_STORAGE=y\n+CONFIG_CMD_BOOTCOUNT=y\n+CONFIG_CMD_CACHE=y\n+CONFIG_CMD_TIME=y\n+CONFIG_CMD_SYSBOOT=y\n+CONFIG_CMD_UUID=y\n+CONFIG_CMD_REGULATOR=y\n+CONFIG_CMD_HASH=y\n+CONFIG_CMD_SCMI=y\n+CONFIG_CMD_EXT4_WRITE=y\n+CONFIG_OF_CONTROL=y\n+CONFIG_SPL_OF_CONTROL=y\n+CONFIG_ENV_OVERWRITE=y\n+CONFIG_ENV_IS_IN_MMC=y\n+CONFIG_ENV_RELOC_GD_ENV_ADDR=y\n+CONFIG_ENV_MMC_EMMC_HW_PARTITION=1\n+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y\n+CONFIG_USE_ETHPRIME=y\n+CONFIG_ETHPRIME=\"eth0\"\n+CONFIG_VERSION_VARIABLE=y\n+CONFIG_PROT_UDP=y\n+CONFIG_IP_DEFRAG=y\n+CONFIG_NET_RANDOM_ETHADDR=y\n+CONFIG_TFTP_BLOCKSIZE=4096\n+CONFIG_SYS_RX_ETH_BUFFER=8\n+CONFIG_SPL_DM=y\n+CONFIG_SPL_DM_SEQ_ALIAS=y\n+CONFIG_SYSCON=y\n+CONFIG_SPL_OF_TRANSLATE=y\n+CONFIG_BOOTCOUNT_LIMIT=y\n+CONFIG_BOOTCOUNT_ENV=y\n+CONFIG_CLK=y\n+CONFIG_SPL_CLK=y\n+CONFIG_SPL_CLK_CCF=y\n+CONFIG_CLK_CCF=y\n+CONFIG_CLK_SCMI=y\n+CONFIG_SPL_CLK_SCMI=y\n+CONFIG_USB_FUNCTION_FASTBOOT=y\n+CONFIG_FASTBOOT_BUF_ADDR=0x90400000\n+CONFIG_FASTBOOT_BUF_SIZE=0x20000000\n+CONFIG_FASTBOOT_FLASH=y\n+CONFIG_FASTBOOT_UUU_SUPPORT=y\n+CONFIG_FASTBOOT_FLASH_MMC_DEV=0\n+CONFIG_SPL_FIRMWARE=y\n+# CONFIG_SCMI_AGENT_SMCCC is not set\n+CONFIG_IMX_SM_CPU=y\n+CONFIG_IMX_SM_LMM=y\n+CONFIG_GPIO_HOG=y\n+CONFIG_SPL_GPIO_HOG=y\n+CONFIG_IMX_RGPIO2P=y\n+CONFIG_DM_PCA953X=y\n+CONFIG_SPL_DM_PCA953X=y\n+CONFIG_DM_I2C=y\n+CONFIG_SYS_I2C_IMX_LPI2C=y\n+CONFIG_IMX_MU_MBOX=y\n+CONFIG_I2C_EEPROM=y\n+CONFIG_SUPPORT_EMMC_BOOT=y\n+CONFIG_MMC_IO_VOLTAGE=y\n+CONFIG_MMC_UHS_SUPPORT=y\n+CONFIG_MMC_HS400_ES_SUPPORT=y\n+CONFIG_MMC_HS400_SUPPORT=y\n+CONFIG_FSL_USDHC=y\n+CONFIG_DM_MDIO=y\n+CONFIG_MII=y\n+CONFIG_FSL_ENETC=y\n+CONFIG_PHYLIB=y\n+CONFIG_PHY_TI_DP83867=y\n+CONFIG_PCIE_ECAM_GENERIC=y\n+CONFIG_PHY_IMX8MQ_USB=y\n+CONFIG_PINCTRL=y\n+CONFIG_SPL_PINCTRL=y\n+CONFIG_PINCTRL_IMX_SCMI=y\n+CONFIG_POWER_DOMAIN=y\n+CONFIG_SCMI_POWER_DOMAIN=y\n+CONFIG_DM_REGULATOR=y\n+CONFIG_SPL_DM_REGULATOR=y\n+CONFIG_DM_REGULATOR_FIXED=y\n+CONFIG_SPL_DM_REGULATOR_FIXED=y\n+CONFIG_DM_REGULATOR_GPIO=y\n+CONFIG_REMOTEPROC_IMX=y\n+CONFIG_DM_RNG=y\n+CONFIG_DM_SERIAL=y\n+CONFIG_FSL_LPUART=y\n+CONFIG_SPI=y\n+CONFIG_DM_THERMAL=y\n+CONFIG_USB=y\n+CONFIG_DM_USB_GADGET=y\n+CONFIG_USB_XHCI_HCD=y\n+CONFIG_USB_XHCI_DWC3=y\n+CONFIG_USB_EHCI_HCD=y\n+CONFIG_USB_DWC3=y\n+# CONFIG_USB_DWC3_GADGET is not set\n+CONFIG_USB_HOST_ETHER=y\n+CONFIG_USB_GADGET=y\n+CONFIG_USB_GADGET_MANUFACTURER=\"Toradex\"\n+CONFIG_USB_GADGET_VENDOR_NUM=0x1b67\n+CONFIG_USB_GADGET_PRODUCT_NUM=0x4000\n+CONFIG_USB_GADGET_OS_DESCRIPTORS=y\n+CONFIG_SDP_LOADADDR=0x90400000\n+CONFIG_ULP_WATCHDOG=y\n+# CONFIG_SPL_SHA1 is not set\n+CONFIG_LZO=y\n+CONFIG_HEXDUMP=y\ndiff --git a/doc/board/toradex/index.rst b/doc/board/toradex/index.rst\nindex 27f059542e6a..2a45bde6991a 100644\n--- a/doc/board/toradex/index.rst\n+++ b/doc/board/toradex/index.rst\n@@ -16,3 +16,4 @@ Toradex\n verdin-am62p\n verdin-imx8mm\n verdin-imx8mp\n+ verdin-imx95\ndiff --git a/doc/board/toradex/verdin-imx95.rst b/doc/board/toradex/verdin-imx95.rst\nnew file mode 100644\nindex 000000000000..d252277cc208\n--- /dev/null\n+++ b/doc/board/toradex/verdin-imx95.rst\n@@ -0,0 +1,171 @@\n+.. SPDX-License-Identifier: GPL-2.0-or-later\n+\n+Verdin iMX95 Module\n+==========================\n+\n+- SoM: https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx95\n+- Carrier board: https://www.toradex.com/products/carrier-board/verdin-development-board-kit\n+\n+Quick Start\n+-----------\n+\n+- Setup environment\n+- Get ahab-container.img\n+- Get DDR PHY Firmware Images\n+- Get and Build OEI Images\n+- Get and Build System Manager Image\n+- Get and Build the ARM Trusted Firmware\n+- Build the Bootloader Image\n+- Boot\n+\n+Setup environment\n+-----------------\n+\n+Suggested current toolchains are ARM 14.3 (https://developer.arm.com/downloads/-/arm-gnu-toolchain-downloads):\n+\n+- https://developer.arm.com/-/media/Files/downloads/gnu/14.3.rel1/binrel/arm-gnu-toolchain-14.3.rel1-x86_64-arm-none-linux-gnueabihf.tar.xz\n+- https://developer.arm.com/-/media/Files/downloads/gnu/14.3.rel1/binrel/arm-gnu-toolchain-14.3.rel1-x86_64-aarch64-none-linux-gnu.tar.xz\n+\n+.. code-block:: console\n+\n+ $ export TOOLS=<path/to/directory/with/toolchains>\n+ $ export CROSS_COMPILE_32=<path/to/arm/toolchain/bin/>arm-none-linux-gnueabihf-\n+ $ export CROSS_COMPILE_64=<path/to/arm64/toolchain/bin/>aarch64-none-linux-gnu-\n+\n+Get ahab-container.img\n+----------------------\n+\n+Note: `$srctree` is the U-Boot source directory\n+\n+.. code-block:: console\n+\n+ $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-ele-imx-2.0.2-89161a8.bin\n+ $ sh firmware-ele-imx-2.0.2-89161a8.bin --auto-accept\n+ $ cp firmware-ele-imx-2.0.2-89161a8/mx95b0-ahab-container.img $(srctree)\n+\n+Get DDR PHY Firmware Images\n+---------------------------\n+\n+Note: `$srctree` is the U-Boot source directory\n+\n+.. code-block:: console\n+\n+ $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.28-994fa14.bin\n+ $ sh firmware-imx-8.28-994fa14.bin --auto-accept\n+ $ cp firmware-imx-8.28-994fa14/firmware/ddr/synopsys/lpddr4x*v202409.bin $(srctree)\n+\n+Get and Build OEI Images\n+------------------------\n+\n+Note: `$srctree` is the U-Boot source directory\n+Get OEI from: https://git.toradex.com/cgit/imx-oei-toradex.git/\n+branch: main\n+\n+.. code-block:: console\n+\n+ $ git clone -b main https://git.toradex.com/cgit/imx-oei-toradex.git/\n+ $ cd imx-oei-toradex\n+\n+ $ make board=toradex-verdin-imx95 oei=ddr DEBUG=1 r=B0 all\n+ $ cp build/toradex-verdin-imx95/ddr/oei-m33-ddr.bin $(srctree)\n+\n+The Makefile will set `DDR_CONFIG` automatically based on the selected silicon\n+revision.\n+\n+Get and Build the System Manager Image\n+--------------------------------------\n+\n+Note: `$srctree` is the U-Boot source directory\n+Get System Manager from: https://git.toradex.com/cgit/imx-sm-toradex.git/\n+branch: main\n+\n+.. code-block:: console\n+\n+ $ git clone -b main https://git.toradex.com/cgit/imx-sm-toradex.git/\n+ $ cd imx-sm-toradex\n+ $ make config=verdin-imx95 all\n+ $ cp build/verdin-imx95/m33_image.bin $(srctree)\n+\n+Get and Build the ARM Trusted Firmware\n+--------------------------------------\n+\n+Note: `$srctree` is the U-Boot source directory\n+Get ATF from: https://github.com/nxp-imx/imx-atf/\n+branch: lf_v2.12\n+\n+.. code-block:: console\n+\n+ $ export CROSS_COMPILE=$CROSS_COMPILE_64\n+ $ unset LDFLAGS\n+ $ unset AS\n+ $ git clone -b lf_v2.12 https://github.com/nxp-imx/imx-atf.git\n+ $ cd imx-atf\n+ $ make PLAT=imx95 bl31\n+ $ cp build/imx95/release/bl31.bin $(srctree)\n+\n+Build the Bootloader Image\n+--------------------------\n+\n+.. code-block:: console\n+\n+ $ export CROSS_COMPILE=$CROSS_COMPILE_64\n+ $ make verdin-imx95_defconfig\n+ $ make\n+\n+Flash to eMMC\n+-------------\n+\n+.. code-block:: console\n+\n+ > tftpboot ${loadaddr} flash.bin\n+ > setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt ${blkcnt} / 0x200\n+ > mmc dev 0 1 && mmc write ${loadaddr} 0x0 ${blkcnt}\n+\n+As a convenience, instead of the last two commands, one may also use the update\n+U-Boot wrapper:\n+\n+.. code-block:: console\n+\n+ > run update_uboot\n+\n+Boot\n+----\n+\n+Boot sequence is:\n+\n+* SPL ---> ATF (TF-A) ---> U-Boot proper\n+\n+Output:\n+\n+.. code-block:: console\n+\n+ U-Boot SPL 2026.04-00756-ge7053d7cab88 (Apr 15 2026 - 12:27:34 +0200)\n+ SYS Boot reason: pmic, origin: -1, errid: -1\n+ SYS shutdown reason: pmic, origin: -1, errid: -1\n+ Trying to boot from MMC1\n+ Primary set selected\n+ Load image from MMC/SD 0xca000\n+ NOTICE: BL31: v2.12.0(release):lf-6.12.20-2.0.0\n+ NOTICE: BL31: Built : 17:34:12, Oct 21 2025\n+\n+\n+ U-Boot 2026.04-00756-ge7053d7cab88 (Apr 15 2026 - 12:27:34 +0200)\n+\n+ CPU: NXP i.MX95 Rev2.0 A55 at 1800 MHz - invalid sensor data\n+ DRAM: 7.8 GiB\n+ Core: 323 devices, 28 uclasses, devicetree: separate\n+ MMC: FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2\n+ Loading Environment from MMC... Reading from MMC(0)... OK\n+ In: serial@44380000\n+ Out: serial@44380000\n+ Err: serial@44380000\n+ Model: Toradex 0089 Verdin iMX95 Hexa 8GB WB IT V1.0B\n+ Serial#: 12594936\n+\n+ BuildInfo:\n+ - ELE firmware version 2.0.2-2a118457\n+\n+ Setting variant to wifi\n+ Net: No ethernet found.\n+ Hit any key to stop autoboot: 0\n+ Verdin iMX95 #\ndiff --git a/include/configs/verdin-imx95.h b/include/configs/verdin-imx95.h\nnew file mode 100644\nindex 000000000000..30eb2e01460b\n--- /dev/null\n+++ b/include/configs/verdin-imx95.h\n@@ -0,0 +1,27 @@\n+/* SPDX-License-Identifier: GPL-2.0-or-later */\n+/* Copyright (c) Toradex */\n+\n+#ifndef __VERDIN_IMX95_H\n+#define __VERDIN_IMX95_H\n+\n+#include <linux/sizes.h>\n+#include <asm/arch/imx-regs.h>\n+\n+/* For 32GB modules: 2GB from 0x80000000..0xffffffff, 30GB above.\n+ * Actual size is determined at runtime.\n+ */\n+#define SZ_30G\t_AC(0x780000000, ULL)\n+\n+/* The first 256MB of SDRAM is reserved for firmware (Cortex M7) */\n+#define PHYS_SDRAM_FW_RSVD\tSZ_256M\n+#define CFG_SYS_INIT_RAM_ADDR\tPHYS_SDRAM\n+#define CFG_SYS_INIT_RAM_SIZE\tSZ_2M\n+\n+#define CFG_SYS_SDRAM_BASE\tPHYS_SDRAM\n+#define PHYS_SDRAM\t\t(0x80000000 + PHYS_SDRAM_FW_RSVD)\n+#define PHYS_SDRAM_SIZE\t\t(SZ_2G - PHYS_SDRAM_FW_RSVD)\n+#define PHYS_SDRAM_2_SIZE\tSZ_30G\n+\n+#define WDOG_BASE_ADDR\t\tWDG3_BASE_ADDR\n+\n+#endif\n", "prefixes": [ "v2", "2/3" ] }