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GET /api/1.2/patches/2224203/?format=api
{ "id": 2224203, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2224203/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260417032837.2664122-2-jamin_lin@aspeedtech.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.2/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260417032837.2664122-2-jamin_lin@aspeedtech.com>", "list_archive_url": null, "date": "2026-04-17T03:28:39", "name": "[v4,01/21] hw/misc/aspeed_scu: Introduce Aspeed2700SCU subclass and separate from generic SCU", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "47d02b7ed2ef86dbe116c14d2016f383111e359c", "submitter": { "id": 81768, "url": "http://patchwork.ozlabs.org/api/1.2/people/81768/?format=api", "name": "Jamin Lin", "email": "jamin_lin@aspeedtech.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260417032837.2664122-2-jamin_lin@aspeedtech.com/mbox/", "series": [ { "id": 500228, "url": "http://patchwork.ozlabs.org/api/1.2/series/500228/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500228", "date": "2026-04-17T03:28:41", "name": "Add SSP/TSP power control and DRAM remap support for AST2700", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/500228/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2224203/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2224203/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=aspeedtech.com header.i=@aspeedtech.com\n header.a=rsa-sha256 header.s=selector1 header.b=RFSr4F2s;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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Thu, 16 Apr 2026 23:28:50 -0400", "from TYPPR06MB8206.apcprd06.prod.outlook.com (2603:1096:405:383::19)\n by KL1PR06MB6299.apcprd06.prod.outlook.com (2603:1096:820:ce::14)\n with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9818.25; Fri, 17 Apr\n 2026 03:28:40 +0000", "from TYPPR06MB8206.apcprd06.prod.outlook.com\n ([fe80::e659:1ead:77cb:f6d3]) by TYPPR06MB8206.apcprd06.prod.outlook.com\n ([fe80::e659:1ead:77cb:f6d3%3]) with mapi id 15.20.9818.023; Fri, 17 Apr 2026\n 03:28:39 +0000" ], "ARC-Seal": "i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none;\n b=oMGI9YIsxQXZ5Lf3atX+GdGGyDwyNU1xAOWcA0BjC1gf+ajvTbc35oVjbGHhC+IR6fYbonb6gGpYeCRObfBUj7LuivHurIBd1ZeC9+ISVLTykRLC3zrzmYpTWzx7AajHmvjhpQsI+7+9vGaabM2JmRzKcyiTKyv+j4t6VrCi3lqCwmAfgBODpHY7e61xg5xizGSjzULiEzFdfDyziacorJE059MUluarATIlxDx7Bdc0HwnsunWI+4DZw760FoT5aYTAO/Fq7BfZZaJJPrC7wQjtD10d3wB68UmN0dC/lyONDSEyxKMLPm+Z/OWhacMhC8pGWP0vWId21+B8fACqNA==", "ARC-Message-Signature": "i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;\n s=arcselector10001;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1;\n bh=X1/CUfImRJKUwTDSTvyffV8Z4qr6OFYqWkkd5PBicsc=;\n b=CkBr+P7sbMoVOM9bPU96Q+WOrbF0GhJhzIaxqVniE87vZukphN/LHW7S6Mgmclcb/4QXjxUxqYkKASY33SvwfjfjYYiejnlx6kHzypq05sJ2EYMo8712FX5AH+9dko+l4HkANHZyqT2MDVXJYLv/LCnZ1ckO3tiK7I7juFjRr+zGKMcEH9LasVVJdU6AkCJufaUOaSJH0+gUoBECUIG9ONa4Wfa7hwjZCcXRgW6CC4YRULTqaIsw6ADJAiDSF3PFBPzWpTpf7nW/8HX9J9dmP4ncIbYnyQbLcY2lNQ7d1KCTrXss5sJl3fZQ+2ahDK6u2GhFe53w//Yd57QIKeLY5w==", "ARC-Authentication-Results": "i=1; mx.microsoft.com 1; spf=pass\n smtp.mailfrom=aspeedtech.com; dmarc=pass action=none\n header.from=aspeedtech.com; dkim=pass header.d=aspeedtech.com; arc=none", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=aspeedtech.com;\n s=selector1;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=X1/CUfImRJKUwTDSTvyffV8Z4qr6OFYqWkkd5PBicsc=;\n b=RFSr4F2smvIwB2LHTwAdy2OfZHTI7nlOo3iSXmbreTouBp2zoPJApjn23iWBAyv12afHkOPAdk3MqTtSec+MIxDCjUEYEUP2VRxKnfYY8q2GbCbSX8O4H4YUmZWWpJNdAZe12loY86Kolqh6A5QJsq4TZKQ8KwQxSYYM/qBzPCh3bXgHYeVhqbKD+tigSOKnanCWO8ygH5+V6V+Fv51s03rvLjfKwRWP+Q03UXyd4pDtpo8n2kvRgs1EuHSVrz0WzjzQQBqAMaAvIpmX9dBuQJZQFqqnnfQF89I/F7Y8aWE7nMGvaQ+ImUzOWPy+FCwihA2v0OPA1drWUMx+eGQScA==", "From": "Jamin Lin <jamin_lin@aspeedtech.com>", "To": "=?iso-8859-1?q?C=E9dric_Le_Goater?= <clg@kaod.org>,\n Peter Maydell <peter.maydell@linaro.org>,\n Steven Lee <steven_lee@aspeedtech.com>, Troy Lee <leetroy@gmail.com>,\n Kane Chen <kane_chen@aspeedtech.com>,\n Andrew Jeffery <andrew@codeconstruct.com.au>, Joel Stanley <joel@jms.id.au>,\n Pierrick Bouvier <pierrick.bouvier@linaro.org>,\n Alistair Francis <alistair@alistair23.me>, Kevin Wolf <kwolf@redhat.com>,\n Hanna Reitz <hreitz@redhat.com>,\n \"open list:ASPEED BMCs\" <qemu-arm@nongnu.org>,\n \"open list:All patches CC here\" <qemu-devel@nongnu.org>,\n \"open list:Block layer core\" <qemu-block@nongnu.org>", "CC": "Jamin Lin <jamin_lin@aspeedtech.com>, Troy Lee <troy_lee@aspeedtech.com>", "Subject": "[PATCH v4 01/21] hw/misc/aspeed_scu: Introduce Aspeed2700SCU subclass\n and separate from generic SCU", "Thread-Topic": "[PATCH v4 01/21] hw/misc/aspeed_scu: Introduce Aspeed2700SCU\n subclass and separate from generic SCU", "Thread-Index": "AQHczhpIwQwUTbK4GEqFW40cS4W0FQ==", "Date": "Fri, 17 Apr 2026 03:28:39 +0000", "Message-ID": "<20260417032837.2664122-2-jamin_lin@aspeedtech.com>", "References": "<20260417032837.2664122-1-jamin_lin@aspeedtech.com>", "In-Reply-To": "<20260417032837.2664122-1-jamin_lin@aspeedtech.com>", "Accept-Language": "zh-TW, en-US", "Content-Language": "en-US", "X-MS-Has-Attach": "", "X-MS-TNEF-Correlator": "", "authentication-results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=aspeedtech.com header.i=@aspeedtech.com\n header.a=rsa-sha256 header.s=selector1 header.b=RFSr4F2s;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=\"iso-8859-1\"", "Content-Transfer-Encoding": "quoted-printable", "MIME-Version": "1.0", "X-Exchange-RoutingPolicyChecked": "\n P6Bj+g71chr7/e0iwtoTiU1BT6E2OjCgwk2xr5Vj8aIq52ZuH+n+j5v8jM2oHpubAFfyaxBRlTuIu8YBO6G3/KWmeULFtiuHUu8ypl6Krdo13c4YujWTXqKXx9fsm8NHKt/JqPjWKUVbfvw4OnZeb+7bF95cMv8S6V6yTwaY8RjtPCq4cxdUdRTgSxFvD/EodHHQi73ZdYoKiq0uGDHXZWLSs03hZVW+c8tPayXexz5n3JLV/ibHOInFyzCrMCDfky2grT07Ux6fnA9JqLVX18RcBNLswcRLj9lN33OzWu2mSVvVIuLio76VpdKF6xWgm6kxlSnd7vIXYUrSSTMsMw==", "X-OriginatorOrg": "aspeedtech.com", "X-MS-Exchange-CrossTenant-AuthAs": "Internal", "X-MS-Exchange-CrossTenant-AuthSource": "TYPPR06MB8206.apcprd06.prod.outlook.com", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 03ca410f-7a5f-40ad-09e5-08de9c316b38", "X-MS-Exchange-CrossTenant-originalarrivaltime": "17 Apr 2026 03:28:39.8951 (UTC)", "X-MS-Exchange-CrossTenant-fromentityheader": "Hosted", "X-MS-Exchange-CrossTenant-id": "43d4aa98-e35b-4575-8939-080e90d5a249", "X-MS-Exchange-CrossTenant-mailboxtype": "HOSTED", "X-MS-Exchange-CrossTenant-userprincipalname": "\n igrXCXqm/LaDPCqeI11AGYAXEJpqKZ4eOEE4Bgykef6wOwC8++6fGwqkdoSIgapWgRbBfNBvcsjxvjzYX7obMh0J3tXRLrncY18+9lm2a9M=", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "KL1PR06MB6299", "Received-SPF": "pass client-ip=2a01:111:f403:c405::5;\n envelope-from=jamin_lin@aspeedtech.com;\n helo=TYPPR03CU001.outbound.protection.outlook.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n SPF_HELO_PASS=-0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Introduce a dedicated Aspeed2700SCUState subclass to isolate AST2700-specific\nbehavior from the generic AspeedSCUState implementation.\n\nPreviously, AST17x0/27x0 platforms reused AspeedSCUState directly, including\nin coprocessor paths. With AST2700 introducing additional requirements (e.g.\nfuture coprocessor features such as DRAM remapping), continuing to extend the\ngeneric SCU risks impacting other SoCs.\n\nTo address this, add Aspeed2700SCUState as a subclass of AspeedSCUState and\nmigrate all AST2700-related users to it, including:\n- AST1700 SoC\n- AST27x0 SoC\n- AST27x0 FC\n- AST27x0 coprocessors\n\nAs part of this refactoring:\n- Remove SCU linkage from the common AspeedCoprocessorState\n- Add a dedicated 'scu' link property to Aspeed27x0CoprocessorState\n- Update SCU memory aliasing to reference the subclass (parent_obj.iomem)\n\nThis separation keeps the common code generic while enabling AST2700-specific\nextensions in both SCU and coprocessor paths.\n\nNo functional change.\n\nSigned-off-by: Jamin Lin <jamin_lin@aspeedtech.com>\n---\n include/hw/arm/aspeed_ast1700.h | 2 +-\n include/hw/arm/aspeed_coprocessor.h | 5 +++--\n include/hw/arm/aspeed_soc.h | 1 +\n include/hw/misc/aspeed_scu.h | 5 +++++\n hw/arm/aspeed_ast27x0-fc.c | 4 ++--\n hw/arm/aspeed_ast27x0-ssp.c | 14 ++++++++++----\n hw/arm/aspeed_ast27x0-tsp.c | 14 ++++++++++----\n hw/arm/aspeed_ast27x0.c | 16 ++++++++--------\n hw/arm/aspeed_coprocessor_common.c | 2 --\n hw/misc/aspeed_scu.c | 8 +++++++-\n 10 files changed, 47 insertions(+), 24 deletions(-)", "diff": "diff --git a/include/hw/arm/aspeed_ast1700.h b/include/hw/arm/aspeed_ast1700.h\nindex f7bd4e8650..39c5977cf1 100644\n--- a/include/hw/arm/aspeed_ast1700.h\n+++ b/include/hw/arm/aspeed_ast1700.h\n@@ -41,7 +41,7 @@ struct AspeedAST1700SoCState {\n MemoryRegion sram;\n AspeedSMCState spi;\n AspeedADCState adc;\n- AspeedSCUState scu;\n+ Aspeed2700SCUState scu;\n AspeedGPIOState gpio;\n AspeedSGPIOState sgpiom[AST1700_SGPIO_NUM];\n AspeedI2CState i2c;\ndiff --git a/include/hw/arm/aspeed_coprocessor.h b/include/hw/arm/aspeed_coprocessor.h\nindex 4a50f688ec..4db995d251 100644\n--- a/include/hw/arm/aspeed_coprocessor.h\n+++ b/include/hw/arm/aspeed_coprocessor.h\n@@ -20,10 +20,8 @@ struct AspeedCoprocessorState {\n MemoryRegion *sram;\n MemoryRegion sram_alias;\n MemoryRegion uart_alias;\n- MemoryRegion scu_alias;\n Clock *sysclk;\n \n- AspeedSCUState *scu;\n AspeedSCUState scuio;\n AspeedTimerCtrlState timerctrl;\n SerialMM *uart;\n@@ -50,6 +48,9 @@ struct Aspeed27x0CoprocessorState {\n UnimplementedDeviceState scuio;\n \n ARMv7MState armv7m;\n+\n+ MemoryRegion scu_alias;\n+ Aspeed2700SCUState *scu;\n };\n \n #define TYPE_ASPEED27X0SSP_COPROCESSOR \"aspeed27x0ssp-coprocessor\"\ndiff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h\nindex d7b3647ca1..adf2f2898a 100644\n--- a/include/hw/arm/aspeed_soc.h\n+++ b/include/hw/arm/aspeed_soc.h\n@@ -151,6 +151,7 @@ struct Aspeed27x0SoCState {\n AspeedINTCState intcioexp[ASPEED_IOEXP_NUM];\n GICv3State gic;\n MemoryRegion dram_empty;\n+ Aspeed2700SCUState scu;\n };\n \n #define TYPE_ASPEED27X0_SOC \"aspeed27x0-soc\"\ndiff --git a/include/hw/misc/aspeed_scu.h b/include/hw/misc/aspeed_scu.h\nindex d003955428..fd30313e69 100644\n--- a/include/hw/misc/aspeed_scu.h\n+++ b/include/hw/misc/aspeed_scu.h\n@@ -20,6 +20,7 @@ OBJECT_DECLARE_TYPE(AspeedSCUState, AspeedSCUClass, ASPEED_SCU)\n #define TYPE_ASPEED_2500_SCU TYPE_ASPEED_SCU \"-ast2500\"\n #define TYPE_ASPEED_2600_SCU TYPE_ASPEED_SCU \"-ast2600\"\n #define TYPE_ASPEED_2700_SCU TYPE_ASPEED_SCU \"-ast2700\"\n+OBJECT_DECLARE_SIMPLE_TYPE(Aspeed2700SCUState, ASPEED_2700_SCU)\n #define TYPE_ASPEED_2700_SCUIO TYPE_ASPEED_SCU \"io\" \"-ast2700\"\n #define TYPE_ASPEED_1030_SCU TYPE_ASPEED_SCU \"-ast1030\"\n \n@@ -41,6 +42,10 @@ struct AspeedSCUState {\n uint32_t hw_prot_key;\n };\n \n+struct Aspeed2700SCUState {\n+ AspeedSCUState parent_obj;\n+};\n+\n #define AST2400_A1_SILICON_REV 0x02010303U\n #define AST2500_A1_SILICON_REV 0x04010303U\n #define AST2600_A3_SILICON_REV 0x05030303U\ndiff --git a/hw/arm/aspeed_ast27x0-fc.c b/hw/arm/aspeed_ast27x0-fc.c\nindex 5eb6680da9..46f0c97329 100644\n--- a/hw/arm/aspeed_ast27x0-fc.c\n+++ b/hw/arm/aspeed_ast27x0-fc.c\n@@ -156,7 +156,7 @@ static bool ast2700fc_ssp_init(MachineState *machine, Error **errp)\n object_property_set_link(OBJECT(&s->ssp), \"sram\",\n OBJECT(&psp->sram), &error_abort);\n object_property_set_link(OBJECT(&s->ssp), \"scu\",\n- OBJECT(&psp->scu), &error_abort);\n+ OBJECT(&s->ca35.scu), &error_abort);\n if (!qdev_realize(DEVICE(&s->ssp), NULL, errp)) {\n return false;\n }\n@@ -188,7 +188,7 @@ static bool ast2700fc_tsp_init(MachineState *machine, Error **errp)\n object_property_set_link(OBJECT(&s->tsp), \"sram\",\n OBJECT(&psp->sram), &error_abort);\n object_property_set_link(OBJECT(&s->tsp), \"scu\",\n- OBJECT(&psp->scu), &error_abort);\n+ OBJECT(&s->ca35.scu), &error_abort);\n if (!qdev_realize(DEVICE(&s->tsp), NULL, errp)) {\n return false;\n }\ndiff --git a/hw/arm/aspeed_ast27x0-ssp.c b/hw/arm/aspeed_ast27x0-ssp.c\nindex 8b84300e0f..9a2079668b 100644\n--- a/hw/arm/aspeed_ast27x0-ssp.c\n+++ b/hw/arm/aspeed_ast27x0-ssp.c\n@@ -186,11 +186,11 @@ static void aspeed_soc_ast27x0ssp_realize(DeviceState *dev_soc, Error **errp)\n &s->sram_alias);\n \n /* SCU */\n- memory_region_init_alias(&s->scu_alias, OBJECT(s), \"scu.alias\",\n- &s->scu->iomem, 0,\n- memory_region_size(&s->scu->iomem));\n+ memory_region_init_alias(&a->scu_alias, OBJECT(a), \"scu.alias\",\n+ &a->scu->parent_obj.iomem, 0,\n+ memory_region_size(&a->scu->parent_obj.iomem));\n memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SCU],\n- &s->scu_alias);\n+ &a->scu_alias);\n \n /* INTC */\n if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc[0]), errp)) {\n@@ -257,6 +257,11 @@ static void aspeed_soc_ast27x0ssp_realize(DeviceState *dev_soc, Error **errp)\n sc->memmap[ASPEED_DEV_SCUIO], 0x1000);\n }\n \n+static const Property aspeed_27x0_coprocessor_properties[] = {\n+ DEFINE_PROP_LINK(\"scu\", Aspeed27x0CoprocessorState, scu,\n+ TYPE_ASPEED_2700_SCU, Aspeed2700SCUState *),\n+};\n+\n static void aspeed_soc_ast27x0ssp_class_init(ObjectClass *klass,\n const void *data)\n {\n@@ -270,6 +275,7 @@ static void aspeed_soc_ast27x0ssp_class_init(ObjectClass *klass,\n /* Reason: The Aspeed Coprocessor can only be instantiated from a board */\n dc->user_creatable = false;\n dc->realize = aspeed_soc_ast27x0ssp_realize;\n+ device_class_set_props(dc, aspeed_27x0_coprocessor_properties);\n \n sc->valid_cpu_types = valid_cpu_types;\n sc->irqmap = aspeed_soc_ast27x0ssp_irqmap;\ndiff --git a/hw/arm/aspeed_ast27x0-tsp.c b/hw/arm/aspeed_ast27x0-tsp.c\nindex e7c7b74491..674307103e 100644\n--- a/hw/arm/aspeed_ast27x0-tsp.c\n+++ b/hw/arm/aspeed_ast27x0-tsp.c\n@@ -186,11 +186,11 @@ static void aspeed_soc_ast27x0tsp_realize(DeviceState *dev_soc, Error **errp)\n &s->sram_alias);\n \n /* SCU */\n- memory_region_init_alias(&s->scu_alias, OBJECT(s), \"scu.alias\",\n- &s->scu->iomem, 0,\n- memory_region_size(&s->scu->iomem));\n+ memory_region_init_alias(&a->scu_alias, OBJECT(a), \"scu.alias\",\n+ &a->scu->parent_obj.iomem, 0,\n+ memory_region_size(&a->scu->parent_obj.iomem));\n memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SCU],\n- &s->scu_alias);\n+ &a->scu_alias);\n \n /* INTC */\n if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc[0]), errp)) {\n@@ -257,6 +257,11 @@ static void aspeed_soc_ast27x0tsp_realize(DeviceState *dev_soc, Error **errp)\n sc->memmap[ASPEED_DEV_SCUIO], 0x1000);\n }\n \n+static const Property aspeed_27x0_coprocessor_properties[] = {\n+ DEFINE_PROP_LINK(\"scu\", Aspeed27x0CoprocessorState, scu,\n+ TYPE_ASPEED_2700_SCU, Aspeed2700SCUState *),\n+};\n+\n static void aspeed_soc_ast27x0tsp_class_init(ObjectClass *klass,\n const void *data)\n {\n@@ -270,6 +275,7 @@ static void aspeed_soc_ast27x0tsp_class_init(ObjectClass *klass,\n /* Reason: The Aspeed Coprocessor can only be instantiated from a board */\n dc->user_creatable = false;\n dc->realize = aspeed_soc_ast27x0tsp_realize;\n+ device_class_set_props(dc, aspeed_27x0_coprocessor_properties);\n \n sc->valid_cpu_types = valid_cpu_types;\n sc->irqmap = aspeed_soc_ast27x0tsp_irqmap;\ndiff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c\nindex 87dcb82e1b..e84975a9c4 100644\n--- a/hw/arm/aspeed_ast27x0.c\n+++ b/hw/arm/aspeed_ast27x0.c\n@@ -425,12 +425,12 @@ static void aspeed_soc_ast2700_init(Object *obj)\n \n object_initialize_child(obj, \"gic\", &a->gic, gicv3_class_name());\n \n- object_initialize_child(obj, \"scu\", &s->scu, TYPE_ASPEED_2700_SCU);\n- qdev_prop_set_uint32(DEVICE(&s->scu), \"silicon-rev\",\n+ object_initialize_child(obj, \"scu\", &a->scu, TYPE_ASPEED_2700_SCU);\n+ qdev_prop_set_uint32(DEVICE(&a->scu), \"silicon-rev\",\n sc->silicon_rev);\n- object_property_add_alias(obj, \"hw-strap1\", OBJECT(&s->scu),\n+ object_property_add_alias(obj, \"hw-strap1\", OBJECT(&a->scu),\n \"hw-strap1\");\n- object_property_add_alias(obj, \"hw-prot-key\", OBJECT(&s->scu),\n+ object_property_add_alias(obj, \"hw-prot-key\", OBJECT(&a->scu),\n \"hw-prot-key\");\n \n object_initialize_child(obj, \"scuio\", &s->scuio, TYPE_ASPEED_2700_SCUIO);\n@@ -794,10 +794,10 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)\n sc->memmap[ASPEED_DEV_VBOOTROM], &s->vbootrom);\n \n /* SCU */\n- if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) {\n+ if (!sysbus_realize(SYS_BUS_DEVICE(&a->scu), errp)) {\n return;\n }\n- aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->scu), 0,\n+ aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&a->scu), 0,\n sc->memmap[ASPEED_DEV_SCU]);\n \n /* SCU1 */\n@@ -915,7 +915,7 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)\n AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]);\n hwaddr wdt_offset = sc->memmap[ASPEED_DEV_WDT] + i * awc->iosize;\n \n- object_property_set_link(OBJECT(&s->wdt[i]), \"scu\", OBJECT(&s->scu),\n+ object_property_set_link(OBJECT(&s->wdt[i]), \"scu\", OBJECT(&a->scu),\n &error_abort);\n if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) {\n return;\n@@ -1018,7 +1018,7 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)\n aspeed_soc_ast2700_get_irq(s, ASPEED_DEV_EMMC));\n \n /* Timer */\n- object_property_set_link(OBJECT(&s->timerctrl), \"scu\", OBJECT(&s->scu),\n+ object_property_set_link(OBJECT(&s->timerctrl), \"scu\", OBJECT(&a->scu),\n &error_abort);\n if (!sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), errp)) {\n return;\ndiff --git a/hw/arm/aspeed_coprocessor_common.c b/hw/arm/aspeed_coprocessor_common.c\nindex a0a4c73d08..43026d2a55 100644\n--- a/hw/arm/aspeed_coprocessor_common.c\n+++ b/hw/arm/aspeed_coprocessor_common.c\n@@ -27,8 +27,6 @@ static const Property aspeed_coprocessor_properties[] = {\n TYPE_MEMORY_REGION, MemoryRegion *),\n DEFINE_PROP_LINK(\"sram\", AspeedCoprocessorState, sram, TYPE_MEMORY_REGION,\n MemoryRegion *),\n- DEFINE_PROP_LINK(\"scu\", AspeedCoprocessorState, scu, TYPE_ASPEED_SCU,\n- AspeedSCUState *),\n DEFINE_PROP_LINK(\"uart\", AspeedCoprocessorState, uart, TYPE_SERIAL_MM,\n SerialMM *),\n DEFINE_PROP_INT32(\"uart-dev\", AspeedCoprocessorState, uart_dev, 0),\ndiff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c\nindex e4160356e4..0a2dad4537 100644\n--- a/hw/misc/aspeed_scu.c\n+++ b/hw/misc/aspeed_scu.c\n@@ -959,6 +959,11 @@ static void aspeed_ast2700_scu_reset(DeviceState *dev)\n s->regs[AST2700_HW_STRAP1] = s->hw_strap1;\n }\n \n+static void aspeed_2700_scu_realize(DeviceState *dev, Error **errp)\n+{\n+ aspeed_scu_realize(dev, errp);\n+}\n+\n static void aspeed_2700_scu_class_init(ObjectClass *klass, const void *data)\n {\n DeviceClass *dc = DEVICE_CLASS(klass);\n@@ -966,6 +971,7 @@ static void aspeed_2700_scu_class_init(ObjectClass *klass, const void *data)\n \n dc->desc = \"ASPEED 2700 System Control Unit\";\n device_class_set_legacy_reset(dc, aspeed_ast2700_scu_reset);\n+ dc->realize = aspeed_2700_scu_realize;\n asc->resets = ast2700_a0_resets;\n asc->calc_hpll = aspeed_2600_scu_calc_hpll;\n asc->get_apb = aspeed_2700_scu_get_apb_freq;\n@@ -1097,7 +1103,7 @@ static void aspeed_2700_scuio_class_init(ObjectClass *klass, const void *data)\n static const TypeInfo aspeed_2700_scu_info = {\n .name = TYPE_ASPEED_2700_SCU,\n .parent = TYPE_ASPEED_SCU,\n- .instance_size = sizeof(AspeedSCUState),\n+ .instance_size = sizeof(Aspeed2700SCUState),\n .class_init = aspeed_2700_scu_class_init,\n };\n \n", "prefixes": [ "v4", "01/21" ] }