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GET /api/1.2/patches/2224201/?format=api
{ "id": 2224201, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2224201/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260417032837.2664122-10-jamin_lin@aspeedtech.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.2/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260417032837.2664122-10-jamin_lin@aspeedtech.com>", "list_archive_url": null, "date": "2026-04-17T03:28:50", "name": "[v4,09/21] hw/misc/aspeed_scu: Add SCU support for SSP SDRAM remap", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "5ba68714ec63d3703ca8e353c2f6a10ede06615d", "submitter": { "id": 81768, "url": "http://patchwork.ozlabs.org/api/1.2/people/81768/?format=api", "name": "Jamin Lin", "email": "jamin_lin@aspeedtech.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260417032837.2664122-10-jamin_lin@aspeedtech.com/mbox/", "series": [ { "id": 500228, "url": "http://patchwork.ozlabs.org/api/1.2/series/500228/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500228", "date": "2026-04-17T03:28:41", "name": "Add SSP/TSP power control and DRAM remap support for AST2700", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/500228/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2224201/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2224201/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=aspeedtech.com header.i=@aspeedtech.com\n header.a=rsa-sha256 header.s=selector1 header.b=RWUQ44sx;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;\n s=arcselector10001;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1;\n bh=okdtxpjVP3phSX2NRzlscNjtC0zc9L+xbSVmFt/fApE=;\n b=CPr92eBlqIHwQp01laUQpEEG6ZJKZC049uZOm+qML1QjCS+8iI7VNK/ZtQpmKbq00iqe24JBP2cwxHDxJ3z7xIWTfFhqNWClxEiBtOfpEgakrXOIYOG18Bpb6vZLXXik42eS4+XbKpy84ujhKmuXBbcDMEb9k6OUdmt8pjPewHXI9XYfkostzYTeRpmIAcWHpC/T0p6DSdojP1mRRIa+i/VI36QAkLDo1b9qju+hdKfey0KhFE6ur8TSDxkOPWjdqZTPAZjBYpKoTE18eown2sCZZ4gWSkJMUpciTbPY8Www6qHPGHu8XcSQF2fjW6vMDn55FE0TrRSU31T1lDuKxQ==", "ARC-Authentication-Results": "i=1; mx.microsoft.com 1; spf=pass\n smtp.mailfrom=aspeedtech.com; dmarc=pass action=none\n header.from=aspeedtech.com; dkim=pass header.d=aspeedtech.com; arc=none", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=aspeedtech.com;\n s=selector1;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=okdtxpjVP3phSX2NRzlscNjtC0zc9L+xbSVmFt/fApE=;\n b=RWUQ44sxaym+n+SucTmucNmi1/I83Gb7DIv3xbLe4jsTZd4TKmX1gkelf1IOr/JpWeQB4Fatxy63upBqParcFF0B8T6GHitwAlG5oXA5c60ciUrksiBkRICnrO8dv1Kju3qmOHfA+54vtVhmCb/yhBrO3y2otPZY+yP1PmBhCFcQeEYRkHL/lBuAFteJddEFvgogqgrtNNwCkD3EKtYJb5fVECRazEF3BV/WdRuO8MKQNKVxVnIFuhSqf05/YzOBgc3CWGRMq+B1WrW76PSBwHGn9vc+qIpGXNNa8wm85h9GY43ggeBsKDlmcKueY3BdhB3hMtx5VT2P7/S+8JcHLQ==", "From": "Jamin Lin <jamin_lin@aspeedtech.com>", "To": "=?iso-8859-1?q?C=E9dric_Le_Goater?= <clg@kaod.org>,\n Peter Maydell <peter.maydell@linaro.org>,\n Steven Lee <steven_lee@aspeedtech.com>, Troy Lee <leetroy@gmail.com>,\n Kane Chen <kane_chen@aspeedtech.com>,\n Andrew Jeffery <andrew@codeconstruct.com.au>, Joel Stanley <joel@jms.id.au>,\n Pierrick Bouvier <pierrick.bouvier@linaro.org>,\n Alistair Francis <alistair@alistair23.me>, Kevin Wolf <kwolf@redhat.com>,\n Hanna Reitz <hreitz@redhat.com>,\n \"open list:ASPEED BMCs\" <qemu-arm@nongnu.org>,\n \"open list:All patches CC here\" <qemu-devel@nongnu.org>,\n \"open list:Block layer core\" <qemu-block@nongnu.org>", "CC": "Jamin Lin <jamin_lin@aspeedtech.com>, Troy Lee <troy_lee@aspeedtech.com>", "Subject": "[PATCH v4 09/21] hw/misc/aspeed_scu: Add SCU support for SSP SDRAM\n remap", "Thread-Topic": "[PATCH v4 09/21] hw/misc/aspeed_scu: Add SCU support for SSP\n SDRAM remap", "Thread-Index": "AQHczhpP7lP3YZX350681N5dJHbE4Q==", "Date": "Fri, 17 Apr 2026 03:28:50 +0000", "Message-ID": "<20260417032837.2664122-10-jamin_lin@aspeedtech.com>", "References": "<20260417032837.2664122-1-jamin_lin@aspeedtech.com>", "In-Reply-To": "<20260417032837.2664122-1-jamin_lin@aspeedtech.com>", "Accept-Language": "zh-TW, en-US", "Content-Language": "en-US", "X-MS-Has-Attach": "", "X-MS-TNEF-Correlator": "", "authentication-results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=aspeedtech.com header.i=@aspeedtech.com\n header.a=rsa-sha256 header.s=selector1 header.b=RWUQ44sx;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=\"iso-8859-1\"", "Content-Transfer-Encoding": "quoted-printable", "MIME-Version": "1.0", "X-Exchange-RoutingPolicyChecked": "\n Qt06daHbEPvVlq+zqiy0pWjGLK7U8irViCSGMiJmuUtivi6AAfLbbvS9sd8KBg+Z0TD9o1q5YhbhMosXvYw8TRCMi2FK/jvR2X1bserviygPudIYIYQ36U/JpBmO2S4cez7FYaYmtZIETpQ37KyyiSWBopT8Y4Di+sv9IKlprkNjQl5DWMSjfmF1p0iKHhHVUdw0g9VERoVTfg9wk08d6tYO6hhNL8XitXVdFislcOQpZKIIymxttncfaeIg6PV/jwxWNc5RWLZIUfJD3DVjUuAIB8bc102LDzwCiiCccZDkXjWFMJXtGc1xsfynsIXXCGY/aw7YGk/MmO06kFsHWQ==", "X-OriginatorOrg": "aspeedtech.com", "X-MS-Exchange-CrossTenant-AuthAs": "Internal", "X-MS-Exchange-CrossTenant-AuthSource": "TYPPR06MB8206.apcprd06.prod.outlook.com", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 6550541e-5708-4f36-6d34-08de9c3171d4", "X-MS-Exchange-CrossTenant-originalarrivaltime": "17 Apr 2026 03:28:50.9755 (UTC)", "X-MS-Exchange-CrossTenant-fromentityheader": "Hosted", "X-MS-Exchange-CrossTenant-id": "43d4aa98-e35b-4575-8939-080e90d5a249", "X-MS-Exchange-CrossTenant-mailboxtype": "HOSTED", "X-MS-Exchange-CrossTenant-userprincipalname": "\n BWUUqvInF33qgn62C8mNOV1IPHEFE/q1UjGfrmi+7jx5rIdw/1xdzOyUkIYy2lf+l1Y2XGRAGoySDU0wPqab7g+GDS+OiBpCyM96neOA3ZI=", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "KL1PR06MB6299", "Received-SPF": "pass client-ip=2a01:111:f403:c405::7;\n envelope-from=jamin_lin@aspeedtech.com;\n helo=TYDPR03CU002.outbound.protection.outlook.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "This commit adds SCU register support for SSP SDRAM remap control and runtime\nactivation. It introduces logic for the PSP to dynamically configure the mapping\nof its own DRAM windows into SSP-visible SDRAM space, enabling shared memory\ncommunication via memory region aliases.\n\n- coprocessor_sdram_remap[0]: maps PSP DRAM offset 0x400000000 (size: 0x1A77E000) to SSP SDRAM\n offset 0x5880000\n- coprocessor_sdram_remap[1]: maps PSP DRAM offset 0x42C000000 (size: 0x05880000) to SSP SDRAM\n offset 0x0\n\nThe SCU registers AST2700_SCU_SSP_CTRL_1/2 and\nAST2700_SCU_SSP_REMAP_ADDR_{1,2} / REMAP_SIZE_{1,2} allow runtime reconfiguration\nof alias offset, base, and size.\n\n|------------------------------------------| |----------------------------|\n| PSP DRAM | | SSP SDRAM |\n|------------------------------------------| |----------------------------|\n| 0x4_0000_0000 (SCU_124 << 4) | --> | 0x0000_0000 |\n| remap1 base |---| | | - SCU_150: target addr |\n| size: 0x1A77E000 (SCU_14C) | | | | remap2 |\n|------------------------------------------| | | |----------------------------|\n| | | | | |\n| 0x4_2C00_0000 (SCU_128 << 4) |-----| | 0x5880000 |\n| remap2 base | | | - SCU_148: target addr |\n| size: 0x05880000 (SCU_154) | |---> | remap1 |\n|------------------------------------------| |----------------------------|\n\nSigned-off-by: Jamin Lin <jamin_lin@aspeedtech.com>\n---\n hw/misc/aspeed_scu.c | 54 ++++++++++++++++++++++++++++++++++++++++++++\n 1 file changed, 54 insertions(+)", "diff": "diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c\nindex 6512b5fccd..8d1ad95402 100644\n--- a/hw/misc/aspeed_scu.c\n+++ b/hw/misc/aspeed_scu.c\n@@ -147,6 +147,14 @@\n \n /* SSP TSP */\n #define AST2700_SCU_SSP_CTRL_0 TO_REG(0x120)\n+#define AST2700_SCU_SSP_CTRL_1 TO_REG(0x124)\n+#define AST2700_SCU_SSP_CTRL_2 TO_REG(0x128)\n+#define AST2700_SCU_SSP_REMAP_ADDR_0 TO_REG(0x140)\n+#define AST2700_SCU_SSP_REMAP_SIZE_0 TO_REG(0x144)\n+#define AST2700_SCU_SSP_REMAP_ADDR_1 TO_REG(0x148)\n+#define AST2700_SCU_SSP_REMAP_SIZE_1 TO_REG(0x14C)\n+#define AST2700_SCU_SSP_REMAP_ADDR_2 TO_REG(0x150)\n+#define AST2700_SCU_SSP_REMAP_SIZE_2 TO_REG(0x154)\n #define AST2700_SCU_TSP_CTRL_0 TO_REG(0x160)\n #define AST2700_SSP_TSP_ENABLE BIT(0)\n #define AST2700_SSP_TSP_RST BIT(1)\n@@ -938,6 +946,7 @@ static void aspeed_ast2700_scu_write(void *opaque, hwaddr offset,\n {\n Aspeed2700SCUState *a = ASPEED_2700_SCU(opaque);\n AspeedSCUState *s = ASPEED_SCU(opaque);\n+ MemoryRegion *mr = NULL;\n int reg = TO_REG(offset);\n /* Truncate here so bitwise operations below behave as expected */\n uint32_t data = data64;\n@@ -995,6 +1004,37 @@ static void aspeed_ast2700_scu_write(void *opaque, hwaddr offset,\n data &= ~AST2700_SSP_TSP_ENABLE;\n s->regs[reg] = (s->regs[reg] & ~0xff) | (data & 0xff);\n return;\n+ case AST2700_SCU_SSP_CTRL_1:\n+ case AST2700_SCU_SSP_CTRL_2:\n+ mr = (reg == AST2700_SCU_SSP_CTRL_1) ?\n+ &a->dram_remap_alias[0] : &a->dram_remap_alias[1];\n+ if (a->ssp_cpuid < 0 || mr == NULL) {\n+ return;\n+ }\n+ data &= 0x7fffffff;\n+ memory_region_set_alias_offset(mr,\n+ ((uint64_t) data << 4) & 0x3ffffffff);\n+ break;\n+ case AST2700_SCU_SSP_REMAP_ADDR_1:\n+ case AST2700_SCU_SSP_REMAP_ADDR_2:\n+ mr = (reg == AST2700_SCU_SSP_REMAP_ADDR_1) ?\n+ &a->dram_remap_alias[0] : &a->dram_remap_alias[1];\n+ if (a->ssp_cpuid < 0 || mr == NULL) {\n+ return;\n+ }\n+ data &= 0x3fffffff;\n+ memory_region_set_address(mr, data);\n+ break;\n+ case AST2700_SCU_SSP_REMAP_SIZE_1:\n+ case AST2700_SCU_SSP_REMAP_SIZE_2:\n+ mr = (reg == AST2700_SCU_SSP_REMAP_SIZE_1) ?\n+ &a->dram_remap_alias[0] : &a->dram_remap_alias[1];\n+ if (a->ssp_cpuid < 0 || mr == NULL) {\n+ return;\n+ }\n+ data &= 0x3fffffff;\n+ memory_region_set_size(mr, data);\n+ break;\n case AST2700_SCU_SYS_RST_CTRL_1:\n if (a->ssp_cpuid < 0) {\n return;\n@@ -1065,6 +1105,14 @@ static const uint32_t ast2700_a0_resets[ASPEED_AST2700_SCU_NR_REGS] = {\n [AST2700_HW_STRAP1_SEC2] = 0x00000000,\n [AST2700_HW_STRAP1_SEC3] = 0x1000408F,\n [AST2700_SCU_SSP_CTRL_0] = 0x000007FE,\n+ [AST2700_SCU_SSP_CTRL_1] = 0x40000000,\n+ [AST2700_SCU_SSP_CTRL_2] = 0x42C00000,\n+ [AST2700_SCU_SSP_REMAP_ADDR_0] = 0x1FFFE000,\n+ [AST2700_SCU_SSP_REMAP_SIZE_0] = 0x00002000,\n+ [AST2700_SCU_SSP_REMAP_ADDR_1] = 0x05880000,\n+ [AST2700_SCU_SSP_REMAP_SIZE_1] = 0x1A77E000,\n+ [AST2700_SCU_SSP_REMAP_ADDR_2] = 0x00000000,\n+ [AST2700_SCU_SSP_REMAP_SIZE_2] = 0x05880000,\n [AST2700_SCU_TSP_CTRL_0] = 0x000007FE,\n [AST2700_SCU_SYS_RST_CTRL_1] = 0xFFC37FDC,\n [AST2700_SCU_SYS_RST_CTRL_2] = 0x00001FFF,\n@@ -1097,6 +1145,12 @@ static void aspeed_ast2700_scu_reset(DeviceState *dev)\n \n if (a->ssp_cpuid > 0) {\n arm_set_cpu_off(a->ssp_cpuid);\n+ memory_region_set_address(&a->dram_remap_alias[0], 0x5880000);\n+ memory_region_set_alias_offset(&a->dram_remap_alias[0], 0);\n+ memory_region_set_size(&a->dram_remap_alias[0], 0x1a77e000);\n+ memory_region_set_address(&a->dram_remap_alias[1], 0);\n+ memory_region_set_alias_offset(&a->dram_remap_alias[1], 0x2c000000);\n+ memory_region_set_size(&a->dram_remap_alias[1], 0x5880000);\n }\n \n if (a->tsp_cpuid > 0) {\n", "prefixes": [ "v4", "09/21" ] }