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GET /api/1.2/patches/2224198/?format=api
{ "id": 2224198, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2224198/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260417032837.2664122-19-jamin_lin@aspeedtech.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.2/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260417032837.2664122-19-jamin_lin@aspeedtech.com>", "list_archive_url": null, "date": "2026-04-17T03:29:02", "name": "[v4,18/21] hw/arm/ast27x0: Share single SCUIO instance across PSP, SSP, and TSP", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "ed8fbd477cc2e76d58859b4575e21b21caecd837", "submitter": { "id": 81768, "url": "http://patchwork.ozlabs.org/api/1.2/people/81768/?format=api", "name": "Jamin Lin", "email": "jamin_lin@aspeedtech.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260417032837.2664122-19-jamin_lin@aspeedtech.com/mbox/", "series": [ { "id": 500228, "url": "http://patchwork.ozlabs.org/api/1.2/series/500228/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500228", "date": "2026-04-17T03:28:41", "name": "Add SSP/TSP power control and DRAM remap support for AST2700", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/500228/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2224198/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2224198/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ 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b=ILarq7JxeJSPAQbsmGr3E15pb15TsA+jQEelW+wgmT34aTLWbzfnqxqOE0eXDmNjak5UIPoWvSwyMSiJpZnpK2beQ3z1+I2+9YD4KEuor77Qr2ABMwFzJo2zI/8T1a9eR/On9cUZp7ZAbov1vU/yyB5dPl4mgEBpWpdHjugXP/Pju2tKw4ReZmGrhxUyuJdafIM69qOYjgvTks4j07/SPVrXfiJyW3oqggxlXO00YXTOFeQTplmKlBC929OU/ivEjkpQUzmbEMPIS1qDaulo2uCQVgFaGo1J3ExDylxociuF1uMaLR3ZD9v55RbjyojrsIxDSZ5vr6h/WVjRQKaBdw==", "From": "Jamin Lin <jamin_lin@aspeedtech.com>", "To": "=?windows-1252?q?C=E9dric_Le_Goater?= <clg@kaod.org>,\n Peter Maydell <peter.maydell@linaro.org>,\n Steven Lee <steven_lee@aspeedtech.com>, Troy Lee <leetroy@gmail.com>,\n Kane Chen <kane_chen@aspeedtech.com>,\n Andrew Jeffery <andrew@codeconstruct.com.au>, Joel Stanley <joel@jms.id.au>,\n Pierrick Bouvier <pierrick.bouvier@linaro.org>,\n Alistair Francis <alistair@alistair23.me>, Kevin Wolf <kwolf@redhat.com>,\n Hanna Reitz <hreitz@redhat.com>,\n \"open list:ASPEED BMCs\" <qemu-arm@nongnu.org>,\n \"open list:All patches CC here\" <qemu-devel@nongnu.org>,\n \"open list:Block layer core\" <qemu-block@nongnu.org>", "CC": "Jamin Lin <jamin_lin@aspeedtech.com>, Troy Lee <troy_lee@aspeedtech.com>", "Subject": "[PATCH v4 18/21] hw/arm/ast27x0: Share single SCUIO instance across\n PSP, SSP, and TSP", "Thread-Topic": "[PATCH v4 18/21] hw/arm/ast27x0: Share single SCUIO instance\n across PSP, SSP, and TSP", "Thread-Index": "AQHczhpWpaIQjJL2qkyBZ0SmmuHXHw==", "Date": "Fri, 17 Apr 2026 03:29:02 +0000", "Message-ID": "<20260417032837.2664122-19-jamin_lin@aspeedtech.com>", "References": "<20260417032837.2664122-1-jamin_lin@aspeedtech.com>", "In-Reply-To": "<20260417032837.2664122-1-jamin_lin@aspeedtech.com>", "Accept-Language": "zh-TW, en-US", "Content-Language": "en-US", "X-MS-Has-Attach": "", "X-MS-TNEF-Correlator": "", "authentication-results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=aspeedtech.com header.i=@aspeedtech.com\n header.a=rsa-sha256 header.s=selector1 header.b=ILarq7Jx;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender 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"X-MS-Exchange-CrossTenant-mailboxtype": "HOSTED", "X-MS-Exchange-CrossTenant-userprincipalname": "\n oJ859lWe01igD+HwPoStmkug3hmbUpU0loXxnescUQV+SHzT9WYvRpdoZlx9zUNXxXZZRBrwqKoTJmRINmzYb0oaNKW2rLQDWVI5aKXFMzY=", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "KUZPR06MB8076", "Received-SPF": "pass client-ip=2a01:111:f403:c40f::6;\n envelope-from=jamin_lin@aspeedtech.com;\n helo=SEYPR02CU001.outbound.protection.outlook.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n SPF_HELO_PASS=-0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "AST2700 has a single SCUIO hardware block, memory-mapped at\n0x14C02000–0x14C03FFF from the perspective of the main CA35 processor (PSP).\nThe SSP and TSP coprocessors access this same SCUIO block at different\naddresses: 0x74C02000–0x74C03FFF.\n\nPreviously, each subsystem (PSP, SSP, and TSP) instantiated its own SCUIO\ndevice, resulting in three independent SCUIO instances in the QEMU model.\nIn real hardware, however, only a single SCUIO exists and is shared among\nall processors.\n\nThis commit reworks the SCUIO model to correctly reflect the hardware\nbehavior by allowing SSP and TSP to reference the PSP’s SCUIO instance.\nThe following changes are introduced:\n\n- Add a scuio property to Aspeed27x0CoprocessorState for linking the\n coprocessor to the PSP’s SCUIO instance.\n- Replace per-coprocessor SCUIO instantiation with a shared SCUIO link.\n- Add \"MemoryRegion scuio_alias\" to model address remapping for SSP and TSP.\n- Create SCUIO alias regions in both SSP and TSP coprocessors and map\n them at 0x74C02000 to mirror the PSP’s SCUIO registers.\n- Ensure the SCUIO device in PSP is realized before SSP/TSP alias setup.\n\nWith this change, PSP, SSP, and TSP now share a consistent SCUIO state,\nmatching the single-SCUIO hardware design of AST2700.\n\nSigned-off-by: Jamin Lin <jamin_lin@aspeedtech.com>\n---\n include/hw/arm/aspeed_coprocessor.h | 4 ++--\n hw/arm/aspeed_ast27x0-fc.c | 4 ++++\n hw/arm/aspeed_ast27x0-ssp.c | 14 +++++++++-----\n hw/arm/aspeed_ast27x0-tsp.c | 14 +++++++++-----\n 4 files changed, 24 insertions(+), 12 deletions(-)", "diff": "diff --git a/include/hw/arm/aspeed_coprocessor.h b/include/hw/arm/aspeed_coprocessor.h\nindex 7750569eed..23c3b97f06 100644\n--- a/include/hw/arm/aspeed_coprocessor.h\n+++ b/include/hw/arm/aspeed_coprocessor.h\n@@ -22,7 +22,6 @@ struct AspeedCoprocessorState {\n MemoryRegion uart_alias;\n Clock *sysclk;\n \n- AspeedSCUState scuio;\n AspeedTimerCtrlState timerctrl;\n SerialMM *uart;\n int uart_dev;\n@@ -45,15 +44,16 @@ struct Aspeed27x0CoprocessorState {\n AspeedCoprocessorState parent;\n AspeedINTCState intc[2];\n UnimplementedDeviceState ipc[2];\n- UnimplementedDeviceState scuio;\n UnimplementedDeviceState pric[2];\n UnimplementedDeviceState otp;\n \n ARMv7MState armv7m;\n \n MemoryRegion scu_alias;\n+ MemoryRegion scuio_alias;\n MemoryRegion fmc_alias;\n Aspeed2700SCUState *scu;\n+ AspeedSCUState *scuio;\n AspeedSMCState *fmc;\n };\n \ndiff --git a/hw/arm/aspeed_ast27x0-fc.c b/hw/arm/aspeed_ast27x0-fc.c\nindex 56dd86e2c2..d1ff6fbd4d 100644\n--- a/hw/arm/aspeed_ast27x0-fc.c\n+++ b/hw/arm/aspeed_ast27x0-fc.c\n@@ -161,6 +161,8 @@ static bool ast2700fc_ssp_init(MachineState *machine, Error **errp)\n OBJECT(&psp->sram), &error_abort);\n object_property_set_link(OBJECT(&s->ssp), \"scu\",\n OBJECT(&s->ca35.scu), &error_abort);\n+ object_property_set_link(OBJECT(&s->ssp), \"scuio\",\n+ OBJECT(&psp->scuio), &error_abort);\n object_property_set_link(OBJECT(&s->ssp), \"fmc\",\n OBJECT(&psp->fmc), &error_abort);\n if (!qdev_realize(DEVICE(&s->ssp), NULL, errp)) {\n@@ -195,6 +197,8 @@ static bool ast2700fc_tsp_init(MachineState *machine, Error **errp)\n OBJECT(&psp->sram), &error_abort);\n object_property_set_link(OBJECT(&s->tsp), \"scu\",\n OBJECT(&s->ca35.scu), &error_abort);\n+ object_property_set_link(OBJECT(&s->tsp), \"scuio\",\n+ OBJECT(&psp->scuio), &error_abort);\n object_property_set_link(OBJECT(&s->tsp), \"fmc\",\n OBJECT(&psp->fmc), &error_abort);\n if (!qdev_realize(DEVICE(&s->tsp), NULL, errp)) {\ndiff --git a/hw/arm/aspeed_ast27x0-ssp.c b/hw/arm/aspeed_ast27x0-ssp.c\nindex 78bd6f342c..6c8945ce6c 100644\n--- a/hw/arm/aspeed_ast27x0-ssp.c\n+++ b/hw/arm/aspeed_ast27x0-ssp.c\n@@ -143,8 +143,6 @@ static void aspeed_soc_ast27x0ssp_init(Object *obj)\n TYPE_UNIMPLEMENTED_DEVICE);\n object_initialize_child(obj, \"ipc1\", &a->ipc[1],\n TYPE_UNIMPLEMENTED_DEVICE);\n- object_initialize_child(obj, \"scuio\", &a->scuio,\n- TYPE_UNIMPLEMENTED_DEVICE);\n object_initialize_child(obj, \"pric0\", &a->pric[0],\n TYPE_UNIMPLEMENTED_DEVICE);\n object_initialize_child(obj, \"pric1\", &a->pric[1],\n@@ -215,6 +213,13 @@ static void aspeed_soc_ast27x0ssp_realize(DeviceState *dev_soc, Error **errp)\n memory_region_size(&a->scu->dram_remap_alias[1]),\n &a->scu->dram_remap_alias[0]);\n \n+ /* SCUIO */\n+ memory_region_init_alias(&a->scuio_alias, OBJECT(a), \"scuio.alias\",\n+ &a->scuio->iomem, 0,\n+ memory_region_size(&a->scuio->iomem));\n+ memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SCUIO],\n+ &a->scuio_alias);\n+\n /* INTC */\n if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc[0]), errp)) {\n return;\n@@ -282,9 +287,6 @@ static void aspeed_soc_ast27x0ssp_realize(DeviceState *dev_soc, Error **errp)\n aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&a->ipc[1]),\n \"aspeed.ipc1\",\n sc->memmap[ASPEED_DEV_IPC1], 0x1000);\n- aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&a->scuio),\n- \"aspeed.scuio\",\n- sc->memmap[ASPEED_DEV_SCUIO], 0x1000);\n aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&a->pric[0]),\n \"aspeed.pric0\",\n sc->memmap[ASPEED_DEV_PRIC0], 0x1000);\n@@ -299,6 +301,8 @@ static void aspeed_soc_ast27x0ssp_realize(DeviceState *dev_soc, Error **errp)\n static const Property aspeed_27x0_coprocessor_properties[] = {\n DEFINE_PROP_LINK(\"scu\", Aspeed27x0CoprocessorState, scu,\n TYPE_ASPEED_2700_SCU, Aspeed2700SCUState *),\n+ DEFINE_PROP_LINK(\"scuio\", Aspeed27x0CoprocessorState, scuio,\n+ TYPE_ASPEED_SCU, AspeedSCUState *),\n DEFINE_PROP_LINK(\"fmc\", Aspeed27x0CoprocessorState, fmc, TYPE_ASPEED_SMC,\n AspeedSMCState *),\n };\ndiff --git a/hw/arm/aspeed_ast27x0-tsp.c b/hw/arm/aspeed_ast27x0-tsp.c\nindex d6448d82f5..cab7f47ac8 100644\n--- a/hw/arm/aspeed_ast27x0-tsp.c\n+++ b/hw/arm/aspeed_ast27x0-tsp.c\n@@ -143,8 +143,6 @@ static void aspeed_soc_ast27x0tsp_init(Object *obj)\n TYPE_UNIMPLEMENTED_DEVICE);\n object_initialize_child(obj, \"ipc1\", &a->ipc[1],\n TYPE_UNIMPLEMENTED_DEVICE);\n- object_initialize_child(obj, \"scuio\", &a->scuio,\n- TYPE_UNIMPLEMENTED_DEVICE);\n object_initialize_child(obj, \"pric0\", &a->pric[0],\n TYPE_UNIMPLEMENTED_DEVICE);\n object_initialize_child(obj, \"pric1\", &a->pric[1],\n@@ -212,6 +210,13 @@ static void aspeed_soc_ast27x0tsp_realize(DeviceState *dev_soc, Error **errp)\n /* SDRAM remap alias used by PSP to access TSP SDRAM */\n memory_region_add_subregion(&s->sdram, 0, &a->scu->dram_remap_alias[2]);\n \n+ /* SCUIO */\n+ memory_region_init_alias(&a->scuio_alias, OBJECT(a), \"scuio.alias\",\n+ &a->scuio->iomem, 0,\n+ memory_region_size(&a->scuio->iomem));\n+ memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SCUIO],\n+ &a->scuio_alias);\n+\n /* INTC */\n if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc[0]), errp)) {\n return;\n@@ -279,9 +284,6 @@ static void aspeed_soc_ast27x0tsp_realize(DeviceState *dev_soc, Error **errp)\n aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&a->ipc[1]),\n \"aspeed.ipc1\",\n sc->memmap[ASPEED_DEV_IPC1], 0x1000);\n- aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&a->scuio),\n- \"aspeed.scuio\",\n- sc->memmap[ASPEED_DEV_SCUIO], 0x1000);\n aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&a->pric[0]),\n \"aspeed.pric0\",\n sc->memmap[ASPEED_DEV_PRIC0], 0x1000);\n@@ -296,6 +298,8 @@ static void aspeed_soc_ast27x0tsp_realize(DeviceState *dev_soc, Error **errp)\n static const Property aspeed_27x0_coprocessor_properties[] = {\n DEFINE_PROP_LINK(\"scu\", Aspeed27x0CoprocessorState, scu,\n TYPE_ASPEED_2700_SCU, Aspeed2700SCUState *),\n+ DEFINE_PROP_LINK(\"scuio\", Aspeed27x0CoprocessorState, scuio,\n+ TYPE_ASPEED_SCU, AspeedSCUState *),\n DEFINE_PROP_LINK(\"fmc\", Aspeed27x0CoprocessorState, fmc, TYPE_ASPEED_SMC,\n AspeedSMCState *),\n };\n", "prefixes": [ "v4", "18/21" ] }