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patch:
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Update a patch.
GET /api/1.2/patches/2224191/?format=api
{ "id": 2224191, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2224191/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260417032837.2664122-15-jamin_lin@aspeedtech.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.2/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260417032837.2664122-15-jamin_lin@aspeedtech.com>", "list_archive_url": null, "date": "2026-04-17T03:28:57", "name": "[v4,14/21] hw/block/m25p80: Implement volatile status register write enable for Winbond", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "22d977c4b54eb4614248b59bafab59d56a36fdfe", "submitter": { "id": 81768, "url": "http://patchwork.ozlabs.org/api/1.2/people/81768/?format=api", "name": "Jamin Lin", "email": "jamin_lin@aspeedtech.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260417032837.2664122-15-jamin_lin@aspeedtech.com/mbox/", "series": [ { "id": 500228, "url": "http://patchwork.ozlabs.org/api/1.2/series/500228/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500228", "date": "2026-04-17T03:28:41", "name": "Add SSP/TSP power control and DRAM remap support for AST2700", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/500228/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2224191/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2224191/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=aspeedtech.com header.i=@aspeedtech.com\n header.a=rsa-sha256 header.s=selector1 header.b=lDfG6Xq9;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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Thu, 16 Apr 2026 23:29:13 -0400", "from TYPPR06MB8206.apcprd06.prod.outlook.com (2603:1096:405:383::19)\n by KL1PR06MB6299.apcprd06.prod.outlook.com (2603:1096:820:ce::14)\n with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9818.25; Fri, 17 Apr\n 2026 03:28:57 +0000", "from TYPPR06MB8206.apcprd06.prod.outlook.com\n ([fe80::e659:1ead:77cb:f6d3]) by TYPPR06MB8206.apcprd06.prod.outlook.com\n ([fe80::e659:1ead:77cb:f6d3%3]) with mapi id 15.20.9818.023; Fri, 17 Apr 2026\n 03:28:57 +0000" ], "ARC-Seal": "i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none;\n b=QCzjSWUNtIK2Z+Hrxvql4B1ySpJsuTDe+3k65k0x23CObIvo1+CT2bRLsF/2x9nA81jniukZDewujlFm2zzGhHrBVR5O0sntI9xbSAJIzF0EafOjRBJB2U1QRiyz9PFcgKBRqRGAt0uDkvpxKq/AAV2bT47GpeZmYKlEuRvN1szYCtM8AwJmBJTtX1+CwvnzQ0xXq91iGlL0KoKG60qLO5GOHLqbIS88EioDTmNURjMtmPfMTB7ToZHys+SELlC56unNIklEliEugufE5txHZDeQIQHQ/zTm0oyO/FQz6zGZj3xBqQdtfbzr8DFk1Rq5AWYD5+gze+H/LqXufEAgwQ==", "ARC-Message-Signature": "i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;\n s=arcselector10001;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1;\n bh=Wdn49wxih/GxlQRPCZsSv0ZU4aHVolZYhvwrQewYITs=;\n b=Up0E0Kpc8/zxMzTGrcb1dAOPNmxNhgdg3StXvROq/+2gsG7h+SQkYZpqaONJIUWhGYIfzVSG8HtGr8M/um73R3GImC1YXKO1ur0fr/3FcIXbv2fyXcEEoXoy0K2Xj0oZslN1qsKsSmd4vx9lU3bpE+0iqNfKzh490uoLeGo+q1llNnFoOmHnW7DV+4n6s2ljum/g4oM2PaVSFyuO76swsnc1G5yeWUmnwS/qpXDpFlu0S+FxEJM/bGmQMCmzQ78+fe0Q7OOc4iUY3mRu0+iDQMNAsGtzOEcOR4lJJXzAv0XuRlKGZaM5k8/Muits+2UczpImYFB5xeJq9ZW1klVufA==", "ARC-Authentication-Results": "i=1; mx.microsoft.com 1; spf=pass\n smtp.mailfrom=aspeedtech.com; dmarc=pass action=none\n header.from=aspeedtech.com; dkim=pass header.d=aspeedtech.com; arc=none", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=aspeedtech.com;\n s=selector1;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=Wdn49wxih/GxlQRPCZsSv0ZU4aHVolZYhvwrQewYITs=;\n b=lDfG6Xq9Tay7J5XBdLULmXLsGjMEGZrvfE5zyyUCE7tDAXpFjDHwBUaLzu9vxBPa660H/qC3i2n/o2QKtU4e/ucy5lphoYWICFX60GvLfabpEnFxG1qAc8Z+YjeKnya/x5AXGjL8XhproQFbTFJzrVZpHGUa1rP44b3+pxAxi0ggEgvczPLQUwTgZ66OuYAgYuZJ/BB9fdyqG8RAlnLP/IGcQT1vOKYIXxB5bCspBs3YlIlN00fKwB6nxurpAUQG/q0vn9KUWOdB0cWtwrjvGeQ5E8qluOvZEuEYZ+P2fHBd+mcJT79NSaIra8eJXSktckBQOtjQvC2l2BN/13cfmA==", "From": "Jamin Lin <jamin_lin@aspeedtech.com>", "To": "=?iso-8859-1?q?C=E9dric_Le_Goater?= <clg@kaod.org>,\n Peter Maydell <peter.maydell@linaro.org>,\n Steven Lee <steven_lee@aspeedtech.com>, Troy Lee <leetroy@gmail.com>,\n Kane Chen <kane_chen@aspeedtech.com>,\n Andrew Jeffery <andrew@codeconstruct.com.au>, Joel Stanley <joel@jms.id.au>,\n Pierrick Bouvier <pierrick.bouvier@linaro.org>,\n Alistair Francis <alistair@alistair23.me>, Kevin Wolf <kwolf@redhat.com>,\n Hanna Reitz <hreitz@redhat.com>,\n \"open list:ASPEED BMCs\" <qemu-arm@nongnu.org>,\n \"open list:All patches CC here\" <qemu-devel@nongnu.org>,\n \"open list:Block layer core\" <qemu-block@nongnu.org>", "CC": "Jamin Lin <jamin_lin@aspeedtech.com>, Troy Lee <troy_lee@aspeedtech.com>", "Subject": "[PATCH v4 14/21] hw/block/m25p80: Implement volatile status register\n write enable for Winbond", "Thread-Topic": "[PATCH v4 14/21] hw/block/m25p80: Implement volatile status\n register write enable for Winbond", "Thread-Index": "AQHczhpT9wtBbTDpD0ylh+liRbo2Cw==", "Date": "Fri, 17 Apr 2026 03:28:57 +0000", "Message-ID": "<20260417032837.2664122-15-jamin_lin@aspeedtech.com>", "References": "<20260417032837.2664122-1-jamin_lin@aspeedtech.com>", "In-Reply-To": "<20260417032837.2664122-1-jamin_lin@aspeedtech.com>", "Accept-Language": "zh-TW, en-US", "Content-Language": "en-US", "X-MS-Has-Attach": "", "X-MS-TNEF-Correlator": "", "authentication-results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=aspeedtech.com header.i=@aspeedtech.com\n header.a=rsa-sha256 header.s=selector1 header.b=lDfG6Xq9;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=\"iso-8859-1\"", "Content-Transfer-Encoding": "quoted-printable", "MIME-Version": "1.0", "X-Exchange-RoutingPolicyChecked": "\n c1vBfhesbAgO/jPeh7n6RYJRalhdbXcUxZ4F8YHakTIEyqYgzNkGJyZfpd6AJrKtPGzISMXgZSuFJ9OQ3TouAvXCOB0+Do1sotJKECG8DTPLk26zNAdHyrXhH3WLqE52MnNhz+RaXYW5zfi1aYB2Pf7Vr4gkdhBr8kOQy+cW495W81ygRompjAd9aer8ARn+9RhKHUa4MwU2u1GDE6vFwAjrcuQ2WxW6On0w7dGGrKJLr0En7//1njTE/NwbU89XczS8JvYOLcKsstvHO39q+peE9IcmqYVy5vYI2HahSTG/kWdU0nztM7fGd1c0JMVUIFXpSCVq7F1Sf94jZZiSQA==", "X-OriginatorOrg": "aspeedtech.com", "X-MS-Exchange-CrossTenant-AuthAs": "Internal", "X-MS-Exchange-CrossTenant-AuthSource": "TYPPR06MB8206.apcprd06.prod.outlook.com", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 3a34299c-5297-4b2b-cdd9-08de9c31759b", "X-MS-Exchange-CrossTenant-originalarrivaltime": "17 Apr 2026 03:28:57.3111 (UTC)", "X-MS-Exchange-CrossTenant-fromentityheader": "Hosted", "X-MS-Exchange-CrossTenant-id": "43d4aa98-e35b-4575-8939-080e90d5a249", "X-MS-Exchange-CrossTenant-mailboxtype": "HOSTED", "X-MS-Exchange-CrossTenant-userprincipalname": "\n uRJTjF5zs06hGXEN6/qj9vrambC7wqE+1ebJUPBTXt0sbhsBDXAIYias7PD81oH+GWzMyXshTb5L2F0GXJug6f4TK3DTfgjbx8eoSIVzf4E=", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "KL1PR06MB6299", "Received-SPF": "pass client-ip=2a01:111:f403:c405::5;\n envelope-from=jamin_lin@aspeedtech.com;\n helo=TYPPR03CU001.outbound.protection.outlook.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n SPF_HELO_PASS=-0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Winbond SPI NOR flashes require the Volatile Status Register Write Enable\n(VSR WREN, opcode 0x50) command to be issued before updating volatile\nstatus register bits, such as those accessed via the WRSR2 command.\n\nCurrently, WRSR2 handling only checks the standard write enable latch,\nwhich does not fully model Winbond hardware behavior.\n\nAdd support for the volatile write enable mechanism by introducing a\nseparate volatile_write_enable flag. For Winbond devices, WRSR2 writes\nthat update volatile status register bits are gated by the VSR WREN\ncommand. If the volatile write enable latch is not set, such writes are\nrejected.\n\nSigned-off-by: Jamin Lin <jamin_lin@aspeedtech.com>\n---\n hw/block/m25p80.c | 36 ++++++++++++++++++++++++++++++++----\n 1 file changed, 32 insertions(+), 4 deletions(-)", "diff": "diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c\nindex b8a2543c0b..5bb8b8efa9 100644\n--- a/hw/block/m25p80.c\n+++ b/hw/block/m25p80.c\n@@ -438,6 +438,11 @@ typedef enum {\n */\n WRSR2 = 0x31,\n \n+ /*\n+ * Winbond: 0x50 - Write Enable for Volatile Status Register\n+ */\n+ VSR_WREN = 0x50,\n+\n RNVCR = 0xB5,\n WNVCR = 0xB1,\n \n@@ -510,6 +515,7 @@ struct Flash {\n uint8_t spansion_cr4v;\n bool wp_level;\n bool write_enable;\n+ bool volatile_write_enable;\n bool four_bytes_address_mode;\n bool reset_enable;\n bool quad_enable;\n@@ -897,6 +903,7 @@ static void reset_memory(Flash *s)\n s->pos = 0;\n s->state = STATE_IDLE;\n s->write_enable = false;\n+ s->volatile_write_enable = false;\n s->reset_enable = false;\n s->quad_enable = false;\n s->aai_enable = false;\n@@ -1305,8 +1312,7 @@ static void decode_new_cmd(Flash *s, uint32_t value)\n * combinations of the two states are called \"software protected mode\"\n * (SPM), and status register writes are permitted.\n */\n- if ((s->wp_level == 0 && s->status_register_write_disabled)\n- || !s->write_enable) {\n+ if (s->wp_level == 0 && s->status_register_write_disabled) {\n qemu_log_mask(LOG_GUEST_ERROR,\n \"M25P80: Status register 2 write is disabled!\\n\");\n break;\n@@ -1314,6 +1320,17 @@ static void decode_new_cmd(Flash *s, uint32_t value)\n \n switch (get_man(s)) {\n case MAN_WINBOND:\n+ /*\n+ * Winbond requires VSR WREN (0x50) prior to updating volatile\n+ * status register bits. VSR WREN does not set WEL.\n+ *\n+ * Accept either standard WEL (0x06) or VSR WREN (0x50).\n+ */\n+ if (!s->write_enable && !s->volatile_write_enable) {\n+ qemu_log_mask(LOG_GUEST_ERROR,\n+ \"M25P80: Status register 2 write is disabled!\\n\");\n+ break;\n+ }\n s->needed_bytes = 1;\n s->state = STATE_COLLECTING_DATA;\n s->pos = 0;\n@@ -1332,6 +1349,16 @@ static void decode_new_cmd(Flash *s, uint32_t value)\n s->write_enable = true;\n break;\n \n+ case VSR_WREN:\n+ switch (get_man(s)) {\n+ case MAN_WINBOND:\n+ s->volatile_write_enable = true;\n+ break;\n+ default:\n+ break;\n+ }\n+ break;\n+\n case RDSR:\n s->data[0] = (!!s->write_enable) << 1;\n s->data[0] |= (!!s->status_register_write_disabled) << 7;\n@@ -1824,8 +1851,8 @@ static const VMStateDescription vmstate_m25p80_block_protect = {\n \n static const VMStateDescription vmstate_m25p80 = {\n .name = \"m25p80\",\n- .version_id = 0,\n- .minimum_version_id = 0,\n+ .version_id = 1,\n+ .minimum_version_id = 1,\n .pre_save = m25p80_pre_save,\n .pre_load = m25p80_pre_load,\n .fields = (const VMStateField[]) {\n@@ -1837,6 +1864,7 @@ static const VMStateDescription vmstate_m25p80 = {\n VMSTATE_UINT8(cmd_in_progress, Flash),\n VMSTATE_UINT32(cur_addr, Flash),\n VMSTATE_BOOL(write_enable, Flash),\n+ VMSTATE_BOOL(volatile_write_enable, Flash),\n VMSTATE_BOOL(reset_enable, Flash),\n VMSTATE_UINT8(ear, Flash),\n VMSTATE_BOOL(four_bytes_address_mode, Flash),\n", "prefixes": [ "v4", "14/21" ] }