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GET /api/1.2/patches/2224183/?format=api
{ "id": 2224183, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2224183/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260417032837.2664122-5-jamin_lin@aspeedtech.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.2/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260417032837.2664122-5-jamin_lin@aspeedtech.com>", "list_archive_url": null, "date": "2026-04-17T03:28:43", "name": "[v4,04/21] hw/arm/ast27x0: Start TSP in powered-off state to match hardware behavior", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "3b7dc7c344b9f81e86f75361472ee543f8385010", "submitter": { "id": 81768, "url": "http://patchwork.ozlabs.org/api/1.2/people/81768/?format=api", "name": "Jamin Lin", "email": "jamin_lin@aspeedtech.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260417032837.2664122-5-jamin_lin@aspeedtech.com/mbox/", "series": [ { "id": 500228, "url": "http://patchwork.ozlabs.org/api/1.2/series/500228/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500228", "date": "2026-04-17T03:28:41", "name": "Add SSP/TSP power control and DRAM remap support for AST2700", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/500228/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2224183/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2224183/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=aspeedtech.com header.i=@aspeedtech.com\n header.a=rsa-sha256 header.s=selector1 header.b=YDImcAdI;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;\n s=arcselector10001;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1;\n bh=14vDysdaVQ5MIdNZeJNc8+7z29whl9gMON17QSCxlSM=;\n b=Ens9sBe35iEIKWefPmwkDpQi1E6bdH51/u7ExKM9f96IVZm1nhQQp6eANoI6IN3SyFnhmk3kCMnOJJADw0PB3taeIjfrzHo4Q/1UHvWch3YDH1TVVl9GeY99pWhDiM1HYQJamMQ9g3u1tPmWBH2oteA+D9uTGUCNRN90iGADXtmOVzSpc22brHMkJ/DjRd3DdUXoGB8w+uv/tqQRUdkjzPMDskE9nQQtWcpg+OW2vvq/HOKpuw87meNQ/6nZ+I7FAcAD9L1FiE44mU/rFWFnMQ5XdXiBytXlJG+y/27iG2tJ0N4AOSgosFHVizrDbOwepsjTVoC60Gj4i3kd8Re2eQ==", "ARC-Authentication-Results": "i=1; mx.microsoft.com 1; spf=pass\n smtp.mailfrom=aspeedtech.com; dmarc=pass action=none\n header.from=aspeedtech.com; dkim=pass header.d=aspeedtech.com; arc=none", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=aspeedtech.com;\n s=selector1;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=14vDysdaVQ5MIdNZeJNc8+7z29whl9gMON17QSCxlSM=;\n b=YDImcAdI7cw781fFJNoSzm8tNcofvI4K9r1OEXvxMZI4n/FHWyQOt3ggISEnDCiS5yH6TUx7LwIyWXOt8+aJ2JEDJqoI+wt7FnujR5BOnG2mq6aVxm5rcmCTyqfMAYpmrIG6llc6+JWvmrZ5DrnuHMaibovY7H65+FEyZyWU07Nfnjuy6Ai7BDoRkBWgYSFfVNWJmH1WXLsQUbbh5XJheZXry48E1lZ1pQ6wiGuTzA80zViC0JCqu7I9q3H4UsRd9jKm+hfMCM7skt6Si8Okb8bM3nzKwhHK8Z6wz+meU8avsw3SKv+cmT+4UpJSp/gZcfBi7xuvLSE4YmNQ4zpxxQ==", "From": "Jamin Lin <jamin_lin@aspeedtech.com>", "To": "=?iso-8859-1?q?C=E9dric_Le_Goater?= <clg@kaod.org>,\n Peter Maydell <peter.maydell@linaro.org>,\n Steven Lee <steven_lee@aspeedtech.com>, Troy Lee <leetroy@gmail.com>,\n Kane Chen <kane_chen@aspeedtech.com>,\n Andrew Jeffery <andrew@codeconstruct.com.au>, Joel Stanley <joel@jms.id.au>,\n Pierrick Bouvier <pierrick.bouvier@linaro.org>,\n Alistair Francis <alistair@alistair23.me>, Kevin Wolf <kwolf@redhat.com>,\n Hanna Reitz <hreitz@redhat.com>,\n \"open list:ASPEED BMCs\" <qemu-arm@nongnu.org>,\n \"open list:All patches CC here\" <qemu-devel@nongnu.org>,\n \"open list:Block layer core\" <qemu-block@nongnu.org>", "CC": "Jamin Lin <jamin_lin@aspeedtech.com>, Troy Lee <troy_lee@aspeedtech.com>", "Subject": "[PATCH v4 04/21] hw/arm/ast27x0: Start TSP in powered-off state to\n match hardware behavior", "Thread-Topic": "[PATCH v4 04/21] hw/arm/ast27x0: Start TSP in powered-off state\n to match hardware behavior", "Thread-Index": "AQHczhpLpiyZnPziN0KYqhzBqDKf3g==", "Date": "Fri, 17 Apr 2026 03:28:43 +0000", "Message-ID": "<20260417032837.2664122-5-jamin_lin@aspeedtech.com>", "References": "<20260417032837.2664122-1-jamin_lin@aspeedtech.com>", "In-Reply-To": "<20260417032837.2664122-1-jamin_lin@aspeedtech.com>", "Accept-Language": "zh-TW, en-US", "Content-Language": "en-US", "X-MS-Has-Attach": "", "X-MS-TNEF-Correlator": "", "authentication-results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=aspeedtech.com header.i=@aspeedtech.com\n header.a=rsa-sha256 header.s=selector1 header.b=YDImcAdI;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=\"iso-8859-1\"", "Content-Transfer-Encoding": "quoted-printable", "MIME-Version": "1.0", "X-Exchange-RoutingPolicyChecked": "\n OhVzPWmSnMEdjn6y17VwehxKa1k+ifQJc9Z0mX95gGcCdEhL/yEUExHXK8kF0CGULbjc6eOWw0m/sDRAqdWukn/vE7iDHb5zPAEths0s/28FbTbHJNRkcmC7vP0jGq9GsYlPNjhCF6+SqBT2MI3d7PNa1tjMVFfupq+x4bDYvJrex8SvNQ2c3s2Efq4vSHyWpF75vVETK5P3firV0DdPSnqFtaHBSWppg7mIXXfQlTNqrNh7C8iNQhYN5CezgRZfm0QfihejQedVtRqzz4mo6VFAHMwk2Diub6rxitY4hGgg986OLmKWkouizYvYrEhSQnzekKc8lCPVXt7YtnEaNQ==", "X-OriginatorOrg": "aspeedtech.com", "X-MS-Exchange-CrossTenant-AuthAs": "Internal", "X-MS-Exchange-CrossTenant-AuthSource": "TYPPR06MB8206.apcprd06.prod.outlook.com", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 01636023-00fb-4f7d-04ee-08de9c316db3", "X-MS-Exchange-CrossTenant-originalarrivaltime": "17 Apr 2026 03:28:44.0353 (UTC)", "X-MS-Exchange-CrossTenant-fromentityheader": "Hosted", "X-MS-Exchange-CrossTenant-id": "43d4aa98-e35b-4575-8939-080e90d5a249", "X-MS-Exchange-CrossTenant-mailboxtype": "HOSTED", "X-MS-Exchange-CrossTenant-userprincipalname": "\n M2N1PknxUMDqI7mFHu+V65XtMsD/SqucOtR7N+81d+qs3ej5FEdbjQ1CUn3SY4jy6U3XqjA5QNJ781J9AXDnVS77ii1+GsdRsBUpSWUwxhg=", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "KL1PR06MB6299", "Received-SPF": "pass client-ip=2a01:111:f403:c405::7;\n envelope-from=jamin_lin@aspeedtech.com;\n helo=TYDPR03CU002.outbound.protection.outlook.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "In the previous design, both the PSP and TSP were started together during\nSoC initialization. However, on real hardware, the TSP begins in a powered-off\nstate. The typical boot sequence involves the PSP powering up first, loading\nthe TSP firmware binary into shared memory via DRAM remap, and then releasing\nthe TSP reset and enabling it through SCU control registers.\n\nTo more accurately model this behavior in QEMU, this commit sets the\n\"start-powered-off\" property for the TSP's ARMv7M core. This change ensures\nthe TSP remains off until explicitly enabled via the SCU, simulating the\nreal-world flow where the PSP controls TSP boot through SCU interaction.\n\nSigned-off-by: Jamin Lin <jamin_lin@aspeedtech.com>\n---\n hw/arm/aspeed_ast27x0-tsp.c | 7 +++++++\n 1 file changed, 7 insertions(+)", "diff": "diff --git a/hw/arm/aspeed_ast27x0-tsp.c b/hw/arm/aspeed_ast27x0-tsp.c\nindex 674307103e..b30f2afd62 100644\n--- a/hw/arm/aspeed_ast27x0-tsp.c\n+++ b/hw/arm/aspeed_ast27x0-tsp.c\n@@ -166,6 +166,13 @@ static void aspeed_soc_ast27x0tsp_realize(DeviceState *dev_soc, Error **errp)\n qdev_connect_clock_in(armv7m, \"cpuclk\", s->sysclk);\n object_property_set_link(OBJECT(&a->armv7m), \"memory\",\n OBJECT(s->memory), &error_abort);\n+ /*\n+ * The TSP starts in a powered-down state and can be powered up\n+ * by setting the TSP Control Register through the SCU\n+ * (System Control Unit)\n+ */\n+ object_property_set_bool(OBJECT(&a->armv7m), \"start-powered-off\", true,\n+ &error_abort);\n sysbus_realize(SYS_BUS_DEVICE(&a->armv7m), &error_abort);\n \n /* SDRAM */\n", "prefixes": [ "v4", "04/21" ] }