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GET /api/1.2/patches/2223497/?format=api
{ "id": 2223497, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2223497/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20260415-ipq9650_tlmm-v1-2-bd16ccb06332@oss.qualcomm.com/", "project": { "id": 42, "url": "http://patchwork.ozlabs.org/api/1.2/projects/42/?format=api", "name": "Linux GPIO development", "link_name": "linux-gpio", "list_id": "linux-gpio.vger.kernel.org", "list_email": "linux-gpio@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260415-ipq9650_tlmm-v1-2-bd16ccb06332@oss.qualcomm.com>", "list_archive_url": null, "date": "2026-04-15T11:29:25", "name": "[2/2] pinctrl: qcom: Introduce IPQ9650 TLMM driver", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "87be392bebad89e2e3c4f2d7fde0ed7d04e479bc", "submitter": { "id": 90386, "url": "http://patchwork.ozlabs.org/api/1.2/people/90386/?format=api", "name": "Kathiravan Thirumoorthy", "email": "kathiravan.thirumoorthy@oss.qualcomm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20260415-ipq9650_tlmm-v1-2-bd16ccb06332@oss.qualcomm.com/mbox/", "series": [ { "id": 499978, "url": "http://patchwork.ozlabs.org/api/1.2/series/499978/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/list/?series=499978", "date": "2026-04-15T11:29:23", "name": "Introduce TLMM driver for Qualcomm IPQ9650 SoC", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/499978/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2223497/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2223497/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-gpio+bounces-35168-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-gpio@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=lWzpPdW9;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=Tq+Mf4oO;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.234.253.10; helo=sea.lore.kernel.org;\n envelope-from=linux-gpio+bounces-35168-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)", "smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com\n header.b=\"lWzpPdW9\";\n\tdkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.b=\"Tq+Mf4oO\"", "smtp.subspace.kernel.org;\n arc=none smtp.client-ip=205.220.180.131", "smtp.subspace.kernel.org;\n dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com", "smtp.subspace.kernel.org;\n spf=pass smtp.mailfrom=oss.qualcomm.com" ], "Received": [ "from sea.lore.kernel.org (sea.lore.kernel.org [172.234.253.10])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fwfGq3NqWz1yCv\n\tfor <incoming@patchwork.ozlabs.org>; Wed, 15 Apr 2026 21:36:03 +1000 (AEST)", "from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby sea.lore.kernel.org (Postfix) with ESMTP id BF4693051C8D\n\tfor <incoming@patchwork.ozlabs.org>; Wed, 15 Apr 2026 11:30:29 +0000 (UTC)", "from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id 12DA237C108;\n\tWed, 15 Apr 2026 11:29:55 +0000 (UTC)", "from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com\n [205.220.180.131])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby smtp.subspace.kernel.org (Postfix) with ESMTPS id B657D37FF47\n\tfor <linux-gpio@vger.kernel.org>; Wed, 15 Apr 2026 11:29:52 +0000 (UTC)", "from pps.filterd (m0279871.ppops.net [127.0.0.1])\n\tby mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id\n 63FACeGr1701741\n\tfor <linux-gpio@vger.kernel.org>; Wed, 15 Apr 2026 11:29:51 GMT", "from mail-pg1-f198.google.com (mail-pg1-f198.google.com\n [209.85.215.198])\n\tby mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4dht56u123-1\n\t(version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT)\n\tfor <linux-gpio@vger.kernel.org>; Wed, 15 Apr 2026 11:29:51 +0000 (GMT)", "by mail-pg1-f198.google.com with SMTP id\n 41be03b00d2f7-c70f19f0f37so159596a12.0\n for <linux-gpio@vger.kernel.org>;\n Wed, 15 Apr 2026 04:29:51 -0700 (PDT)", "from hu-kathirav-blr.qualcomm.com\n (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com. 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charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-Id": "<20260415-ipq9650_tlmm-v1-2-bd16ccb06332@oss.qualcomm.com>", "References": "<20260415-ipq9650_tlmm-v1-0-bd16ccb06332@oss.qualcomm.com>", "In-Reply-To": "<20260415-ipq9650_tlmm-v1-0-bd16ccb06332@oss.qualcomm.com>", "To": "Bjorn Andersson <andersson@kernel.org>, Linus Walleij <linusw@kernel.org>,\n Rob Herring <robh@kernel.org>,\n Krzysztof Kozlowski <krzk+dt@kernel.org>,\n Conor Dooley <conor+dt@kernel.org>", "Cc": "linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org,\n devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,\n Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>", "X-Mailer": "b4 0.15.0", "X-Developer-Signature": "v=1; a=ed25519-sha256; t=1776252577; l=25436;\n i=kathiravan.thirumoorthy@oss.qualcomm.com; s=20230906;\n h=from:subject:message-id; bh=ev7gbVNG1XMt1Wso0pyHEd0CTSpOAX78sTj7lRrAqmg=;\n b=Ih5mKiQT6uX6BZm99vvuHVe4aGHnv0o/Nxx9tNqSfus3rNmFSf96bcqk0ly3Q1JTSMitan4R5\n 5pqsZAQ6fpmDeQIewxjt5b6sycyjWrfVlI9XiE0f3NlW4f1DUMuKnVe", "X-Developer-Key": "i=kathiravan.thirumoorthy@oss.qualcomm.com; a=ed25519;\n pk=xWsR7pL6ch+vdZ9MoFGEaP61JUaRf0XaZYWztbQsIiM=", "X-Proofpoint-ORIG-GUID": "ePxAvpf_9x6ft3oq32QPNNr9-TTr35__", "X-Proofpoint-GUID": "ePxAvpf_9x6ft3oq32QPNNr9-TTr35__", "X-Authority-Analysis": "v=2.4 cv=K9gS2SWI c=1 sm=1 tr=0 ts=69df76af cx=c_pps\n a=Qgeoaf8Lrialg5Z894R3/Q==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17\n a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10\n a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=3WHJM1ZQz_JShphwDgj5:22\n a=EUspDBNiAAAA:8 a=9BfRLheWMJIugVHxdQMA:9 a=QEXdDO2ut3YA:10 a=O8hF6Hzn-FEA:10\n a=x9snwWr2DeNwDh03kgHS:22", "X-Proofpoint-Spam-Details-Enc": "AW1haW4tMjYwNDE1MDEwNSBTYWx0ZWRfX0LVE8bfIskLo\n AF0lUbS+zqw4NQLHvBCbVscdK2ptxlicE+8eAWSoLlvaZxiv2MCz986Dhy7yXcnJxxr2G7eQXcK\n CaefIQCwm7W1drGqyPbm2g/jPnssVkmvYEy/FjOVGWi5RVlwbKm316v4Xb65JZexIIKb/Q0bN53\n nq1ml6Y3DpY6roXgXthUYeSpDZSaxWWXb9zFXxneA0hn+rB3dB6Na6fSTkzuDMKlRzWJjkobSvQ\n unD7oDAqYpsw6VPslUM6FF7uyQxOXTY20rGveAS9Quga92kA9MqXDyPLDJMkgpfAQ5ES5nEgKV+\n 0R1JHXKyguTKAMG1GTSyVIgdWgFWAVt9fhliJ8f83xhNJ//uk+HTnUMSvrAF+PycWysSfSNwoZt\n e3zw42/93yugSZKFpEXgUJd3y9C+TMqJ9mq6SpJUaVCrKpbWUnnWKQlU3gFN+cyZp0FFxPDAVsq\n S8tsavLfbn+SkYdGQhQ==", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-04-14_04,2026-04-13_04,2025-10-01_01", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n lowpriorityscore=0 impostorscore=0 suspectscore=0 malwarescore=0\n priorityscore=1501 spamscore=0 clxscore=1015 phishscore=0 bulkscore=0\n adultscore=0 classifier=typeunknown authscore=0 authtc= authcc=\n route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604070000\n definitions=main-2604150105" }, "content": "Qualcomm's IPQ9650 comes with a TLMM block, like all other platforms,\nso add a driver for it.\n\nSigned-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>\n---\n drivers/pinctrl/qcom/Kconfig.msm | 9 +\n drivers/pinctrl/qcom/Makefile | 1 +\n drivers/pinctrl/qcom/pinctrl-ipq9650.c | 762 +++++++++++++++++++++++++++++++++\n 3 files changed, 772 insertions(+)", "diff": "diff --git a/drivers/pinctrl/qcom/Kconfig.msm b/drivers/pinctrl/qcom/Kconfig.msm\nindex 836cdeca1006..0d6f698e26ec 100644\n--- a/drivers/pinctrl/qcom/Kconfig.msm\n+++ b/drivers/pinctrl/qcom/Kconfig.msm\n@@ -120,6 +120,15 @@ config PINCTRL_IPQ9574\n Qualcomm Technologies Inc. IPQ9574 platform. Select this for\n IPQ9574.\n \n+config PINCTRL_IPQ9650\n+\ttristate \"Qualcomm Technologies, Inc. IPQ9650 pin controller driver\"\n+\tdepends on ARM64 || COMPILE_TEST\n+\thelp\n+\t This is the pinctrl, pinmux, pinconf and gpiolib driver for\n+ the Qualcomm Technologies Inc. TLMM block found on the\n+ Qualcomm Technologies Inc. IPQ9650 platform. Select this for\n+ IPQ9650.\n+\n config PINCTRL_KAANAPALI\n \ttristate \"Qualcomm Technologies Inc Kaanapali pin controller driver\"\n \tdepends on ARM64 || COMPILE_TEST\ndiff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile\nindex 84bda3ada874..f0bb1920b27b 100644\n--- a/drivers/pinctrl/qcom/Makefile\n+++ b/drivers/pinctrl/qcom/Makefile\n@@ -15,6 +15,7 @@ obj-$(CONFIG_PINCTRL_IPQ5424)\t+= pinctrl-ipq5424.o\n obj-$(CONFIG_PINCTRL_IPQ8074)\t+= pinctrl-ipq8074.o\n obj-$(CONFIG_PINCTRL_IPQ6018)\t+= pinctrl-ipq6018.o\n obj-$(CONFIG_PINCTRL_IPQ9574)\t+= pinctrl-ipq9574.o\n+obj-$(CONFIG_PINCTRL_IPQ9650)\t+= pinctrl-ipq9650.o\n obj-$(CONFIG_PINCTRL_KAANAPALI) += pinctrl-kaanapali.o\n obj-$(CONFIG_PINCTRL_MSM8226)\t+= pinctrl-msm8226.o\n obj-$(CONFIG_PINCTRL_MSM8660)\t+= pinctrl-msm8660.o\ndiff --git a/drivers/pinctrl/qcom/pinctrl-ipq9650.c b/drivers/pinctrl/qcom/pinctrl-ipq9650.c\nnew file mode 100644\nindex 000000000000..64e443aa31b2\n--- /dev/null\n+++ b/drivers/pinctrl/qcom/pinctrl-ipq9650.c\n@@ -0,0 +1,762 @@\n+// SPDX-License-Identifier: GPL-2.0-only\n+/*\n+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.\n+ */\n+\n+#include <linux/module.h>\n+#include <linux/of.h>\n+#include <linux/platform_device.h>\n+\n+#include \"pinctrl-msm.h\"\n+\n+#define REG_SIZE 0x1000\n+#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9)\t \\\n+\t{ \\\n+\t\t.grp = PINCTRL_PINGROUP(\"gpio\" #id, \\\n+\t\t\t\t\tgpio##id##_pins, \\\n+\t\t\t\t\tARRAY_SIZE(gpio##id##_pins)), \\\n+\t\t.ctl_reg = REG_SIZE * id, \\\n+\t\t.io_reg = 0x4 + REG_SIZE * id, \\\n+\t\t.intr_cfg_reg = 0x8 + REG_SIZE * id, \\\n+\t\t.intr_status_reg = 0xc + REG_SIZE * id, \\\n+\t\t.mux_bit = 2, \\\n+\t\t.pull_bit = 0, \\\n+\t\t.drv_bit = 6, \\\n+\t\t.oe_bit = 9, \\\n+\t\t.in_bit = 0, \\\n+\t\t.out_bit = 1, \\\n+\t\t.intr_enable_bit = 0, \\\n+\t\t.intr_status_bit = 0, \\\n+\t\t.intr_target_bit = 5, \\\n+\t\t.intr_target_kpss_val = 3, \\\n+\t\t.intr_raw_status_bit = 4, \\\n+\t\t.intr_polarity_bit = 1, \\\n+\t\t.intr_detection_bit = 2, \\\n+\t\t.intr_detection_width = 2, \\\n+\t\t.funcs = (int[]){ \\\n+\t\t\tmsm_mux_gpio, /* gpio mode */ \\\n+\t\t\tmsm_mux_##f1, \\\n+\t\t\tmsm_mux_##f2, \\\n+\t\t\tmsm_mux_##f3, \\\n+\t\t\tmsm_mux_##f4, \\\n+\t\t\tmsm_mux_##f5, \\\n+\t\t\tmsm_mux_##f6, \\\n+\t\t\tmsm_mux_##f7, \\\n+\t\t\tmsm_mux_##f8, \\\n+\t\t\tmsm_mux_##f9, \\\n+\t\t}, \\\n+\t\t.nfuncs = 10, \\\n+\t}\n+\n+static const struct pinctrl_pin_desc ipq9650_pins[] = {\n+\tPINCTRL_PIN(0, \"GPIO_0\"),\n+\tPINCTRL_PIN(1, \"GPIO_1\"),\n+\tPINCTRL_PIN(2, \"GPIO_2\"),\n+\tPINCTRL_PIN(3, \"GPIO_3\"),\n+\tPINCTRL_PIN(4, \"GPIO_4\"),\n+\tPINCTRL_PIN(5, \"GPIO_5\"),\n+\tPINCTRL_PIN(6, \"GPIO_6\"),\n+\tPINCTRL_PIN(7, \"GPIO_7\"),\n+\tPINCTRL_PIN(8, \"GPIO_8\"),\n+\tPINCTRL_PIN(9, \"GPIO_9\"),\n+\tPINCTRL_PIN(10, \"GPIO_10\"),\n+\tPINCTRL_PIN(11, \"GPIO_11\"),\n+\tPINCTRL_PIN(12, \"GPIO_12\"),\n+\tPINCTRL_PIN(13, \"GPIO_13\"),\n+\tPINCTRL_PIN(14, \"GPIO_14\"),\n+\tPINCTRL_PIN(15, \"GPIO_15\"),\n+\tPINCTRL_PIN(16, \"GPIO_16\"),\n+\tPINCTRL_PIN(17, \"GPIO_17\"),\n+\tPINCTRL_PIN(18, \"GPIO_18\"),\n+\tPINCTRL_PIN(19, \"GPIO_19\"),\n+\tPINCTRL_PIN(20, \"GPIO_20\"),\n+\tPINCTRL_PIN(21, \"GPIO_21\"),\n+\tPINCTRL_PIN(22, \"GPIO_22\"),\n+\tPINCTRL_PIN(23, \"GPIO_23\"),\n+\tPINCTRL_PIN(24, \"GPIO_24\"),\n+\tPINCTRL_PIN(25, \"GPIO_25\"),\n+\tPINCTRL_PIN(26, \"GPIO_26\"),\n+\tPINCTRL_PIN(27, \"GPIO_27\"),\n+\tPINCTRL_PIN(28, \"GPIO_28\"),\n+\tPINCTRL_PIN(29, \"GPIO_29\"),\n+\tPINCTRL_PIN(30, \"GPIO_30\"),\n+\tPINCTRL_PIN(31, \"GPIO_31\"),\n+\tPINCTRL_PIN(32, \"GPIO_32\"),\n+\tPINCTRL_PIN(33, \"GPIO_33\"),\n+\tPINCTRL_PIN(34, \"GPIO_34\"),\n+\tPINCTRL_PIN(35, \"GPIO_35\"),\n+\tPINCTRL_PIN(36, \"GPIO_36\"),\n+\tPINCTRL_PIN(37, \"GPIO_37\"),\n+\tPINCTRL_PIN(38, \"GPIO_38\"),\n+\tPINCTRL_PIN(39, \"GPIO_39\"),\n+\tPINCTRL_PIN(40, \"GPIO_40\"),\n+\tPINCTRL_PIN(41, \"GPIO_41\"),\n+\tPINCTRL_PIN(42, \"GPIO_42\"),\n+\tPINCTRL_PIN(43, \"GPIO_43\"),\n+\tPINCTRL_PIN(44, \"GPIO_44\"),\n+\tPINCTRL_PIN(45, \"GPIO_45\"),\n+\tPINCTRL_PIN(46, \"GPIO_46\"),\n+\tPINCTRL_PIN(47, \"GPIO_47\"),\n+\tPINCTRL_PIN(48, \"GPIO_48\"),\n+\tPINCTRL_PIN(49, \"GPIO_49\"),\n+\tPINCTRL_PIN(50, \"GPIO_50\"),\n+\tPINCTRL_PIN(51, \"GPIO_51\"),\n+\tPINCTRL_PIN(52, \"GPIO_52\"),\n+\tPINCTRL_PIN(53, \"GPIO_53\"),\n+};\n+\n+#define DECLARE_MSM_GPIO_PINS(pin) \\\n+\tstatic const unsigned int gpio##pin##_pins[] = { pin }\n+DECLARE_MSM_GPIO_PINS(0);\n+DECLARE_MSM_GPIO_PINS(1);\n+DECLARE_MSM_GPIO_PINS(2);\n+DECLARE_MSM_GPIO_PINS(3);\n+DECLARE_MSM_GPIO_PINS(4);\n+DECLARE_MSM_GPIO_PINS(5);\n+DECLARE_MSM_GPIO_PINS(6);\n+DECLARE_MSM_GPIO_PINS(7);\n+DECLARE_MSM_GPIO_PINS(8);\n+DECLARE_MSM_GPIO_PINS(9);\n+DECLARE_MSM_GPIO_PINS(10);\n+DECLARE_MSM_GPIO_PINS(11);\n+DECLARE_MSM_GPIO_PINS(12);\n+DECLARE_MSM_GPIO_PINS(13);\n+DECLARE_MSM_GPIO_PINS(14);\n+DECLARE_MSM_GPIO_PINS(15);\n+DECLARE_MSM_GPIO_PINS(16);\n+DECLARE_MSM_GPIO_PINS(17);\n+DECLARE_MSM_GPIO_PINS(18);\n+DECLARE_MSM_GPIO_PINS(19);\n+DECLARE_MSM_GPIO_PINS(20);\n+DECLARE_MSM_GPIO_PINS(21);\n+DECLARE_MSM_GPIO_PINS(22);\n+DECLARE_MSM_GPIO_PINS(23);\n+DECLARE_MSM_GPIO_PINS(24);\n+DECLARE_MSM_GPIO_PINS(25);\n+DECLARE_MSM_GPIO_PINS(26);\n+DECLARE_MSM_GPIO_PINS(27);\n+DECLARE_MSM_GPIO_PINS(28);\n+DECLARE_MSM_GPIO_PINS(29);\n+DECLARE_MSM_GPIO_PINS(30);\n+DECLARE_MSM_GPIO_PINS(31);\n+DECLARE_MSM_GPIO_PINS(32);\n+DECLARE_MSM_GPIO_PINS(33);\n+DECLARE_MSM_GPIO_PINS(34);\n+DECLARE_MSM_GPIO_PINS(35);\n+DECLARE_MSM_GPIO_PINS(36);\n+DECLARE_MSM_GPIO_PINS(37);\n+DECLARE_MSM_GPIO_PINS(38);\n+DECLARE_MSM_GPIO_PINS(39);\n+DECLARE_MSM_GPIO_PINS(40);\n+DECLARE_MSM_GPIO_PINS(41);\n+DECLARE_MSM_GPIO_PINS(42);\n+DECLARE_MSM_GPIO_PINS(43);\n+DECLARE_MSM_GPIO_PINS(44);\n+DECLARE_MSM_GPIO_PINS(45);\n+DECLARE_MSM_GPIO_PINS(46);\n+DECLARE_MSM_GPIO_PINS(47);\n+DECLARE_MSM_GPIO_PINS(48);\n+DECLARE_MSM_GPIO_PINS(49);\n+DECLARE_MSM_GPIO_PINS(50);\n+DECLARE_MSM_GPIO_PINS(51);\n+DECLARE_MSM_GPIO_PINS(52);\n+DECLARE_MSM_GPIO_PINS(53);\n+\n+enum ipq9650_functions {\n+\tmsm_mux_atest_char_start,\n+\tmsm_mux_atest_char_status0,\n+\tmsm_mux_atest_char_status1,\n+\tmsm_mux_atest_char_status2,\n+\tmsm_mux_atest_char_status3,\n+\tmsm_mux_atest_tic_en,\n+\tmsm_mux_audio_pri_mclk_in0,\n+\tmsm_mux_audio_pri_mclk_out0,\n+\tmsm_mux_audio_pri_mclk_in1,\n+\tmsm_mux_audio_pri_mclk_out1,\n+\tmsm_mux_audio_pri,\n+\tmsm_mux_audio_sec,\n+\tmsm_mux_audio_sec_mclk_in0,\n+\tmsm_mux_audio_sec_mclk_out0,\n+\tmsm_mux_audio_sec_mclk_in1,\n+\tmsm_mux_audio_sec_mclk_out1,\n+\tmsm_mux_core_voltage_0,\n+\tmsm_mux_core_voltage_1,\n+\tmsm_mux_core_voltage_2,\n+\tmsm_mux_core_voltage_3,\n+\tmsm_mux_core_voltage_4,\n+\tmsm_mux_cri_rng0,\n+\tmsm_mux_cri_rng1,\n+\tmsm_mux_cri_rng2,\n+\tmsm_mux_dbg_out_clk,\n+\tmsm_mux_gcc_plltest_bypassnl,\n+\tmsm_mux_gcc_plltest_resetn,\n+\tmsm_mux_gcc_tlmm,\n+\tmsm_mux_gpio,\n+\tmsm_mux_mdc_mst,\n+\tmsm_mux_mdc_slv0,\n+\tmsm_mux_mdc_slv1,\n+\tmsm_mux_mdio_mst,\n+\tmsm_mux_mdio_slv,\n+\tmsm_mux_mdio_slv0,\n+\tmsm_mux_mdio_slv1,\n+\tmsm_mux_pcie0_clk_req_n,\n+\tmsm_mux_pcie0_wake,\n+\tmsm_mux_pcie1_clk_req_n,\n+\tmsm_mux_pcie1_wake,\n+\tmsm_mux_pcie2_clk_req_n,\n+\tmsm_mux_pcie2_wake,\n+\tmsm_mux_pcie3_clk_req_n,\n+\tmsm_mux_pcie3_wake,\n+\tmsm_mux_pcie4_clk_req_n,\n+\tmsm_mux_pcie4_wake,\n+\tmsm_mux_pll_bist_sync,\n+\tmsm_mux_pll_test,\n+\tmsm_mux_pwm,\n+\tmsm_mux_qdss_cti_trig_in_a0,\n+\tmsm_mux_qdss_cti_trig_in_a1,\n+\tmsm_mux_qdss_cti_trig_in_b0,\n+\tmsm_mux_qdss_cti_trig_in_b1,\n+\tmsm_mux_qdss_cti_trig_out_a0,\n+\tmsm_mux_qdss_cti_trig_out_a1,\n+\tmsm_mux_qdss_cti_trig_out_b0,\n+\tmsm_mux_qdss_cti_trig_out_b1,\n+\tmsm_mux_qdss_traceclk_a,\n+\tmsm_mux_qdss_tracectl_a,\n+\tmsm_mux_qdss_tracedata_a,\n+\tmsm_mux_qspi_data,\n+\tmsm_mux_qspi_clk,\n+\tmsm_mux_qspi_cs_n,\n+\tmsm_mux_qup_se0,\n+\tmsm_mux_qup_se1,\n+\tmsm_mux_qup_se2,\n+\tmsm_mux_qup_se3,\n+\tmsm_mux_qup_se4,\n+\tmsm_mux_qup_se5,\n+\tmsm_mux_qup_se6,\n+\tmsm_mux_qup_se7,\n+\tmsm_mux_resout,\n+\tmsm_mux_rx_los0,\n+\tmsm_mux_rx_los1,\n+\tmsm_mux_rx_los2,\n+\tmsm_mux_sdc_clk,\n+\tmsm_mux_sdc_cmd,\n+\tmsm_mux_sdc_data,\n+\tmsm_mux_tsens_max,\n+\tmsm_mux_tsn,\n+\tmsm_mux__,\n+};\n+\n+static const char *const gpio_groups[] = {\n+\t\"gpio0\", \"gpio1\", \"gpio2\", \"gpio3\",\t\"gpio4\", \"gpio5\", \"gpio6\",\n+\t\"gpio7\", \"gpio8\", \"gpio9\", \"gpio10\", \"gpio11\", \"gpio12\", \"gpio13\",\n+\t\"gpio14\", \"gpio15\", \"gpio16\", \"gpio17\", \"gpio18\", \"gpio19\", \"gpio20\",\n+\t\"gpio21\", \"gpio22\", \"gpio23\", \"gpio24\", \"gpio25\", \"gpio26\", \"gpio27\",\n+\t\"gpio28\", \"gpio29\", \"gpio30\", \"gpio31\", \"gpio32\", \"gpio33\", \"gpio34\",\n+\t\"gpio35\", \"gpio36\", \"gpio37\", \"gpio38\", \"gpio39\", \"gpio40\", \"gpio41\",\n+\t\"gpio42\", \"gpio43\", \"gpio44\", \"gpio45\", \"gpio46\", \"gpio47\", \"gpio48\",\n+\t\"gpio49\", \"gpio50\", \"gpio51\", \"gpio52\", \"gpio53\",\n+};\n+\n+static const char *const atest_char_start_groups[] = {\n+\t\"gpio21\",\n+};\n+\n+static const char *const atest_char_status0_groups[] = {\n+\t\"gpio33\",\n+};\n+\n+static const char *const atest_char_status1_groups[] = {\n+\t\"gpio35\",\n+};\n+\n+static const char *const atest_char_status2_groups[] = {\n+\t\"gpio22\",\n+};\n+\n+static const char *const atest_char_status3_groups[] = {\n+\t\"gpio23\",\n+};\n+\n+static const char *const atest_tic_en_groups[] = {\n+\t\"gpio53\",\n+};\n+\n+static const char *const audio_pri_mclk_in0_groups[] = {\n+\t\"gpio53\",\n+};\n+\n+static const char *const audio_pri_mclk_out0_groups[] = {\n+\t\"gpio53\",\n+};\n+\n+static const char *const audio_pri_mclk_in1_groups[] = {\n+\t\"gpio51\",\n+};\n+\n+static const char *const audio_pri_mclk_out1_groups[] = {\n+\t\"gpio51\",\n+};\n+\n+static const char *const audio_pri_groups[] = {\n+\t\"gpio36\", \"gpio37\", \"gpio38\", \"gpio39\",\n+};\n+\n+static const char *const audio_sec_mclk_in0_groups[] = {\n+\t\"gpio37\",\n+};\n+\n+static const char *const audio_sec_mclk_out0_groups[] = {\n+\t\"gpio37\",\n+};\n+\n+static const char *const audio_sec_mclk_in1_groups[] = {\n+\t\"gpio37\",\n+};\n+\n+static const char *const audio_sec_mclk_out1_groups[] = {\n+\t\"gpio37\",\n+};\n+\n+static const char *const audio_sec_groups[] = {\n+\t\"gpio45\", \"gpio46\", \"gpio47\", \"gpio48\",\n+};\n+\n+static const char *const core_voltage_0_groups[] = {\n+\t\"gpio16\",\n+};\n+\n+static const char *const core_voltage_1_groups[] = {\n+\t\"gpio17\",\n+};\n+\n+static const char *const core_voltage_2_groups[] = {\n+\t\"gpio33\",\n+};\n+\n+static const char *const core_voltage_3_groups[] = {\n+\t\"gpio34\",\n+};\n+\n+static const char *const core_voltage_4_groups[] = {\n+\t\"gpio35\",\n+};\n+\n+static const char *const cri_rng0_groups[] = {\n+\t\"gpio6\",\n+};\n+\n+static const char *const cri_rng1_groups[] = {\n+\t\"gpio7\",\n+};\n+\n+static const char *const cri_rng2_groups[] = {\n+\t\"gpio8\",\n+};\n+\n+static const char *const dbg_out_clk_groups[] = {\n+\t\"gpio46\",\n+};\n+\n+static const char *const gcc_plltest_bypassnl_groups[] = {\n+\t\"gpio33\",\n+};\n+\n+static const char *const gcc_plltest_resetn_groups[] = {\n+\t\"gpio35\",\n+};\n+\n+static const char *const gcc_tlmm_groups[] = {\n+\t\"gpio34\",\n+};\n+\n+static const char *const mdc_mst_groups[] = {\n+\t\"gpio22\",\n+};\n+\n+static const char *const mdc_slv0_groups[] = {\n+\t\"gpio20\",\n+};\n+\n+static const char *const mdc_slv1_groups[] = {\n+\t\"gpio14\",\n+};\n+\n+static const char *const mdio_mst_groups[] = {\n+\t\"gpio23\",\n+};\n+\n+static const char *const mdio_slv_groups[] = {\n+\t\"gpio46\",\n+\t\"gpio47\",\n+};\n+\n+static const char *const mdio_slv0_groups[] = {\n+\t\"gpio21\",\n+};\n+\n+static const char *const mdio_slv1_groups[] = {\n+\t\"gpio15\",\n+};\n+\n+static const char *const pcie0_clk_req_n_groups[] = {\n+\t\"gpio24\",\n+};\n+\n+static const char *const pcie0_wake_groups[] = {\n+\t\"gpio26\",\n+};\n+\n+static const char *const pcie1_clk_req_n_groups[] = {\n+\t\"gpio27\",\n+};\n+\n+static const char *const pcie1_wake_groups[] = {\n+\t\"gpio29\",\n+};\n+\n+static const char *const pcie2_clk_req_n_groups[] = {\n+\t\"gpio51\",\n+};\n+\n+static const char *const pcie2_wake_groups[] = {\n+\t\"gpio53\",\n+};\n+\n+static const char *const pcie3_clk_req_n_groups[] = {\n+\t\"gpio40\",\n+};\n+\n+static const char *const pcie3_wake_groups[] = {\n+\t\"gpio42\",\n+};\n+\n+static const char *const pcie4_clk_req_n_groups[] = {\n+\t\"gpio30\",\n+};\n+\n+static const char *const pcie4_wake_groups[] = {\n+\t\"gpio32\",\n+};\n+\n+static const char *const pll_bist_sync_groups[] = {\n+\t\"gpio47\",\n+};\n+\n+static const char *const pll_test_groups[] = {\n+\t\"gpio39\",\n+};\n+\n+static const char *const pwm_groups[] = {\n+\t\"gpio6\", \"gpio7\", \"gpio8\", \"gpio9\", \"gpio10\", \"gpio11\", \"gpio16\",\n+\t\"gpio17\", \"gpio33\", \"gpio34\", \"gpio35\", \"gpio43\", \"gpio44\", \"gpio45\",\n+\t\"gpio46\", \"gpio47\", \"gpio48\",\n+};\n+\n+static const char *const qdss_cti_trig_in_a0_groups[] = {\n+\t\"gpio53\",\n+};\n+\n+static const char *const qdss_cti_trig_in_a1_groups[] = {\n+\t\"gpio29\",\n+};\n+\n+static const char *const qdss_cti_trig_in_b0_groups[] = {\n+\t\"gpio42\",\n+};\n+\n+static const char *const qdss_cti_trig_in_b1_groups[] = {\n+\t\"gpio43\",\n+};\n+\n+static const char *const qdss_cti_trig_out_a0_groups[] = {\n+\t\"gpio51\",\n+};\n+\n+static const char *const qdss_cti_trig_out_a1_groups[] = {\n+\t\"gpio27\",\n+};\n+\n+static const char *const qdss_cti_trig_out_b0_groups[] = {\n+\t\"gpio40\",\n+};\n+\n+static const char *const qdss_cti_trig_out_b1_groups[] = {\n+\t\"gpio44\",\n+};\n+\n+static const char *const qdss_traceclk_a_groups[] = {\n+\t\"gpio45\",\n+};\n+\n+static const char *const qdss_tracectl_a_groups[] = {\n+\t\"gpio46\",\n+};\n+\n+static const char *const qdss_tracedata_a_groups[] = {\n+\t\"gpio6\", \"gpio7\", \"gpio8\", \"gpio9\",\t\"gpio10\", \"gpio11\",\n+\t\"gpio12\", \"gpio13\", \"gpio14\", \"gpio15\", \"gpio20\", \"gpio21\",\n+\t\"gpio36\", \"gpio37\", \"gpio38\", \"gpio39\",\n+};\n+\n+static const char *const qspi_data_groups[] = {\n+\t\"gpio0\", \"gpio1\", \"gpio2\", \"gpio3\",\n+};\n+\n+static const char *const qspi_clk_groups[] = {\n+\t\"gpio5\",\n+};\n+\n+static const char *const qspi_cs_n_groups[] = {\n+\t\"gpio4\",\n+};\n+\n+static const char *const qup_se0_groups[] = {\n+\t\"gpio6\", \"gpio7\", \"gpio8\", \"gpio9\", \"gpio51\", \"gpio53\",\n+};\n+\n+static const char *const qup_se1_groups[] = {\n+\t\"gpio10\", \"gpio11\", \"gpio12\", \"gpio13\", \"gpio27\", \"gpio29\",\n+};\n+\n+static const char *const qup_se2_groups[] = {\n+\t\"gpio27\", \"gpio29\", \"gpio33\", \"gpio34\",\n+};\n+\n+static const char *const qup_se3_groups[] = {\n+\t\"gpio16\", \"gpio17\", \"gpio20\", \"gpio21\",\n+};\n+\n+static const char *const qup_se4_groups[] = {\n+\t\"gpio14\", \"gpio15\", \"gpio40\", \"gpio42\", \"gpio43\", \"gpio44\",\n+};\n+\n+static const char *const qup_se5_groups[] = {\n+\t\"gpio40\", \"gpio42\", \"gpio45\", \"gpio46\", \"gpio47\", \"gpio48\",\n+};\n+\n+static const char *const qup_se6_groups[] = {\n+\t\"gpio43\", \"gpio44\", \"gpio51\", \"gpio53\",\n+};\n+\n+static const char *const qup_se7_groups[] = {\n+\t\"gpio36\", \"gpio37\", \"gpio38\", \"gpio39\",\n+};\n+\n+static const char *const resout_groups[] = {\n+\t\"gpio49\",\n+};\n+\n+static const char *const rx_los0_groups[] = {\n+\t\"gpio39\", \"gpio47\", \"gpio50\",\n+};\n+\n+static const char *const rx_los1_groups[] = {\n+\t\"gpio38\", \"gpio46\",\n+};\n+\n+static const char *const rx_los2_groups[] = {\n+\t\"gpio37\", \"gpio45\",\n+};\n+\n+static const char *const sdc_clk_groups[] = {\n+\t\"gpio5\",\n+};\n+\n+static const char *const sdc_cmd_groups[] = {\n+\t\"gpio4\",\n+};\n+\n+static const char *const sdc_data_groups[] = {\n+\t\"gpio0\", \"gpio1\", \"gpio2\", \"gpio3\",\n+};\n+\n+static const char *const tsens_max_groups[] = {\n+\t\"gpio14\",\n+};\n+\n+static const char *const tsn_groups[] = {\n+\t\"gpio50\",\n+};\n+\n+static const struct pinfunction ipq9650_functions[] = {\n+\tMSM_PIN_FUNCTION(atest_char_start),\n+\tMSM_PIN_FUNCTION(atest_char_status0),\n+\tMSM_PIN_FUNCTION(atest_char_status1),\n+\tMSM_PIN_FUNCTION(atest_char_status2),\n+\tMSM_PIN_FUNCTION(atest_char_status3),\n+\tMSM_PIN_FUNCTION(atest_tic_en),\n+\tMSM_PIN_FUNCTION(audio_pri_mclk_in0),\n+\tMSM_PIN_FUNCTION(audio_pri_mclk_out0),\n+\tMSM_PIN_FUNCTION(audio_pri_mclk_in1),\n+\tMSM_PIN_FUNCTION(audio_pri_mclk_out1),\n+\tMSM_PIN_FUNCTION(audio_pri),\n+\tMSM_PIN_FUNCTION(audio_sec),\n+\tMSM_PIN_FUNCTION(audio_sec_mclk_in0),\n+\tMSM_PIN_FUNCTION(audio_sec_mclk_out0),\n+\tMSM_PIN_FUNCTION(audio_sec_mclk_in1),\n+\tMSM_PIN_FUNCTION(audio_sec_mclk_out1),\n+\tMSM_PIN_FUNCTION(core_voltage_0),\n+\tMSM_PIN_FUNCTION(core_voltage_1),\n+\tMSM_PIN_FUNCTION(core_voltage_2),\n+\tMSM_PIN_FUNCTION(core_voltage_3),\n+\tMSM_PIN_FUNCTION(core_voltage_4),\n+\tMSM_PIN_FUNCTION(cri_rng0),\n+\tMSM_PIN_FUNCTION(cri_rng1),\n+\tMSM_PIN_FUNCTION(cri_rng2),\n+\tMSM_PIN_FUNCTION(dbg_out_clk),\n+\tMSM_PIN_FUNCTION(gcc_plltest_bypassnl),\n+\tMSM_PIN_FUNCTION(gcc_plltest_resetn),\n+\tMSM_PIN_FUNCTION(gcc_tlmm),\n+\tMSM_GPIO_PIN_FUNCTION(gpio),\n+\tMSM_PIN_FUNCTION(mdc_mst),\n+\tMSM_PIN_FUNCTION(mdc_slv0),\n+\tMSM_PIN_FUNCTION(mdc_slv1),\n+\tMSM_PIN_FUNCTION(mdio_mst),\n+\tMSM_PIN_FUNCTION(mdio_slv),\n+\tMSM_PIN_FUNCTION(mdio_slv0),\n+\tMSM_PIN_FUNCTION(mdio_slv1),\n+\tMSM_PIN_FUNCTION(pcie0_clk_req_n),\n+\tMSM_PIN_FUNCTION(pcie0_wake),\n+\tMSM_PIN_FUNCTION(pcie1_clk_req_n),\n+\tMSM_PIN_FUNCTION(pcie1_wake),\n+\tMSM_PIN_FUNCTION(pcie2_clk_req_n),\n+\tMSM_PIN_FUNCTION(pcie2_wake),\n+\tMSM_PIN_FUNCTION(pcie3_clk_req_n),\n+\tMSM_PIN_FUNCTION(pcie3_wake),\n+\tMSM_PIN_FUNCTION(pcie4_clk_req_n),\n+\tMSM_PIN_FUNCTION(pcie4_wake),\n+\tMSM_PIN_FUNCTION(pll_bist_sync),\n+\tMSM_PIN_FUNCTION(pll_test),\n+\tMSM_PIN_FUNCTION(pwm),\n+\tMSM_PIN_FUNCTION(qdss_cti_trig_in_a0),\n+\tMSM_PIN_FUNCTION(qdss_cti_trig_in_a1),\n+\tMSM_PIN_FUNCTION(qdss_cti_trig_in_b0),\n+\tMSM_PIN_FUNCTION(qdss_cti_trig_in_b1),\n+\tMSM_PIN_FUNCTION(qdss_cti_trig_out_a0),\n+\tMSM_PIN_FUNCTION(qdss_cti_trig_out_a1),\n+\tMSM_PIN_FUNCTION(qdss_cti_trig_out_b0),\n+\tMSM_PIN_FUNCTION(qdss_cti_trig_out_b1),\n+\tMSM_PIN_FUNCTION(qdss_traceclk_a),\n+\tMSM_PIN_FUNCTION(qdss_tracectl_a),\n+\tMSM_PIN_FUNCTION(qdss_tracedata_a),\n+\tMSM_PIN_FUNCTION(qspi_data),\n+\tMSM_PIN_FUNCTION(qspi_clk),\n+\tMSM_PIN_FUNCTION(qspi_cs_n),\n+\tMSM_PIN_FUNCTION(qup_se0),\n+\tMSM_PIN_FUNCTION(qup_se1),\n+\tMSM_PIN_FUNCTION(qup_se2),\n+\tMSM_PIN_FUNCTION(qup_se3),\n+\tMSM_PIN_FUNCTION(qup_se4),\n+\tMSM_PIN_FUNCTION(qup_se5),\n+\tMSM_PIN_FUNCTION(qup_se6),\n+\tMSM_PIN_FUNCTION(qup_se7),\n+\tMSM_PIN_FUNCTION(resout),\n+\tMSM_PIN_FUNCTION(rx_los0),\n+\tMSM_PIN_FUNCTION(rx_los1),\n+\tMSM_PIN_FUNCTION(rx_los2),\n+\tMSM_PIN_FUNCTION(sdc_clk),\n+\tMSM_PIN_FUNCTION(sdc_cmd),\n+\tMSM_PIN_FUNCTION(sdc_data),\n+\tMSM_PIN_FUNCTION(tsens_max),\n+\tMSM_PIN_FUNCTION(tsn),\n+};\n+\n+static const struct msm_pingroup ipq9650_groups[] = {\n+\t[0] = PINGROUP(0, sdc_data, qspi_data, _, _, _, _, _, _, _),\n+\t[1] = PINGROUP(1, sdc_data, qspi_data, _, _, _, _, _, _, _),\n+\t[2] = PINGROUP(2, sdc_data, qspi_data, _, _, _, _, _, _, _),\n+\t[3] = PINGROUP(3, sdc_data, qspi_data, _, _, _, _, _, _, _),\n+\t[4] = PINGROUP(4, sdc_cmd, qspi_cs_n, _, _, _, _, _, _, _),\n+\t[5] = PINGROUP(5, sdc_clk, qspi_clk, _, _, _, _, _, _, _),\n+\t[6] = PINGROUP(6, qup_se0, pwm, _, cri_rng0, qdss_tracedata_a, _, _, _, _),\n+\t[7] = PINGROUP(7, qup_se0, pwm, _, cri_rng1, qdss_tracedata_a, _, _, _, _),\n+\t[8] = PINGROUP(8, qup_se0, pwm, _, cri_rng2, qdss_tracedata_a, _, _, _, _),\n+\t[9] = PINGROUP(9, qup_se0, pwm, _, qdss_tracedata_a, _, _, _, _, _),\n+\t[10] = PINGROUP(10, qup_se1, pwm, _, _, qdss_tracedata_a, _, _, _, _),\n+\t[11] = PINGROUP(11, qup_se1, pwm, _, _, qdss_tracedata_a, _, _, _, _),\n+\t[12] = PINGROUP(12, qup_se1, _, qdss_tracedata_a, _, _, _, _, _, _),\n+\t[13] = PINGROUP(13, qup_se1, _, qdss_tracedata_a, _, _, _, _, _, _),\n+\t[14] = PINGROUP(14, qup_se4, mdc_slv1, tsens_max, _, qdss_tracedata_a, _, _, _, _),\n+\t[15] = PINGROUP(15, qup_se4, mdio_slv1, _, qdss_tracedata_a, _, _, _, _, _),\n+\t[16] = PINGROUP(16, core_voltage_0, qup_se3, pwm, _, _, _, _, _, _),\n+\t[17] = PINGROUP(17, core_voltage_1, qup_se3, pwm, _, _, _, _, _, _),\n+\t[18] = PINGROUP(18, _, _, _, _, _, _, _, _, _),\n+\t[19] = PINGROUP(19, _, _, _, _, _, _, _, _, _),\n+\t[20] = PINGROUP(20, mdc_slv0, qup_se3, _, qdss_tracedata_a, _, _, _, _, _),\n+\t[21] = PINGROUP(21, mdio_slv0, qup_se3, atest_char_start, _, qdss_tracedata_a, _, _, _, _),\n+\t[22] = PINGROUP(22, mdc_mst, atest_char_status2, _, _, _, _, _, _, _),\n+\t[23] = PINGROUP(23, mdio_mst, atest_char_status3, _, _, _, _, _, _, _),\n+\t[24] = PINGROUP(24, pcie0_clk_req_n, _, _, _, _, _, _, _, _),\n+\t[25] = PINGROUP(25, _, _, _, _, _, _, _, _, _),\n+\t[26] = PINGROUP(26, pcie0_wake, _, _, _, _, _, _, _, _),\n+\t[27] = PINGROUP(27, pcie1_clk_req_n, qup_se2, qup_se1, _, qdss_cti_trig_out_a1, _, _, _, _),\n+\t[28] = PINGROUP(28, _, _, _, _, _, _, _, _, _),\n+\t[29] = PINGROUP(29, pcie1_wake, qup_se2, qup_se1, _, qdss_cti_trig_in_a1, _, _, _, _),\n+\t[30] = PINGROUP(30, pcie4_clk_req_n, _, _, _, _, _, _, _, _),\n+\t[31] = PINGROUP(31, _, _, _, _, _, _, _, _, _),\n+\t[32] = PINGROUP(32, pcie4_wake, _, _, _, _, _, _, _, _),\n+\t[33] = PINGROUP(33, core_voltage_2, qup_se2, gcc_plltest_bypassnl, pwm, atest_char_status0, _, _, _, _),\n+\t[34] = PINGROUP(34, core_voltage_3, qup_se2, gcc_tlmm, pwm, _, _, _, _, _),\n+\t[35] = PINGROUP(35, core_voltage_4, gcc_plltest_resetn, pwm, atest_char_status1, _, _, _, _, _),\n+\t[36] = PINGROUP(36, audio_pri, qup_se7, qdss_tracedata_a, _, _, _, _, _, _),\n+\t[37] = PINGROUP(37, audio_pri, qup_se7, audio_sec_mclk_out0, audio_sec_mclk_in0, rx_los2, qdss_tracedata_a, _, _, _),\n+\t[38] = PINGROUP(38, audio_pri, qup_se7, rx_los1, qdss_tracedata_a, _, _, _, _, _),\n+\t[39] = PINGROUP(39, audio_pri, qup_se7, audio_sec_mclk_out1, audio_sec_mclk_in1, pll_test, rx_los0, _, qdss_tracedata_a, _),\n+\t[40] = PINGROUP(40, pcie3_clk_req_n, qup_se5, qup_se4, _, qdss_cti_trig_out_b0, _, _, _, _),\n+\t[41] = PINGROUP(41, _, _, _, _, _, _, _, _, _),\n+\t[42] = PINGROUP(42, pcie3_wake, qup_se5, qup_se4, _, qdss_cti_trig_in_b0, _, _, _, _),\n+\t[43] = PINGROUP(43, qup_se4, qup_se6, pwm, _, qdss_cti_trig_in_b1, _, _, _, _),\n+\t[44] = PINGROUP(44, qup_se4, qup_se6, pwm, _, qdss_cti_trig_out_b1, _, _, _, _),\n+\t[45] = PINGROUP(45, qup_se5, rx_los2, audio_sec, pwm, _, qdss_traceclk_a, _, _, _),\n+\t[46] = PINGROUP(46, qup_se5, rx_los1, audio_sec, mdio_slv, pwm, dbg_out_clk, qdss_tracectl_a, _, _),\n+\t[47] = PINGROUP(47, qup_se5, rx_los0, audio_sec, mdio_slv, pll_bist_sync, pwm, _, _, _),\n+\t[48] = PINGROUP(48, qup_se5, audio_sec, pwm, _, _, _, _, _, _),\n+\t[49] = PINGROUP(49, resout, _, _, _, _, _, _, _, _),\n+\t[50] = PINGROUP(50, tsn, rx_los0, _, _, _, _, _, _, _),\n+\t[51] = PINGROUP(51, pcie2_clk_req_n, qup_se6, qup_se0, audio_pri_mclk_out1, audio_pri_mclk_in1, qdss_cti_trig_out_a0, _, _, _),\n+\t[52] = PINGROUP(52, _, _, _, _, _, _, _, _, _),\n+\t[53] = PINGROUP(53, pcie2_wake, qup_se6, qup_se0, audio_pri_mclk_out0, audio_pri_mclk_in0, qdss_cti_trig_in_a0, _, atest_tic_en, _),\n+};\n+\n+static const struct msm_pinctrl_soc_data ipq9650_tlmm = {\n+\t.pins = ipq9650_pins,\n+\t.npins = ARRAY_SIZE(ipq9650_pins),\n+\t.functions = ipq9650_functions,\n+\t.nfunctions = ARRAY_SIZE(ipq9650_functions),\n+\t.groups = ipq9650_groups,\n+\t.ngroups = ARRAY_SIZE(ipq9650_groups),\n+\t.ngpios = 54,\n+};\n+\n+static const struct of_device_id ipq9650_tlmm_of_match[] = {\n+\t{ .compatible = \"qcom,ipq9650-tlmm\", },\n+\t{},\n+};\n+\n+static int ipq9650_tlmm_probe(struct platform_device *pdev)\n+{\n+\treturn msm_pinctrl_probe(pdev, &ipq9650_tlmm);\n+}\n+\n+static struct platform_driver ipq9650_tlmm_driver = {\n+\t.driver = {\n+\t\t.name = \"ipq9650-tlmm\",\n+\t\t.of_match_table = ipq9650_tlmm_of_match,\n+\t},\n+\t.probe = ipq9650_tlmm_probe,\n+};\n+\n+static int __init ipq9650_tlmm_init(void)\n+{\n+\treturn platform_driver_register(&ipq9650_tlmm_driver);\n+}\n+arch_initcall(ipq9650_tlmm_init);\n+\n+static void __exit ipq9650_tlmm_exit(void)\n+{\n+\tplatform_driver_unregister(&ipq9650_tlmm_driver);\n+}\n+module_exit(ipq9650_tlmm_exit);\n+\n+MODULE_DESCRIPTION(\"QTI IPQ9650 TLMM driver\");\n+MODULE_LICENSE(\"GPL\");\n", "prefixes": [ "2/2" ] }