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GET /api/1.2/patches/2223496/?format=api
{ "id": 2223496, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2223496/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20260415-ipq9650_tlmm-v1-1-bd16ccb06332@oss.qualcomm.com/", "project": { "id": 42, "url": "http://patchwork.ozlabs.org/api/1.2/projects/42/?format=api", "name": "Linux GPIO development", "link_name": "linux-gpio", "list_id": "linux-gpio.vger.kernel.org", "list_email": "linux-gpio@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260415-ipq9650_tlmm-v1-1-bd16ccb06332@oss.qualcomm.com>", "list_archive_url": null, "date": "2026-04-15T11:29:24", "name": "[1/2] dt-bindings: pinctrl: qcom: add IPQ9650 pinctrl", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "b1c1f1c8e06d2417b67f5cb434108c36f741c35d", "submitter": { "id": 90386, "url": "http://patchwork.ozlabs.org/api/1.2/people/90386/?format=api", "name": "Kathiravan Thirumoorthy", "email": "kathiravan.thirumoorthy@oss.qualcomm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20260415-ipq9650_tlmm-v1-1-bd16ccb06332@oss.qualcomm.com/mbox/", "series": [ { "id": 499978, "url": "http://patchwork.ozlabs.org/api/1.2/series/499978/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/list/?series=499978", "date": "2026-04-15T11:29:23", "name": "Introduce TLMM driver for Qualcomm IPQ9650 SoC", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/499978/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2223496/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2223496/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-gpio+bounces-35167-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-gpio@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=B8R2VLDS;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=XgZHSVd/;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.105.105.114; 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adf61e73a8af0-39fe3f5b42dmr17221234637.36.1776252585535;\n Wed, 15 Apr 2026 04:29:45 -0700 (PDT)" ], "From": "Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>", "Date": "Wed, 15 Apr 2026 16:59:24 +0530", "Subject": "[PATCH 1/2] dt-bindings: pinctrl: qcom: add IPQ9650 pinctrl", "Precedence": "bulk", "X-Mailing-List": "linux-gpio@vger.kernel.org", "List-Id": "<linux-gpio.vger.kernel.org>", "List-Subscribe": "<mailto:linux-gpio+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-gpio+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-Id": "<20260415-ipq9650_tlmm-v1-1-bd16ccb06332@oss.qualcomm.com>", "References": "<20260415-ipq9650_tlmm-v1-0-bd16ccb06332@oss.qualcomm.com>", "In-Reply-To": "<20260415-ipq9650_tlmm-v1-0-bd16ccb06332@oss.qualcomm.com>", "To": "Bjorn Andersson <andersson@kernel.org>, Linus Walleij <linusw@kernel.org>,\n Rob Herring <robh@kernel.org>,\n Krzysztof Kozlowski <krzk+dt@kernel.org>,\n Conor Dooley <conor+dt@kernel.org>", "Cc": "linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org,\n devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,\n Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>", "X-Mailer": "b4 0.15.0", "X-Developer-Signature": "v=1; a=ed25519-sha256; t=1776252577; l=4547;\n i=kathiravan.thirumoorthy@oss.qualcomm.com; s=20230906;\n h=from:subject:message-id; bh=Kw7qLT5MhFXRMxGuny+FowYlCESO4Y+NTzQw2T7ofD0=;\n b=1rRUE+fuFkcnI51aMj/2eYvRE8Uo0OjJ0Ci/HAGR4XE2U8RtvvHKzKv0pA37hwQDOguw6fB5x\n WFgUG2IfYj6BeNcGi8JHCHBEAxgNe1xR/y0OfbwkjK2OTWS0+Iz8upx", "X-Developer-Key": "i=kathiravan.thirumoorthy@oss.qualcomm.com; a=ed25519;\n pk=xWsR7pL6ch+vdZ9MoFGEaP61JUaRf0XaZYWztbQsIiM=", "X-Proofpoint-Spam-Details-Enc": "AW1haW4tMjYwNDE1MDEwNSBTYWx0ZWRfXyfFjL5LVBFKN\n J2c8NCapIwmdh/lVBYQ8aX0rJrmmumIpA7pKE7BrSHx6ksSkhv0s8ZG9nAzof2nYzPJk0AqSLZn\n hc6SoZSnKB6eN5neNDJtmTZP84FrNKGtmA7YwT8JycOFzRcqxShIWeRqezOnOzZJIPNiNiBRiUs\n JttRj8Oq13x5BObRMZHtWGsnjMBJ6zNSTHDiFcby9SXkO/39NLqiMlOMXre4zJ9WNLq9hdq7zYk\n EXE1fUyjUDzdVTy0fdCfsa+7G11qhEYJxv4LounWlAIpNXKgB1RaN4BIf1WXlZFGHInpOYBoSu9\n O1nDXK1qkuh2m7ixsDVs/o7o0OaSWkGXHBAYc/bkyr8WkM7G60DyU/1VPNJi7LeNC7eWos1oOfU\n korB9nG5ErfEQMqnOOVEzctglG9KOzFxN0KoRs6psGKQJqVeAhVH3Kl219AEBI3ldhMHFt3CWcP\n KCtAexZS+P4DySYS8oA==", "X-Proofpoint-ORIG-GUID": "SrCkVOnFu4SCwLEq_Gzl4ExDUlJ4IGyc", "X-Authority-Analysis": "v=2.4 cv=ZIfnX37b c=1 sm=1 tr=0 ts=69df76ab cx=c_pps\n a=rz3CxIlbcmazkYymdCej/Q==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17\n a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10\n a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22\n a=gEfo2CItAAAA:8 a=EUspDBNiAAAA:8 a=VwQbUJbxAAAA:8 a=N690yQSzLXC5e7GKbG4A:9\n a=QEXdDO2ut3YA:10 a=bFCP_H2QrGi7Okbo017w:22 a=sptkURWiP4Gy88Gu7hUp:22", "X-Proofpoint-GUID": "SrCkVOnFu4SCwLEq_Gzl4ExDUlJ4IGyc", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-04-14_04,2026-04-13_04,2025-10-01_01", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n impostorscore=0 suspectscore=0 lowpriorityscore=0 spamscore=0 bulkscore=0\n phishscore=0 clxscore=1015 malwarescore=0 adultscore=0 priorityscore=1501\n classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0\n reason=mlx scancount=1 engine=8.22.0-2604070000 definitions=main-2604150105" }, "content": "Add device tree bindings for IPQ9650 TLMM block.\n\nSigned-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>\n---\n .../bindings/pinctrl/qcom,ipq9650-tlmm.yaml | 118 +++++++++++++++++++++\n 1 file changed, 118 insertions(+)", "diff": "diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,ipq9650-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,ipq9650-tlmm.yaml\nnew file mode 100644\nindex 000000000000..549eaa6aa11b\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/pinctrl/qcom,ipq9650-tlmm.yaml\n@@ -0,0 +1,118 @@\n+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)\n+%YAML 1.2\n+---\n+$id: http://devicetree.org/schemas/pinctrl/qcom,ipq9650-tlmm.yaml#\n+$schema: http://devicetree.org/meta-schemas/core.yaml#\n+\n+title: Qualcomm IPQ9650 TLMM pin controller\n+\n+maintainers:\n+ - Bjorn Andersson <andersson@kernel.org>\n+ - Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>\n+\n+description:\n+ Top Level Mode Multiplexer pin controller in Qualcomm IPQ9650 SoC.\n+\n+allOf:\n+ - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#\n+\n+properties:\n+ compatible:\n+ const: qcom,ipq9650-tlmm\n+\n+ reg:\n+ maxItems: 1\n+\n+ interrupts:\n+ maxItems: 1\n+\n+ gpio-reserved-ranges:\n+ minItems: 1\n+ maxItems: 27\n+\n+ gpio-line-names:\n+ maxItems: 54\n+\n+patternProperties:\n+ \"-state$\":\n+ oneOf:\n+ - $ref: \"#/$defs/qcom-ipq9650-tlmm-state\"\n+ - patternProperties:\n+ \"-pins$\":\n+ $ref: \"#/$defs/qcom-ipq9650-tlmm-state\"\n+ additionalProperties: false\n+\n+$defs:\n+ qcom-ipq9650-tlmm-state:\n+ type: object\n+ description:\n+ Pinctrl node's client devices use subnodes for desired pin configuration.\n+ Client device subnodes use below standard properties.\n+ $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state\n+ unevaluatedProperties: false\n+\n+ properties:\n+ pins:\n+ description:\n+ List of gpio pins affected by the properties specified in this\n+ subnode.\n+ items:\n+ pattern: \"^gpio([0-9]|[1-4][0-9]|5[0-3])$\"\n+ minItems: 1\n+ maxItems: 36\n+\n+ function:\n+ description:\n+ Specify the alternative function to be configured for the specified\n+ pins.\n+\n+ enum: [ atest_char_start, atest_char_status0, atest_char_status1,\n+ atest_char_status2, atest_char_status3, atest_tic_en,\n+ audio_pri_mclk_in0, audio_pri_mclk_out0, audio_pri_mclk_in1,\n+ audio_pri_mclk_out1, audio_pri, audio_sec, audio_sec_mclk_in0,\n+ audio_sec_mclk_out0, audio_sec_mclk_in1, audio_sec_mclk_out1,\n+ core_voltage_0, core_voltage_1, core_voltage_2, core_voltage_3,\n+ core_voltage_4, cri_rng0, cri_rng1, cri_rng2, dbg_out_clk,\n+ gcc_plltest_bypassnl, gcc_plltest_resetn, gcc_tlmm, gpio,\n+ mdc_mst, mdc_slv0, mdc_slv1, mdio_mst, mdio_slv, mdio_slv0,\n+ mdio_slv1, pcie0_clk_req_n, pcie0_wake, pcie1_clk_req_n,\n+ pcie1_wake, pcie2_clk_req_n, pcie2_wake, pcie3_clk_req_n,\n+ pcie3_wake, pcie4_clk_req_n, pcie4_wake, pll_bist_sync,\n+ pll_test, pwm, qdss_cti_trig_in_a0, qdss_cti_trig_in_a1,\n+ qdss_cti_trig_in_b0, qdss_cti_trig_in_b1, qdss_cti_trig_out_a0,\n+ qdss_cti_trig_out_a1, qdss_cti_trig_out_b0, qdss_cti_trig_out_b1,\n+ qdss_traceclk_a, qdss_tracectl_a, qdss_tracedata_a, qspi_data,\n+ qspi_clk, qspi_cs_n, qup_se0, qup_se1, qup_se2, qup_se3,\n+ qup_se4, qup_se5, qup_se6, qup_se7, resout, rx_los0, rx_los1,\n+ rx_los2, sdc_clk, sdc_cmd, sdc_data, tsens_max, tsn ]\n+\n+ required:\n+ - pins\n+\n+required:\n+ - compatible\n+ - reg\n+\n+unevaluatedProperties: false\n+\n+examples:\n+ - |\n+ #include <dt-bindings/interrupt-controller/arm-gic.h>\n+\n+ tlmm: pinctrl@1000000 {\n+ compatible = \"qcom,ipq9650-tlmm\";\n+ reg = <0x01000000 0x300000>;\n+ gpio-controller;\n+ #gpio-cells = <2>;\n+ gpio-ranges = <&tlmm 0 0 54>;\n+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;\n+ interrupt-controller;\n+ #interrupt-cells = <2>;\n+\n+ qup-uart1-default-state {\n+ pins = \"gpio43\", \"gpio44\";\n+ function = \"qup_se6\";\n+ drive-strength = <8>;\n+ bias-pull-down;\n+ };\n+ };\n", "prefixes": [ "1/2" ] }