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GET /api/1.2/patches/2223473/?format=api
{ "id": 2223473, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2223473/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260415105552.622421-24-skolothumtho@nvidia.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.2/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260415105552.622421-24-skolothumtho@nvidia.com>", "list_archive_url": null, "date": "2026-04-15T10:55:44", "name": "[v4,23/31] hw/arm/smmuv3-accel: Introduce common helper for veventq read", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "8858033dd0be65c607fc746584b3a3bbbcdb4fbe", "submitter": { "id": 91580, "url": "http://patchwork.ozlabs.org/api/1.2/people/91580/?format=api", "name": "Shameer Kolothum Thodi", "email": "skolothumtho@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260415105552.622421-24-skolothumtho@nvidia.com/mbox/", "series": [ { "id": 499965, "url": "http://patchwork.ozlabs.org/api/1.2/series/499965/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=499965", "date": "2026-04-15T10:55:21", "name": "hw/arm/virt: Introduce Tegra241 CMDQV support for accelerated SMMUv3", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/499965/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2223473/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2223473/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=tT5AG29S;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail.nvidia.com; pr=C", "permerror client-ip=2a01:111:f403:c105::7;\n envelope-from=skolothumtho@nvidia.com;\n helo=CH4PR04CU002.outbound.protection.outlook.com" ], "From": "Shameer Kolothum <skolothumtho@nvidia.com>", "To": "<qemu-arm@nongnu.org>, <qemu-devel@nongnu.org>", "CC": "<eric.auger@redhat.com>, <peter.maydell@linaro.org>, <clg@redhat.com>,\n <alex@shazbot.org>, <nicolinc@nvidia.com>, <nathanc@nvidia.com>,\n <mochs@nvidia.com>, <jan@nvidia.com>, <jgg@nvidia.com>,\n <jonathan.cameron@huawei.com>, <zhenzhong.duan@intel.com>,\n <kjaju@nvidia.com>, <phrdina@redhat.com>, <skolothumtho@nvidia.com>", "Subject": "[PATCH v4 23/31] hw/arm/smmuv3-accel: Introduce common helper for\n veventq read", "Date": "Wed, 15 Apr 2026 11:55:44 +0100", "Message-ID": "<20260415105552.622421-24-skolothumtho@nvidia.com>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260415105552.622421-1-skolothumtho@nvidia.com>", "References": "<20260415105552.622421-1-skolothumtho@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.230.37]", "X-ClientProxiedBy": "rnnvmail203.nvidia.com (10.129.68.9) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "CY4PEPF0000EE3B:EE_|PH8PR12MB7255:EE_", "X-MS-Office365-Filtering-Correlation-Id": "951b2cfd-9d52-44e7-3c75-08de9adde60d", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;\n ARA:13230040|82310400026|376014|36860700016|1800799024|22082099003|56012099003|18002099003;", "X-Microsoft-Antispam-Message-Info": "\n FIkx7s/+rwuhqidKR5nCZOuJVWJvcWY1rAVVORQynBuWEcu8uU0bhJrh1zJpuPl52vw0KyspLBzSORSx3pEFZQDvRSdz3DQWfBboleH9+6am0n+nz6sKopJ7yQTqUJUraWCYeVopSsweAf5QMl5EY+WQVgfdTNt5F9ZhfxwMwxJbsJgbblBKifWTbWseJ2TWXua2Uvy5coNdl+lXfMWHPE9Rqd8mSuUMuYV56wsP8O/Bwipn+J3FUz/XlT3MUW2drVjLliI5bDj6pTBizj3nwGAu4UjGxPXm5bA+iM/EkGMi9d7a5rqpvYaz0mo8o0m71AWNXq7ytDMUoetDQB3m9UzeAIB0vHf85ZoqBTbcYdQQ3jJSfC2M9uVBcYYBxQ/AEF2WTAK6vTGuev8UrKmSi4kPZNYpSe+0jP5Sp60mWSRN4BSVLposS88DOQvM4F0jMGWU9c22sh003thP8bar73ugECH8b7Rh2uaK31KWPMDm0vQ+U+W4R7ftieTFfEFb26LjVXnMrSBByH63krbUCJpF0iaxwX4upN61vOyM545MlJUA70gzV8UypqNfpYBUvFQ8ft+hP4acOifUaD76yT/qJkq0HEcLFZLOPHBNmhlgbndzFOjJksmdmZi4z9CpKQGLGWK49edfSG63Kk1di4tLbwuHW/uN6hjv+9uIZdlDBKyMEjGF3K6dUyFJxyPQutnqZgo+/rWnVpyzwR8EHIEsbAK1wNfJ9RYt0SNQIplExn43Pu8cbAGA0m5QLjU8VPaGmto+ohi6Mx0wwDLQYA==", "X-Forefront-Antispam-Report": "CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE;\n SFS:(13230040)(82310400026)(376014)(36860700016)(1800799024)(22082099003)(56012099003)(18002099003);\n DIR:OUT; SFP:1101;", "X-MS-Exchange-AntiSpam-MessageData-ChunkCount": "1", "X-MS-Exchange-AntiSpam-MessageData-0": "\n LcTXPD4D2OL6Pd0fnDO/FTon+TFkNwA/u21sNC9R2dPoxF1E9wVQyKgxHW1EHFRwbJQ4qYHICfBhGT7+k7mBgCTySmUi8Yyas2v4J/cRVO/1s5p+jkdi6pO216ljDegl99XEJhl0c8mZPCB2wrmsA5ow4KSgr7/FmAVxigs8YMgUs/PKar4zWihKHNiqn/sskmACv/PNu8rn1L903Mo84m6kJsNUwr+C2SGeE3YrHDU3pN7YZ+8q4uDc4afhRjiqzE4onJkzjR+czyIJfAe3NPWOZCzpmMj4WT0936YvYk9Yt2kHr1k3WY23jS6Y8WOZnGhqEpCUsHbXBmTo3bBldg7BIjm6f40lp9kxa7oAjwDkViPXefw9P8/3ln2VW0/ZP9EOROcpwJ6ava+n2SJw4xeOp0XNW+Hf75Ahj7/tWC4UOm4G5Kb2ywAv/0qe31Bp", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "15 Apr 2026 10:58:16.9816 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 951b2cfd-9d52-44e7-3c75-08de9adde60d", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CY4PEPF0000EE3B.namprd03.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "PH8PR12MB7255", "X-Spam_score_int": "-15", "X-Spam_score": "-1.6", "X-Spam_bar": "-", "X-Spam_report": "(-1.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.54,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n FORGED_SPF_HELO=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001,\n SPF_NONE=0.001 autolearn=no autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Move the vEVENTQ read and validation logic into a common helper\nsmmuv3_accel_event_read_validate(). The helper performs the read(),\nchecks for overflow and short reads, validates the sequence number,\nand updates the sequence state.\n\nThis helper can be reused for Tegra241 CMDQV vEVENTQ support in a\nsubsequent patch.\n\nError handling is slightly adjusted: instead of reporting errors\ndirectly in the read handler, the helper now returns errors via\nError **. Sequence gaps are reported as warnings.\n\nSigned-off-by: Shameer Kolothum <skolothumtho@nvidia.com>\n---\n hw/arm/smmuv3-accel.h | 2 ++\n hw/arm/smmuv3-accel-stubs.c | 11 ++++++\n hw/arm/smmuv3-accel.c | 67 ++++++++++++++++++++++---------------\n 3 files changed, 53 insertions(+), 27 deletions(-)", "diff": "diff --git a/hw/arm/smmuv3-accel.h b/hw/arm/smmuv3-accel.h\nindex 28bceca061..448f47c0ca 100644\n--- a/hw/arm/smmuv3-accel.h\n+++ b/hw/arm/smmuv3-accel.h\n@@ -71,6 +71,8 @@ bool smmuv3_accel_issue_inv_cmd(SMMUv3State *s, void *cmd, SMMUDevice *sdev,\n Error **errp);\n void smmuv3_accel_idr_override(SMMUv3State *s);\n bool smmuv3_accel_alloc_veventq(SMMUv3State *s, Error **errp);\n+bool smmuv3_accel_event_read_validate(IOMMUFDVeventq *veventq, uint32_t type,\n+ void *buf, size_t size, Error **errp);\n void smmuv3_accel_reset(SMMUv3State *s);\n \n #endif /* HW_ARM_SMMUV3_ACCEL_H */\ndiff --git a/hw/arm/smmuv3-accel-stubs.c b/hw/arm/smmuv3-accel-stubs.c\nindex c08caa6fa4..e8f08dc833 100644\n--- a/hw/arm/smmuv3-accel-stubs.c\n+++ b/hw/arm/smmuv3-accel-stubs.c\n@@ -41,6 +41,17 @@ void smmuv3_accel_idr_override(SMMUv3State *s)\n {\n }\n \n+bool smmuv3_accel_alloc_veventq(SMMUv3State *s, Error **errp)\n+{\n+ return true;\n+}\n+\n+bool smmuv3_accel_event_read_validate(IOMMUFDVeventq *veventq, uint32_t type,\n+ void *buf, size_t size, Error **errp)\n+{\n+ return true;\n+}\n+\n void smmuv3_accel_reset(SMMUv3State *s)\n {\n }\ndiff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c\nindex 9068e65e2b..230f608f03 100644\n--- a/hw/arm/smmuv3-accel.c\n+++ b/hw/arm/smmuv3-accel.c\n@@ -436,47 +436,60 @@ bool smmuv3_accel_issue_inv_cmd(SMMUv3State *bs, void *cmd, SMMUDevice *sdev,\n sizeof(Cmd), &entry_num, cmd, errp);\n }\n \n-static void smmuv3_accel_event_read(void *opaque)\n+bool smmuv3_accel_event_read_validate(IOMMUFDVeventq *veventq, uint32_t type,\n+ void *buf, size_t size, Error **errp)\n {\n- SMMUv3State *s = opaque;\n- IOMMUFDVeventq *veventq = s->s_accel->veventq;\n- struct {\n- struct iommufd_vevent_header hdr;\n- struct iommu_vevent_arm_smmuv3 vevent;\n- } buf;\n- enum iommu_veventq_type type = IOMMU_VEVENTQ_TYPE_ARM_SMMUV3;\n- uint32_t id = veventq->veventq_id;\n uint32_t last_seq = veventq->last_event_seq;\n+ uint32_t id = veventq->veventq_id;\n+ struct iommufd_vevent_header *hdr;\n ssize_t bytes;\n \n- bytes = read(veventq->veventq_fd, &buf, sizeof(buf));\n+ bytes = read(veventq->veventq_fd, buf, size);\n if (bytes <= 0) {\n if (errno == EAGAIN || errno == EINTR) {\n- return;\n+ return true;\n }\n- error_report_once(\"vEVENTQ(type %u id %u): read failed (%m)\", type, id);\n- return;\n+ error_setg(errp, \"vEVENTQ(type %u id %u): read failed (%m)\", type, id);\n+ return false;\n }\n-\n- if (bytes == sizeof(buf.hdr) &&\n- (buf.hdr.flags & IOMMU_VEVENTQ_FLAG_LOST_EVENTS)) {\n- error_report_once(\"vEVENTQ(type %u id %u): overflowed\", type, id);\n+ hdr = (struct iommufd_vevent_header *)buf;\n+ if (bytes == sizeof(*hdr) &&\n+ (hdr->flags & IOMMU_VEVENTQ_FLAG_LOST_EVENTS)) {\n+ error_setg(errp, \"vEVENTQ(type %u id %u): overflowed\", type, id);\n veventq->event_start = false;\n- return;\n+ return false;\n }\n- if (bytes < sizeof(buf)) {\n- error_report_once(\"vEVENTQ(type %u id %u): short read(%zd/%zd bytes)\",\n- type, id, bytes, sizeof(buf));\n- return;\n+ if (bytes < size) {\n+ error_setg(errp, \"vEVENTQ(type %u id %u): short read(%zd/%zd bytes)\",\n+ type, id, bytes, size);\n+ return false;\n }\n-\n /* Check sequence in hdr for lost events if any */\n- if (veventq->event_start && (buf.hdr.sequence - last_seq != 1)) {\n- error_report_once(\"vEVENTQ(type %u id %u): lost %u event(s)\",\n- type, id, buf.hdr.sequence - last_seq - 1);\n+ if (veventq->event_start && (hdr->sequence - last_seq != 1)) {\n+ warn_report(\"vEVENTQ(type %u id %u): lost %u event(s)\",\n+ type, id, hdr->sequence - last_seq - 1);\n }\n- veventq->last_event_seq = buf.hdr.sequence;\n+ veventq->last_event_seq = hdr->sequence;\n veventq->event_start = true;\n+ return true;\n+}\n+\n+static void smmuv3_accel_event_read(void *opaque)\n+{\n+ SMMUv3State *s = opaque;\n+ IOMMUFDVeventq *veventq = s->s_accel->veventq;\n+ struct {\n+ struct iommufd_vevent_header hdr;\n+ struct iommu_vevent_arm_smmuv3 vevent;\n+ } buf;\n+ Error *local_err = NULL;\n+\n+ if (!smmuv3_accel_event_read_validate(veventq,\n+ IOMMU_VEVENTQ_TYPE_ARM_SMMUV3, &buf,\n+ sizeof(buf), &local_err)) {\n+ warn_report_err_once(local_err);\n+ return;\n+ }\n smmuv3_propagate_event(s, (Evt *)&buf.vevent);\n }\n \n", "prefixes": [ "v4", "23/31" ] }