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GET /api/1.2/patches/2223472/?format=api
{ "id": 2223472, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2223472/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260415105552.622421-9-skolothumtho@nvidia.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.2/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260415105552.622421-9-skolothumtho@nvidia.com>", "list_archive_url": null, "date": "2026-04-15T10:55:29", "name": "[v4,08/31] hw/arm/smmuv3-accel: Wire CMDQV ops into accel lifecycle", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "3e3953a25a84eec10ab29a3d7045146eb7324196", "submitter": { "id": 91580, "url": "http://patchwork.ozlabs.org/api/1.2/people/91580/?format=api", "name": "Shameer Kolothum Thodi", "email": "skolothumtho@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260415105552.622421-9-skolothumtho@nvidia.com/mbox/", "series": [ { "id": 499965, "url": "http://patchwork.ozlabs.org/api/1.2/series/499965/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=499965", "date": "2026-04-15T10:55:21", "name": "hw/arm/virt: Introduce Tegra241 CMDQV support for accelerated SMMUv3", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/499965/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2223472/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2223472/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=UtxBRwQj;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail.nvidia.com; pr=C", "permerror client-ip=2a01:111:f403:c001::2;\n envelope-from=skolothumtho@nvidia.com;\n helo=SJ2PR03CU001.outbound.protection.outlook.com" ], "From": "Shameer Kolothum <skolothumtho@nvidia.com>", "To": "<qemu-arm@nongnu.org>, <qemu-devel@nongnu.org>", "CC": "<eric.auger@redhat.com>, <peter.maydell@linaro.org>, <clg@redhat.com>,\n <alex@shazbot.org>, <nicolinc@nvidia.com>, <nathanc@nvidia.com>,\n <mochs@nvidia.com>, <jan@nvidia.com>, <jgg@nvidia.com>,\n <jonathan.cameron@huawei.com>, <zhenzhong.duan@intel.com>,\n <kjaju@nvidia.com>, <phrdina@redhat.com>, <skolothumtho@nvidia.com>", "Subject": "[PATCH v4 08/31] hw/arm/smmuv3-accel: Wire CMDQV ops into accel\n lifecycle", "Date": "Wed, 15 Apr 2026 11:55:29 +0100", "Message-ID": "<20260415105552.622421-9-skolothumtho@nvidia.com>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260415105552.622421-1-skolothumtho@nvidia.com>", "References": "<20260415105552.622421-1-skolothumtho@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.230.37]", "X-ClientProxiedBy": "rnnvmail203.nvidia.com (10.129.68.9) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "BL02EPF00021F68:EE_|CH3PR12MB9730:EE_", "X-MS-Office365-Filtering-Correlation-Id": "24c9976a-2679-414b-18e2-08de9addc394", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;\n ARA:13230040|376014|82310400026|36860700016|1800799024|18002099003|56012099003|22082099003;", "X-Microsoft-Antispam-Message-Info": "\n fFxiT9YSqy3g4M90AUkPnqsBiPmHh3HusrKwpTgjFUN/kGM+fox1TJcuxL7f8OyRZuwXBTnGLMF305b925tFXy/92D4s9KjHBqKpTryts2eGJzM9VMNp16L/7YS7SQqocrY79X/9MgsIs5Vr3cyrHuYxC0PUp47BiKcPdT/cORwuVNMuQ/dC3+E1wpuQzeqLesC0M7WlgiwG8vixBukrH8NV0ldNHiC704eJY68GaBs4v2yDwXZ1nVbBUm4+WGKTuaeE47zrtnnPC9eSmI0L8bX5Q+7EIUSWdgO3MVuKCf87fBoM0d/KXcFaS9AK0PRM2s/vSRWx1MKsCq5pdc/Tz2iLeCIORhJC/9t4r1sG4/p2CyDYDpuWoNWbicLTplAiEFToJGkP7OZxutZ1lVx7AlfLoyL9AD8BQuhW+uO2qFUJ/dvztJft38Dynzfqf77LpSb8c6Q8GHVgjDChKYRENM0ZJpgV6jUWoVIMfe39dl3isIx+B3nRPipDUN+ZLiSYjW5gsp4Syze9pnweBAUEs8jsUQvVaMPkeSturta7FGEmm+pfEJAi0fseW25xdsUGqkNgte5vZscxuvsigDnBtMsIJkzjUrUo008+uTys/oNpF9u9/0ltZUp2u2A0Q2TsbWAEOGlg5Cxz4w/nFbuGo/VfrkeqbxSNtZt9GsqIPoijrHNAcdIPVDbZEt3rUITBBGddL6O/BRtzjEhefnn3RZJKslujIIPAI64p3LG8JQiLRUL3ssKDjkb3sQHDJpdaSaLYZ2XUHe/pZmky0jdmSQ==", "X-Forefront-Antispam-Report": "CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE;\n SFS:(13230040)(376014)(82310400026)(36860700016)(1800799024)(18002099003)(56012099003)(22082099003);\n DIR:OUT; SFP:1101;", "X-MS-Exchange-AntiSpam-MessageData-ChunkCount": "1", "X-MS-Exchange-AntiSpam-MessageData-0": "\n rqtqIRj3FEnDJTEzsd73qY+q7pCrp3se+fTcLcoW86/LmaGszx46mxXpbNYUVnr5R7VnR2TIMU1nN0mlmzXxChcFj8ljr+12uhxI2nHTANmuaEyzE7HAjRm2k9uWdy9cDm7lim3g7EXy6s+J38XQ3G34scNbLXupCyRnhHYko0IeWcAx2ELM51u7Y6JK8VmMJD/35JN7weMJqsbcOZRBDVZEEJxqypjBS+p10JWlGn+8t5zUC5csnY1YLneYMjTlE0GpwSpWzNuKWWEzYw6doAGQxbzE6f5OGWGXsYvtQllINp3FK++PIy84o0EMgFzVeSN9BRup/x9jUMX7F54HInbcalnZl0WZ/rBzks6VJnnkpvw7mdM8pgC2CjOcKtevenAplfpPcVuvZY6ew+QHGoPGknOoIM500vGsmmZOewk3n8l2AFQVXMsEPSmgXphX", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "15 Apr 2026 10:57:19.1026 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 24c9976a-2679-414b-18e2-08de9addc394", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BL02EPF00021F68.namprd02.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "CH3PR12MB9730", "X-Spam_score_int": "-15", "X-Spam_score": "-1.6", "X-Spam_bar": "-", "X-Spam_report": "(-1.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.54,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n FORGED_SPF_HELO=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001,\n SPF_NONE=0.001 autolearn=no autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Add support for selecting and initializing a CMDQV backend based on the\ncmdqv OnOffAuto property.\n\nIf set to OFF, CMDQV is not used and the default IOMMUFD-backed allocation\npath is taken.\n\nIf set to AUTO, QEMU attempts to probe a CMDQV backend during device setup.\nIf probing succeeds, the selected ops are stored in the accelerated SMMUv3\nstate and used. If probing fails, QEMU silently falls back to the default\npath.\n\nIf set to ON, QEMU requires CMDQV support. Probing is performed during\nsetup and failure results in an error.\n\nWhen a CMDQV backend is active, its callbacks are used for vIOMMU\nallocation, free, and reset handling. Otherwise, the base implementation\nis used.\n\nThe current implementation wires up the Tegra241 CMDQV backend through the\ngeneric ops interface. Functional CMDQV behaviour is added in subsequent\npatches.\n\nNo functional change.\n\nSigned-off-by: Shameer Kolothum <skolothumtho@nvidia.com>\n---\n include/hw/arm/smmuv3.h | 2 +\n hw/arm/smmuv3-accel.c | 93 +++++++++++++++++++++++++++++++++++++----\n 2 files changed, 88 insertions(+), 7 deletions(-)", "diff": "diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h\nindex fe0493c1aa..aa6a79237a 100644\n--- a/include/hw/arm/smmuv3.h\n+++ b/include/hw/arm/smmuv3.h\n@@ -74,6 +74,8 @@ struct SMMUv3State {\n OnOffAuto ats;\n OasMode oas;\n SsidSizeMode ssidsize;\n+ /* SMMU CMDQV extension */\n+ OnOffAuto cmdqv;\n \n Notifier machine_done;\n };\ndiff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c\nindex f65e654adf..9068e65e2b 100644\n--- a/hw/arm/smmuv3-accel.c\n+++ b/hw/arm/smmuv3-accel.c\n@@ -18,6 +18,7 @@\n \n #include \"smmuv3-internal.h\"\n #include \"smmuv3-accel.h\"\n+#include \"tegra241-cmdqv.h\"\n \n /*\n * The root region aliases the global system memory, and shared_as_sysmem\n@@ -566,6 +567,7 @@ smmuv3_accel_alloc_viommu(SMMUv3State *s, HostIOMMUDeviceIOMMUFD *idev,\n Error **errp)\n {\n SMMUv3AccelState *accel = s->s_accel;\n+ const SMMUv3AccelCmdqvOps *cmdqv_ops = accel->cmdqv_ops;\n struct iommu_hwpt_arm_smmuv3 bypass_data = {\n .ste = { SMMU_STE_CFG_BYPASS | SMMU_STE_VALID, 0x0ULL },\n };\n@@ -576,10 +578,17 @@ smmuv3_accel_alloc_viommu(SMMUv3State *s, HostIOMMUDeviceIOMMUFD *idev,\n uint32_t viommu_id, hwpt_id;\n IOMMUFDViommu *viommu;\n \n- if (!iommufd_backend_alloc_viommu(idev->iommufd, idev->devid,\n- IOMMU_VIOMMU_TYPE_ARM_SMMUV3, s2_hwpt_id,\n- NULL, 0, &viommu_id, errp)) {\n- return false;\n+ if (cmdqv_ops) {\n+ if (!cmdqv_ops->alloc_viommu(s, idev, &viommu_id, errp)) {\n+ return false;\n+ }\n+ } else {\n+ if (!iommufd_backend_alloc_viommu(idev->iommufd, idev->devid,\n+ IOMMU_VIOMMU_TYPE_ARM_SMMUV3,\n+ s2_hwpt_id, NULL, 0, &viommu_id,\n+ errp)) {\n+ return false;\n+ }\n }\n \n viommu = g_new0(IOMMUFDViommu, 1);\n@@ -625,12 +634,69 @@ free_bypass_hwpt:\n free_abort_hwpt:\n iommufd_backend_free_id(idev->iommufd, accel->abort_hwpt_id);\n free_viommu:\n- iommufd_backend_free_id(idev->iommufd, viommu->viommu_id);\n+ if (cmdqv_ops && cmdqv_ops->free_viommu) {\n+ cmdqv_ops->free_viommu(s);\n+ } else {\n+ iommufd_backend_free_id(idev->iommufd, viommu->viommu_id);\n+ }\n g_free(viommu);\n accel->viommu = NULL;\n return false;\n }\n \n+static const SMMUv3AccelCmdqvOps *\n+smmuv3_accel_probe_cmdqv(SMMUv3State *s, HostIOMMUDeviceIOMMUFD *idev,\n+ Error **errp)\n+{\n+ const SMMUv3AccelCmdqvOps *ops = tegra241_cmdqv_get_ops();\n+\n+ if (!ops || !ops->probe) {\n+ error_setg(errp, \"No CMDQV ops found\");\n+ return NULL;\n+ }\n+\n+ if (!ops->probe(s, idev, errp)) {\n+ return NULL;\n+ }\n+ return ops;\n+}\n+\n+static bool\n+smmuv3_accel_select_cmdqv(SMMUv3State *s, HostIOMMUDeviceIOMMUFD *idev,\n+ Error **errp)\n+{\n+ const SMMUv3AccelCmdqvOps *ops = NULL;\n+\n+ if (s->s_accel->cmdqv_ops) {\n+ return true;\n+ }\n+\n+ switch (s->cmdqv) {\n+ case ON_OFF_AUTO_OFF:\n+ s->s_accel->cmdqv_ops = NULL;\n+ return true;\n+ case ON_OFF_AUTO_AUTO:\n+ ops = smmuv3_accel_probe_cmdqv(s, idev, NULL);\n+ break;\n+ case ON_OFF_AUTO_ON:\n+ ops = smmuv3_accel_probe_cmdqv(s, idev, errp);\n+ if (!ops) {\n+ error_append_hint(errp, \"CMDQV requested but not supported\");\n+ return false;\n+ }\n+ s->s_accel->cmdqv_ops = ops;\n+ break;\n+ default:\n+ g_assert_not_reached();\n+ }\n+\n+ if (ops && ops->init && !ops->init(s, errp)) {\n+ return false;\n+ }\n+ s->s_accel->cmdqv_ops = ops;\n+ return true;\n+}\n+\n static bool smmuv3_accel_set_iommu_device(PCIBus *bus, void *opaque, int devfn,\n HostIOMMUDevice *hiod, Error **errp)\n {\n@@ -665,6 +731,10 @@ static bool smmuv3_accel_set_iommu_device(PCIBus *bus, void *opaque, int devfn,\n goto done;\n }\n \n+ if (!smmuv3_accel_select_cmdqv(s, idev, errp)) {\n+ return false;\n+ }\n+\n if (!smmuv3_accel_alloc_viommu(s, idev, errp)) {\n error_append_hint(errp, \"Unable to alloc vIOMMU: idev devid 0x%x: \",\n idev->devid);\n@@ -936,8 +1006,17 @@ bool smmuv3_accel_attach_gbpa_hwpt(SMMUv3State *s, Error **errp)\n \n void smmuv3_accel_reset(SMMUv3State *s)\n {\n- /* Attach a HWPT based on GBPA reset value */\n- smmuv3_accel_attach_gbpa_hwpt(s, NULL);\n+ SMMUv3AccelState *accel = s->s_accel;\n+\n+ if (!accel) {\n+ return;\n+ }\n+ /* Attach a HWPT based on GBPA reset value */\n+ smmuv3_accel_attach_gbpa_hwpt(s, NULL);\n+\n+ if (accel->cmdqv_ops && accel->cmdqv_ops->reset) {\n+ accel->cmdqv_ops->reset(s);\n+ }\n }\n \n static void smmuv3_accel_as_init(SMMUv3State *s)\n", "prefixes": [ "v4", "08/31" ] }