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GET /api/1.2/patches/2223471/?format=api
{ "id": 2223471, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2223471/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260415105552.622421-16-skolothumtho@nvidia.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.2/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260415105552.622421-16-skolothumtho@nvidia.com>", "list_archive_url": null, "date": "2026-04-15T10:55:36", "name": "[v4,15/31] hw/arm/tegra241-cmdqv: Emulate VCMDQ register reads", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "b4468a1c5c1de92325367c3e99938b81508390fc", "submitter": { "id": 91580, "url": "http://patchwork.ozlabs.org/api/1.2/people/91580/?format=api", "name": "Shameer Kolothum Thodi", "email": "skolothumtho@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260415105552.622421-16-skolothumtho@nvidia.com/mbox/", "series": [ { "id": 499965, "url": "http://patchwork.ozlabs.org/api/1.2/series/499965/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=499965", "date": "2026-04-15T10:55:21", "name": "hw/arm/virt: Introduce Tegra241 CMDQV support for accelerated SMMUv3", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/499965/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2223471/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2223471/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=Pr6pNuFh;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail.nvidia.com; pr=C", "permerror client-ip=2a01:111:f403:c110::3;\n envelope-from=skolothumtho@nvidia.com;\n helo=BN8PR05CU002.outbound.protection.outlook.com" ], "From": "Shameer Kolothum <skolothumtho@nvidia.com>", "To": "<qemu-arm@nongnu.org>, <qemu-devel@nongnu.org>", "CC": "<eric.auger@redhat.com>, <peter.maydell@linaro.org>, <clg@redhat.com>,\n <alex@shazbot.org>, <nicolinc@nvidia.com>, <nathanc@nvidia.com>,\n <mochs@nvidia.com>, <jan@nvidia.com>, <jgg@nvidia.com>,\n <jonathan.cameron@huawei.com>, <zhenzhong.duan@intel.com>,\n <kjaju@nvidia.com>, <phrdina@redhat.com>, <skolothumtho@nvidia.com>", "Subject": "[PATCH v4 15/31] hw/arm/tegra241-cmdqv: Emulate VCMDQ register reads", "Date": "Wed, 15 Apr 2026 11:55:36 +0100", "Message-ID": "<20260415105552.622421-16-skolothumtho@nvidia.com>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260415105552.622421-1-skolothumtho@nvidia.com>", "References": "<20260415105552.622421-1-skolothumtho@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.230.37]", "X-ClientProxiedBy": "rnnvmail203.nvidia.com (10.129.68.9) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "CY4PEPF0000EE3B:EE_|LV2PR12MB5968:EE_", "X-MS-Office365-Filtering-Correlation-Id": "f94d0f72-fabf-4076-ad62-08de9addd113", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;\n ARA:13230040|36860700016|82310400026|376014|1800799024|56012099003|18002099003|22082099003;", "X-Microsoft-Antispam-Message-Info": "\n fs36zJ2ElvK/rHvvTl3E2sFRX00uGjdZqdR4uQyqhFNfFfsp5JjZ2JRPA1RV0u9UmlEJ5QsBBt1PzusaG2A6bzxenGmwP1xBWUo+KCNu38GTAk+eodhhj1Twv8M4gMYzNV506u6muIL3sv4vuT0DYMhhYFkfgA4fcTfkizLpLPeYyIFKhH9WW1bth024jFyLGcdaZga2ZeywwugxayKaXTCyuv3e/Er+FukKewYWK5WdOz3rllNVCqaA7KXPTJR5niq6F9cGahU7Z0ROTnAfU3OzLEKLve85dxtHdHPzgqnBG6iXcczi2h/FFjDsr1MQmz742SAtijkHIxFjqs5FEyZqF4PDNzXb71UevrE0qneT2EOsuiWWU0UxAFeIPHa0df9/+oxXqpPoo+QGKJ7b3S6Ipxng6G6TnLdYRqpo0WaVyHRcWaTRjxKwgE3qKVB39Nk1k2GiUv6+uUW0iLLxU095tO21AyZEcGY5SsCZ918PjBMUEOrKNGMd11xUyR/B63TgLU9ffo4Ey9hjBrFJGVqlPXUnkwXgrPUv8VqxJc/nz1WepaiYCbH87YVbZ1Jl8kBSFhUkfdGmikE/24M5J2YI8T5JlADRX1KlG2xT7kbsWrp+Hm8yoGTDs5axy3O5yU/FTJiTk54Fa1Qn/8Iq8lF9dYcGCRl5v0D1Fda5azBA3r731mnpPZUzkm/oD1qSgj17WDX0IjuYO+wEJIaAfswqBMknDrMlKuCo/OaxWyjkboTJKpH+plLmJsS9ks5GLvWQ8GdNg5eiBuN5Ha/18w==", "X-Forefront-Antispam-Report": "CIP:216.228.117.160; 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Ip=[216.228.117.160];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CY4PEPF0000EE3B.namprd03.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "LV2PR12MB5968", "X-Spam_score_int": "-15", "X-Spam_score": "-1.6", "X-Spam_bar": "-", "X-Spam_report": "(-1.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.54,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n FORGED_SPF_HELO=1, SPF_HELO_PASS=-0.001,\n SPF_NONE=0.001 autolearn=no autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "From: Nicolin Chen <nicolinc@nvidia.com>\n\nTegra241 CMDQV exposes per-VCMDQ register windows through two MMIO\napertures:\n\n CMDQV_CMDQ_BASE (0x10000/0x20000): VCMDQ Page0/Page1\n CMDQV_VI_CMDQ_BASE (0x30000/0x40000): VINTF VCMDQ Page0/Page1\n\nVINTF Page0 (0x30000) and VCMDQ Page0 (0x10000) are hardware aliases\naddressing the same underlying registers. Add read emulation for both\napertures, backed by a register cache. VINTF Page0 reads are translated\nto their VCMDQ Page0 equivalent and served from the same cached state.\n\nOnce IOMMU_HW_QUEUE_ALLOC and viommu_mmap are wired up in a subsequent\npatch, Page0 register reads will be served directly from the hardware\nbacked mmap'd page instead of the cache. Page1 registers are always\nserved from cache.\n\nSigned-off-by: Nicolin Chen <nicolinc@nvidia.com>\nSigned-off-by: Shameer Kolothum <skolothumtho@nvidia.com>\n---\n hw/arm/tegra241-cmdqv.h | 185 ++++++++++++++++++++++++++++++++++++++++\n hw/arm/tegra241-cmdqv.c | 73 ++++++++++++++++\n 2 files changed, 258 insertions(+)", "diff": "diff --git a/hw/arm/tegra241-cmdqv.h b/hw/arm/tegra241-cmdqv.h\nindex 965670066d..b8bd8cd8ff 100644\n--- a/hw/arm/tegra241-cmdqv.h\n+++ b/hw/arm/tegra241-cmdqv.h\n@@ -29,6 +29,13 @@\n */\n #define TEGRA241_CMDQV_IO_LEN 0x50000\n \n+/* CMDQV MMIO aperture bases and VCMDQ stride */\n+#define CMDQV_VCMDQ_PAGE0_BASE 0x10000 /* CMDQV_CMDQ_BASE */\n+#define CMDQV_VCMDQ_PAGE1_BASE 0x20000\n+#define CMDQV_VINTF_PAGE0_BASE 0x30000 /* CMDQV_VI_CMDQ_BASE */\n+#define CMDQV_VINTF_PAGE1_BASE 0x40000\n+#define CMDQV_VCMDQ_STRIDE 0x80\n+\n typedef struct Tegra241CMDQV {\n struct iommu_viommu_tegra241_cmdqv cmdqv_data;\n SMMUv3AccelState *s_accel;\n@@ -49,6 +56,14 @@ typedef struct Tegra241CMDQV {\n uint32_t vintf_sid_match[16];\n uint32_t vintf_sid_replace[16];\n uint32_t vintf_cmdq_err_map[4];\n+ uint32_t vcmdq_cons_indx[TEGRA241_CMDQV_MAX_CMDQ];\n+ uint32_t vcmdq_prod_indx[TEGRA241_CMDQV_MAX_CMDQ];\n+ uint32_t vcmdq_config[TEGRA241_CMDQV_MAX_CMDQ];\n+ uint32_t vcmdq_status[TEGRA241_CMDQV_MAX_CMDQ];\n+ uint32_t vcmdq_gerror[TEGRA241_CMDQV_MAX_CMDQ];\n+ uint32_t vcmdq_gerrorn[TEGRA241_CMDQV_MAX_CMDQ];\n+ uint64_t vcmdq_base[TEGRA241_CMDQV_MAX_CMDQ];\n+ uint64_t vcmdq_cons_indx_base[TEGRA241_CMDQV_MAX_CMDQ];\n } Tegra241CMDQV;\n \n /* CMDQ-V Config page registers (offset 0x00000) */\n@@ -160,6 +175,176 @@ SMMU_CMDQV_VINTFi_LVCMDQ_ERR_MAP_(0, 0)\n /* MAP_1 and MAP_2 omitted; not referenced directly */\n SMMU_CMDQV_VINTFi_LVCMDQ_ERR_MAP_(0, 3)\n \n+/*\n+ * VCMDQ register windows.\n+ *\n+ * Page 0 @ 0x10000: VCMDQ control and status registers\n+ * Page 1 @ 0x20000: VCMDQ base and DRAM address registers\n+ */\n+#define A_VCMDQi_CONS_INDX(i) \\\n+ REG32(VCMDQ##i##_CONS_INDX, 0x10000 + i * 0x80) \\\n+ FIELD(VCMDQ##i##_CONS_INDX, RD, 0, 20) \\\n+ FIELD(VCMDQ##i##_CONS_INDX, ERR, 24, 7)\n+\n+A_VCMDQi_CONS_INDX(0)\n+A_VCMDQi_CONS_INDX(1)\n+\n+#define V_VCMDQ_CONS_INDX_ERR_CERROR_NONE 0\n+#define V_VCMDQ_CONS_INDX_ERR_CERROR_ILL_OPCODE 1\n+#define V_VCMDQ_CONS_INDX_ERR_CERROR_ABT 2\n+#define V_VCMDQ_CONS_INDX_ERR_CERROR_ATC_INV_SYNC 3\n+#define V_VCMDQ_CONS_INDX_ERR_CERROR_ILL_ACCESS 4\n+\n+#define A_VCMDQi_PROD_INDX(i) \\\n+ REG32(VCMDQ##i##_PROD_INDX, 0x10000 + 0x4 + i * 0x80) \\\n+ FIELD(VCMDQ##i##_PROD_INDX, WR, 0, 20)\n+\n+A_VCMDQi_PROD_INDX(0)\n+A_VCMDQi_PROD_INDX(1)\n+\n+#define A_VCMDQi_CONFIG(i) \\\n+ REG32(VCMDQ##i##_CONFIG, 0x10000 + 0x8 + i * 0x80) \\\n+ FIELD(VCMDQ##i##_CONFIG, CMDQ_EN, 0, 1)\n+\n+A_VCMDQi_CONFIG(0)\n+A_VCMDQi_CONFIG(1)\n+\n+#define A_VCMDQi_STATUS(i) \\\n+ REG32(VCMDQ##i##_STATUS, 0x10000 + 0xc + i * 0x80) \\\n+ FIELD(VCMDQ##i##_STATUS, CMDQ_EN_OK, 0, 1)\n+\n+A_VCMDQi_STATUS(0)\n+A_VCMDQi_STATUS(1)\n+\n+#define A_VCMDQi_GERROR(i) \\\n+ REG32(VCMDQ##i##_GERROR, 0x10000 + 0x10 + i * 0x80) \\\n+ FIELD(VCMDQ##i##_GERROR, CMDQ_ERR, 0, 1) \\\n+ FIELD(VCMDQ##i##_GERROR, CONS_DRAM_WR_ABT_ERR, 1, 1) \\\n+ FIELD(VCMDQ##i##_GERROR, CMDQ_INIT_ERR, 2, 1)\n+\n+A_VCMDQi_GERROR(0)\n+A_VCMDQi_GERROR(1)\n+\n+#define A_VCMDQi_GERRORN(i) \\\n+ REG32(VCMDQ##i##_GERRORN, 0x10000 + 0x14 + i * 0x80) \\\n+ FIELD(VCMDQ##i##_GERRORN, CMDQ_ERR, 0, 1) \\\n+ FIELD(VCMDQ##i##_GERRORN, CONS_DRAM_WR_ABT_ERR, 1, 1) \\\n+ FIELD(VCMDQ##i##_GERRORN, CMDQ_INIT_ERR, 2, 1)\n+\n+A_VCMDQi_GERRORN(0)\n+A_VCMDQi_GERRORN(1)\n+\n+#define A_VCMDQi_BASE_L(i) \\\n+ REG32(VCMDQ##i##_BASE_L, 0x20000 + i * 0x80) \\\n+ FIELD(VCMDQ##i##_BASE_L, LOG2SIZE, 0, 5) \\\n+ FIELD(VCMDQ##i##_BASE_L, ADDR, 5, 27)\n+\n+A_VCMDQi_BASE_L(0)\n+A_VCMDQi_BASE_L(1)\n+\n+#define A_VCMDQi_BASE_H(i) \\\n+ REG32(VCMDQ##i##_BASE_H, 0x20000 + 0x4 + i * 0x80) \\\n+ FIELD(VCMDQ##i##_BASE_H, ADDR, 0, 16)\n+\n+A_VCMDQi_BASE_H(0)\n+A_VCMDQi_BASE_H(1)\n+\n+#define A_VCMDQi_CONS_INDX_BASE_DRAM_L(i) \\\n+ REG32(VCMDQ##i##_CONS_INDX_BASE_DRAM_L, 0x20000 + 0x8 + i * 0x80) \\\n+ FIELD(VCMDQ##i##_CONS_INDX_BASE_DRAM_L, ADDR, 0, 32)\n+\n+A_VCMDQi_CONS_INDX_BASE_DRAM_L(0)\n+A_VCMDQi_CONS_INDX_BASE_DRAM_L(1)\n+\n+#define A_VCMDQi_CONS_INDX_BASE_DRAM_H(i) \\\n+ REG32(VCMDQ##i##_CONS_INDX_BASE_DRAM_H, 0x20000 + 0xc + i * 0x80) \\\n+ FIELD(VCMDQ##i##_CONS_INDX_BASE_DRAM_H, ADDR, 0, 16)\n+\n+A_VCMDQi_CONS_INDX_BASE_DRAM_H(0)\n+A_VCMDQi_CONS_INDX_BASE_DRAM_H(1)\n+\n+/*\n+ * VI_VCMDQ register windows (VCMDQs mapped via VINTF).\n+ *\n+ * Page 0 @ 0x30000: VI_VCMDQ control and status registers\n+ * Page 1 @ 0x40000: VI_VCMDQ base and DRAM address registers\n+ */\n+#define A_VI_VCMDQi_CONS_INDX(i) \\\n+ REG32(VI_VCMDQ##i##_CONS_INDX, 0x30000 + i * 0x80) \\\n+ FIELD(VI_VCMDQ##i##_CONS_INDX, RD, 0, 20) \\\n+ FIELD(VI_VCMDQ##i##_CONS_INDX, ERR, 24, 7)\n+\n+A_VI_VCMDQi_CONS_INDX(0)\n+A_VI_VCMDQi_CONS_INDX(1)\n+\n+#define A_VI_VCMDQi_PROD_INDX(i) \\\n+ REG32(VI_VCMDQ##i##_PROD_INDX, 0x30000 + 0x4 + i * 0x80) \\\n+ FIELD(VI_VCMDQ##i##_PROD_INDX, WR, 0, 20)\n+\n+A_VI_VCMDQi_PROD_INDX(0)\n+A_VI_VCMDQi_PROD_INDX(1)\n+\n+#define A_VI_VCMDQi_CONFIG(i) \\\n+ REG32(VI_VCMDQ##i##_CONFIG, 0x30000 + 0x8 + i * 0x80) \\\n+ FIELD(VI_VCMDQ##i##_CONFIG, CMDQ_EN, 0, 1)\n+\n+A_VI_VCMDQi_CONFIG(0)\n+A_VI_VCMDQi_CONFIG(1)\n+\n+#define A_VI_VCMDQi_STATUS(i) \\\n+ REG32(VI_VCMDQ##i##_STATUS, 0x30000 + 0xc + i * 0x80) \\\n+ FIELD(VI_VCMDQ##i##_STATUS, CMDQ_EN_OK, 0, 1)\n+\n+A_VI_VCMDQi_STATUS(0)\n+A_VI_VCMDQi_STATUS(1)\n+\n+#define A_VI_VCMDQi_GERROR(i) \\\n+ REG32(VI_VCMDQ##i##_GERROR, 0x30000 + 0x10 + i * 0x80) \\\n+ FIELD(VI_VCMDQ##i##_GERROR, CMDQ_ERR, 0, 1) \\\n+ FIELD(VI_VCMDQ##i##_GERROR, CONS_DRAM_WR_ABT_ERR, 1, 1) \\\n+ FIELD(VI_VCMDQ##i##_GERROR, CMDQ_INIT_ERR, 2, 1)\n+\n+A_VI_VCMDQi_GERROR(0)\n+A_VI_VCMDQi_GERROR(1)\n+\n+#define A_VI_VCMDQi_GERRORN(i) \\\n+ REG32(VI_VCMDQ##i##_GERRORN, 0x30000 + 0x14 + i * 0x80) \\\n+ FIELD(VI_VCMDQ##i##_GERRORN, CMDQ_ERR, 0, 1) \\\n+ FIELD(VI_VCMDQ##i##_GERRORN, CONS_DRAM_WR_ABT_ERR, 1, 1) \\\n+ FIELD(VI_VCMDQ##i##_GERRORN, CMDQ_INIT_ERR, 2, 1)\n+\n+A_VI_VCMDQi_GERRORN(0)\n+A_VI_VCMDQi_GERRORN(1)\n+\n+#define A_VI_VCMDQi_BASE_L(i) \\\n+ REG32(VI_VCMDQ##i##_BASE_L, 0x40000 + i * 0x80) \\\n+ FIELD(VI_VCMDQ##i##_BASE_L, LOG2SIZE, 0, 5) \\\n+ FIELD(VI_VCMDQ##i##_BASE_L, ADDR, 5, 27)\n+\n+A_VI_VCMDQi_BASE_L(0)\n+A_VI_VCMDQi_BASE_L(1)\n+\n+#define A_VI_VCMDQi_BASE_H(i) \\\n+ REG32(VI_VCMDQ##i##_BASE_H, 0x40000 + 0x4 + i * 0x80) \\\n+ FIELD(VI_VCMDQ##i##_BASE_H, ADDR, 0, 16)\n+\n+A_VI_VCMDQi_BASE_H(0)\n+A_VI_VCMDQi_BASE_H(1)\n+\n+#define A_VI_VCMDQi_CONS_INDX_BASE_DRAM_L(i) \\\n+ REG32(VI_VCMDQ##i##_CONS_INDX_BASE_DRAM_L, 0x40000 + 0x8 + i * 0x80) \\\n+ FIELD(VI_VCMDQ##i##_CONS_INDX_BASE_DRAM_L, ADDR, 0, 32)\n+\n+A_VI_VCMDQi_CONS_INDX_BASE_DRAM_L(0)\n+A_VI_VCMDQi_CONS_INDX_BASE_DRAM_L(1)\n+\n+#define A_VI_VCMDQi_CONS_INDX_BASE_DRAM_H(i) \\\n+ REG32(VI_VCMDQ##i##_CONS_INDX_BASE_DRAM_H, 0x40000 + 0xc + i * 0x80) \\\n+ FIELD(VI_VCMDQ##i##_CONS_INDX_BASE_DRAM_H, ADDR, 0, 16)\n+\n+A_VI_VCMDQi_CONS_INDX_BASE_DRAM_H(0)\n+A_VI_VCMDQi_CONS_INDX_BASE_DRAM_H(1)\n+\n const SMMUv3AccelCmdqvOps *tegra241_cmdqv_get_ops(void);\n \n #endif /* HW_ARM_TEGRA241_CMDQV_H */\ndiff --git a/hw/arm/tegra241-cmdqv.c b/hw/arm/tegra241-cmdqv.c\nindex 3b08ed0ff3..35e6f0bbd6 100644\n--- a/hw/arm/tegra241-cmdqv.c\n+++ b/hw/arm/tegra241-cmdqv.c\n@@ -15,6 +15,46 @@\n #include \"tegra241-cmdqv.h\"\n #include \"trace.h\"\n \n+/*\n+ * Read a VCMDQ register using VCMDQ0_* offsets.\n+ *\n+ * The caller normalizes the MMIO offset such that @offset0 always refers\n+ * to a VCMDQ0_* register, while @index selects the VCMDQ instance.\n+ *\n+ * All VCMDQ accesses return cached registers.\n+ */\n+static uint64_t tegra241_cmdqv_read_vcmdq(Tegra241CMDQV *cmdqv, hwaddr offset0,\n+ int index)\n+{\n+ switch (offset0) {\n+ case A_VCMDQ0_CONS_INDX:\n+ return cmdqv->vcmdq_cons_indx[index];\n+ case A_VCMDQ0_PROD_INDX:\n+ return cmdqv->vcmdq_prod_indx[index];\n+ case A_VCMDQ0_CONFIG:\n+ return cmdqv->vcmdq_config[index];\n+ case A_VCMDQ0_STATUS:\n+ return cmdqv->vcmdq_status[index];\n+ case A_VCMDQ0_GERROR:\n+ return cmdqv->vcmdq_gerror[index];\n+ case A_VCMDQ0_GERRORN:\n+ return cmdqv->vcmdq_gerrorn[index];\n+ case A_VCMDQ0_BASE_L:\n+ return cmdqv->vcmdq_base[index];\n+ case A_VCMDQ0_BASE_H:\n+ return cmdqv->vcmdq_base[index] >> 32;\n+ case A_VCMDQ0_CONS_INDX_BASE_DRAM_L:\n+ return cmdqv->vcmdq_cons_indx_base[index];\n+ case A_VCMDQ0_CONS_INDX_BASE_DRAM_H:\n+ return cmdqv->vcmdq_cons_indx_base[index] >> 32;\n+ default:\n+ qemu_log_mask(LOG_UNIMP,\n+ \"%s unhandled read access at 0x%\" PRIx64 \"\\n\",\n+ __func__, offset0);\n+ return 0;\n+ }\n+}\n+\n static uint64_t tegra241_cmdqv_config_vintf_read(Tegra241CMDQV *cmdqv,\n hwaddr offset)\n {\n@@ -92,6 +132,7 @@ static uint64_t tegra241_cmdqv_read_mmio(void *opaque, hwaddr offset,\n {\n Tegra241CMDQV *cmdqv = (Tegra241CMDQV *)opaque;\n uint64_t val = 0;\n+ int index;\n \n if (offset >= TEGRA241_CMDQV_IO_LEN) {\n qemu_log_mask(LOG_UNIMP,\n@@ -125,6 +166,38 @@ static uint64_t tegra241_cmdqv_read_mmio(void *opaque, hwaddr offset,\n case A_VINTF0_CONFIG ... A_VINTF0_LVCMDQ_ERR_MAP_3:\n val = tegra241_cmdqv_config_vintf_read(cmdqv, offset);\n break;\n+ case A_VI_VCMDQ0_CONS_INDX ... A_VI_VCMDQ1_GERRORN:\n+ /*\n+ * VINTF Page0 registers have the same per-VCMDQ layout as the\n+ * VCMDQ Page0 registers. Translate the VINTF aperture offset to the\n+ * equivalent VCMDQ aperture offset, then fall through to reuse the\n+ * common VCMDQ decoding logic below.\n+ */\n+ offset -= CMDQV_VINTF_PAGE0_BASE - CMDQV_VCMDQ_PAGE0_BASE;\n+ QEMU_FALLTHROUGH;\n+ case A_VCMDQ0_CONS_INDX ... A_VCMDQ1_GERRORN:\n+ /*\n+ * Decode a per-VCMDQ register access.\n+ *\n+ * The hardware supports up to 128 identical VCMDQ instances; we\n+ * currently expose TEGRA241_CMDQV_MAX_CMDQ (= 2). Each VCMDQ\n+ * occupies a CMDQV_VCMDQ_STRIDE-byte window within the page.\n+ *\n+ * Extract the VCMDQ index and normalize to the VCMDQ0_* register\n+ * offset. A single helper services all instances via @index.\n+ */\n+ index = (offset - CMDQV_VCMDQ_PAGE0_BASE) / CMDQV_VCMDQ_STRIDE;\n+ return tegra241_cmdqv_read_vcmdq(cmdqv,\n+ offset - index * CMDQV_VCMDQ_STRIDE, index);\n+ case A_VI_VCMDQ0_BASE_L ... A_VI_VCMDQ1_CONS_INDX_BASE_DRAM_H:\n+ /* Same VINTF-to-VCMDQ translation as VINTF Page0 case above */\n+ offset -= CMDQV_VINTF_PAGE1_BASE - CMDQV_VCMDQ_PAGE1_BASE;\n+ QEMU_FALLTHROUGH;\n+ case A_VCMDQ0_BASE_L ... A_VCMDQ1_CONS_INDX_BASE_DRAM_H:\n+ /* Same decode logic as VCMDQ Page0 case above */\n+ index = (offset - CMDQV_VCMDQ_PAGE1_BASE) / CMDQV_VCMDQ_STRIDE;\n+ return tegra241_cmdqv_read_vcmdq(cmdqv,\n+ offset - index * CMDQV_VCMDQ_STRIDE, index);\n default:\n qemu_log_mask(LOG_UNIMP, \"%s unhandled read access at 0x%\" PRIx64 \"\\n\",\n __func__, offset);\n", "prefixes": [ "v4", "15/31" ] }