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GET /api/1.2/patches/2223470/?format=api
{ "id": 2223470, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2223470/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260415105552.622421-27-skolothumtho@nvidia.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.2/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260415105552.622421-27-skolothumtho@nvidia.com>", "list_archive_url": null, "date": "2026-04-15T10:55:47", "name": "[v4,26/31] hw/arm/tegra241-cmdqv: Limit queue size based on backend page size", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "56047c05ad46bea4ccc7b3b0caaf8e76442f7702", "submitter": { "id": 91580, "url": "http://patchwork.ozlabs.org/api/1.2/people/91580/?format=api", "name": "Shameer Kolothum Thodi", "email": "skolothumtho@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260415105552.622421-27-skolothumtho@nvidia.com/mbox/", "series": [ { "id": 499965, "url": "http://patchwork.ozlabs.org/api/1.2/series/499965/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=499965", "date": "2026-04-15T10:55:21", "name": "hw/arm/virt: Introduce Tegra241 CMDQV support for accelerated SMMUv3", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/499965/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2223470/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2223470/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=Q0gjRo97;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail.nvidia.com; pr=C", "permerror client-ip=2a01:111:f403:c112::7;\n envelope-from=skolothumtho@nvidia.com;\n helo=CY3PR05CU001.outbound.protection.outlook.com" ], "From": "Shameer Kolothum <skolothumtho@nvidia.com>", "To": "<qemu-arm@nongnu.org>, <qemu-devel@nongnu.org>", "CC": "<eric.auger@redhat.com>, <peter.maydell@linaro.org>, <clg@redhat.com>,\n <alex@shazbot.org>, <nicolinc@nvidia.com>, <nathanc@nvidia.com>,\n <mochs@nvidia.com>, <jan@nvidia.com>, <jgg@nvidia.com>,\n <jonathan.cameron@huawei.com>, <zhenzhong.duan@intel.com>,\n <kjaju@nvidia.com>, <phrdina@redhat.com>, <skolothumtho@nvidia.com>", "Subject": "[PATCH v4 26/31] hw/arm/tegra241-cmdqv: Limit queue size based on\n backend page size", "Date": "Wed, 15 Apr 2026 11:55:47 +0100", "Message-ID": "<20260415105552.622421-27-skolothumtho@nvidia.com>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260415105552.622421-1-skolothumtho@nvidia.com>", "References": "<20260415105552.622421-1-skolothumtho@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.230.37]", "X-ClientProxiedBy": "rnnvmail203.nvidia.com (10.129.68.9) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "BL02EPF00021F69:EE_|MW6PR12MB8708:EE_", "X-MS-Office365-Filtering-Correlation-Id": "5e84e054-a102-4066-b9a0-08de9addea3a", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;\n ARA:13230040|1800799024|36860700016|376014|82310400026|22082099003|18002099003|56012099003;", "X-Microsoft-Antispam-Message-Info": "\n i5F5wUCRBOtwPxmKplh7srHU3NWNYSrMrLJvl4KKoowQjJge5d7BXPt1O4Xu3aymeL2mroVuVtmsD8p3fheCkLgeva/K2E/T9ubRLPPkBM1MfvQhfNKd2DuecXMhksvjBz/veF1ozwWl0QIYFl0vvozJA5lwLDBQxye0OVejvc5bFxNdbexOwUCTE3dGEGqEgn27wKxib/89IuDe2CYgHivjzxA9f1AlyRm+oQuYuEulq2a/Fd1zm8exuGonUfA7TrU89ZNCVIKPTRmVkn1ABuguCArPwVpeQ0F9g/39q9L+1m23pbhONVKgDL3TD6JTZeC2QFAiMxULliW6P/x4ZXr1VAP0oK2lFMxk1eDYfAia18FTM5MYV65lMspjcbfqU1mPSw/4pW/c1hm0lO9lnp7am8XW6Q1vr9Az+HYzl00mLqVnfRk1E14nTFlNpwFRFsx+yOvPJ71wNIPa4x15fIN4L7h1ASBX9sPp6eAz0Dbu2u+z6W36RMwMCpYYUarwcdbyXlIunD1GzOhvibaaFXNddTwdOQ+ZP0ef4OFteNl/0IsGYlZU82msvvlPpIHdb9/Wz7ggYctuMbewoVk3HoMYKbyKRoN4ZC5tN4dchcw8oSzGVxLnKxWuXZgxYGXl5OlCIFVTk8RPkZg49PXpQx7HGjyIhSt8K2B5TlQ4P8e9TdePzyrj1QaZ2elRkM3lLPCdbqvyGyaI9emSMsX64Gc10ec67+143NsPRKS8jltCVhaC0rBzFGD49fK+3LT6okHRDtTdsD3KR/qS5mPOUw==", "X-Forefront-Antispam-Report": "CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE;\n SFS:(13230040)(1800799024)(36860700016)(376014)(82310400026)(22082099003)(18002099003)(56012099003);\n DIR:OUT; SFP:1101;", "X-MS-Exchange-AntiSpam-MessageData-ChunkCount": "1", "X-MS-Exchange-AntiSpam-MessageData-0": "\n zOjHtDT1QEnt6+uOgvD5KcJaJ3Wu+0l9puuBkrJpdyIPykaMtAqbL4pKz2SuaEnh7cSz1s7j1XAtdTtlAWHlOhK44IrUk/0evjCeLCj+a96wGDhwiKgD+rcGv4bfNW1GTFwrPkeOYDsW5/hBflRmGMTm9DFa0S7/52Hr/Wh0HB6vKSEBjJIF7SIrDX/RxFjSBMYcvXJEsRqgFchocklqdMHQc9TeYqR5nFwhEuhjAlaFDCXWr5dxQ4oMLadiFwbxAcgx3zqwM0plA4nFMnYl6Mpw7XaCQ74BfEUcQLc0rwUuTt+sXaFpefPmNippky1O4Y9W09uPvS5V4dDrPMnOiekN8cESIyMxtYCaNgHfPfXrlwL3Ku5UDGDiNh1Cs2IUfe1Nu9XFQur+4L4RhC2DhNHfzT1XFyojr65SvNSa8CX7RwVxRrnWQwcODi1AFhcr", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "15 Apr 2026 10:58:23.9422 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 5e84e054-a102-4066-b9a0-08de9addea3a", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BL02EPF00021F69.namprd02.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "MW6PR12MB8708", "X-Spam_score_int": "-15", "X-Spam_score": "-1.6", "X-Spam_bar": "-", "X-Spam_report": "(-1.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.54,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n FORGED_SPF_HELO=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001,\n SPF_NONE=0.001 autolearn=no autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "From: Nicolin Chen <nicolinc@nvidia.com>\n\nCMDQV HW reads guest queue memory in its host physical address setup via\nIOMMUFD. This requires the guest queue memory is not only contiguous in\nguest PA space but also in host PA space. With Tegra241 CMDQV enabled, we\nmust only advertise a CMDQS that the host can safely back with physically\ncontiguous memory. Allowing a queue larger than the host page size could\ncause the hardware to DMA across page boundaries, leading to faults.\n\nWalk the RAMBlock list to find the smallest memory-backend page size, then\nlimit IDR1.CMDQS so the guest cannot configure a command queue that exceeds\nthat contiguous backing. Fall back to the real host page size if no\nmemory-backend RAM blocks are found.\n\nSigned-off-by: Nicolin Chen <nicolinc@nvidia.com>\nSigned-off-by: Shameer Kolothum <skolothumtho@nvidia.com>\n---\n hw/arm/tegra241-cmdqv.c | 41 +++++++++++++++++++++++++++++++++++++++++\n 1 file changed, 41 insertions(+)", "diff": "diff --git a/hw/arm/tegra241-cmdqv.c b/hw/arm/tegra241-cmdqv.c\nindex af68add2f0..2870886783 100644\n--- a/hw/arm/tegra241-cmdqv.c\n+++ b/hw/arm/tegra241-cmdqv.c\n@@ -14,6 +14,9 @@\n #include \"hw/arm/smmuv3.h\"\n #include \"hw/core/irq.h\"\n #include \"smmuv3-accel.h\"\n+#include \"smmuv3-internal.h\"\n+#include \"system/ramblock.h\"\n+#include \"system/ramlist.h\"\n #include \"tegra241-cmdqv.h\"\n #include \"trace.h\"\n \n@@ -646,9 +649,38 @@ free_viommu:\n return false;\n }\n \n+static size_t tegra241_cmdqv_min_ram_pagesize(void)\n+{\n+ RAMBlock *rb;\n+ size_t pg, min_pg = SIZE_MAX;\n+\n+ RAMBLOCK_FOREACH(rb) {\n+ MemoryRegion *mr = rb->mr;\n+\n+ /* Only consider real RAM regions */\n+ if (!mr || !memory_region_is_ram(mr)) {\n+ continue;\n+ }\n+\n+ /* Skip RAM regions that are not backed by a memory-backend */\n+ if (!object_dynamic_cast(mr->owner, TYPE_MEMORY_BACKEND)) {\n+ continue;\n+ }\n+\n+ pg = qemu_ram_pagesize(rb);\n+ if (pg && pg < min_pg) {\n+ min_pg = pg;\n+ }\n+ }\n+\n+ return (min_pg == SIZE_MAX) ? qemu_real_host_page_size() : min_pg;\n+}\n+\n static void tegra241_cmdqv_init_regs(SMMUv3State *s, Tegra241CMDQV *cmdqv)\n {\n int i;\n+ size_t pgsize;\n+ uint32_t val;\n \n cmdqv->config = V_CONFIG_RESET;\n cmdqv->param = FIELD_DP32(0, PARAM, CMDQV_VER, CMDQV_VER);\n@@ -681,6 +713,15 @@ static void tegra241_cmdqv_init_regs(SMMUv3State *s, Tegra241CMDQV *cmdqv)\n cmdqv->vcmdq_base[i] = 0;\n cmdqv->vcmdq_cons_indx_base[i] = 0;\n }\n+\n+ /*\n+ * CMDQ must not cross a physical RAM backend page. Adjust CMDQS so the\n+ * queue fits entirely within the smallest backend page size, ensuring\n+ * the command queue is physically contiguous in host memory.\n+ */\n+ pgsize = tegra241_cmdqv_min_ram_pagesize();\n+ val = FIELD_EX32(s->idr[1], IDR1, CMDQS);\n+ s->idr[1] = FIELD_DP32(s->idr[1], IDR1, CMDQS, MIN(ctz64(pgsize) - 4, val));\n }\n \n static void tegra241_cmdqv_reset(SMMUv3State *s)\n", "prefixes": [ "v4", "26/31" ] }