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GET /api/1.2/patches/2223469/?format=api
{ "id": 2223469, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2223469/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260415105552.622421-28-skolothumtho@nvidia.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.2/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260415105552.622421-28-skolothumtho@nvidia.com>", "list_archive_url": null, "date": "2026-04-15T10:55:48", "name": "[v4,27/31] hw/arm/smmuv3: Add per-device identifier property", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "5c68e89e745074f9957b6605ea4e934ba2a94e0c", "submitter": { "id": 91580, "url": "http://patchwork.ozlabs.org/api/1.2/people/91580/?format=api", "name": "Shameer Kolothum Thodi", "email": "skolothumtho@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260415105552.622421-28-skolothumtho@nvidia.com/mbox/", "series": [ { "id": 499965, "url": "http://patchwork.ozlabs.org/api/1.2/series/499965/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=499965", "date": "2026-04-15T10:55:21", "name": "hw/arm/virt: Introduce Tegra241 CMDQV support for accelerated SMMUv3", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/499965/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2223469/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2223469/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=aUZGyc+t;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail.nvidia.com; pr=C", "permerror client-ip=2a01:111:f403:c105::1;\n envelope-from=skolothumtho@nvidia.com;\n helo=CH1PR05CU001.outbound.protection.outlook.com" ], "From": "Shameer Kolothum <skolothumtho@nvidia.com>", "To": "<qemu-arm@nongnu.org>, <qemu-devel@nongnu.org>", "CC": "<eric.auger@redhat.com>, <peter.maydell@linaro.org>, <clg@redhat.com>,\n <alex@shazbot.org>, <nicolinc@nvidia.com>, <nathanc@nvidia.com>,\n <mochs@nvidia.com>, <jan@nvidia.com>, <jgg@nvidia.com>,\n <jonathan.cameron@huawei.com>, <zhenzhong.duan@intel.com>,\n <kjaju@nvidia.com>, <phrdina@redhat.com>, <skolothumtho@nvidia.com>", "Subject": "[PATCH v4 27/31] hw/arm/smmuv3: Add per-device identifier property", "Date": "Wed, 15 Apr 2026 11:55:48 +0100", "Message-ID": "<20260415105552.622421-28-skolothumtho@nvidia.com>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260415105552.622421-1-skolothumtho@nvidia.com>", "References": "<20260415105552.622421-1-skolothumtho@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.230.37]", "X-ClientProxiedBy": "rnnvmail203.nvidia.com (10.129.68.9) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "BL02EPF00021F69:EE_|DM4PR12MB5915:EE_", "X-MS-Office365-Filtering-Correlation-Id": "a1bed5c0-ceca-44d9-e4f7-08de9added49", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;\n ARA:13230040|36860700016|376014|82310400026|1800799024|56012099003|18002099003|22082099003;", "X-Microsoft-Antispam-Message-Info": "\n +w2LH0tKBK0im6uTNFUmpmcjJK186gHeFuNs8Y4ocoxlDK48RQSP2PVkgL4N9jKkC75W3al7WBSJm/laFu6m0cO7VUvUYiD7ELc+xtOJvlaf68ddSLVWRGofQwV9DmkwS0BYoJNvk3vciiW0cjmxxRB2lqD5WQXV3wFWmwzAeg6w/HgBC4ouves0Azw8b6JJqX79xa8yCm51pBGHr205AAm4v22i8aX8Ae9BhoBgbQxpueXArXBBkEUlzUNC+uqpetfzSlt04oIF71igdbt24MObtyySNl9uLSW4Kci8XAIjKIjo30mTSmKxLadEr2A/BrQSLtPJZNdvOBfxnVl8u9pNyc8BiHpqU0hTWjosSk7V6EgV40jGkHjU2AQ3fZLecgDrVNYDAuktdrWagt2MpHnwqwQUWVNyI3ieX0U3vChoBIp71KD5Uk/74OOh4qladOX42dqN0SXvoC3quIVK8huBU1UT6iJUnVH4GSNpQbAad4yE1qnOXgmha4gmVSj0zbOWEbIw0BF5hIWr4qVb9cVYQkez68QEJU/x8bpzBV/VXFTG04EPrCm78AST5Y37XOLuUw2ZpmQ/WB/96Z1OPuOc9xiqLbiBlFXKCbAwPeW6BiOosBCLGcWCpLKPU8zza99hyV2bQIyZHH3MlVdSm1A+CGyQn3mABFhxnGea7ADVIDXz3b3JN+0sBzBXOkgpuZXZvRyv82T8If7WQGhEF4m0zwf0/PnFzyR6jvzeoX0jd50hodyTp/efxZhPaeOhHd7Y4qen5JweODA2M3pimw==", "X-Forefront-Antispam-Report": "CIP:216.228.117.161; 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Ip=[216.228.117.161];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BL02EPF00021F69.namprd02.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DM4PR12MB5915", "X-Spam_score_int": "-15", "X-Spam_score": "-1.6", "X-Spam_bar": "-", "X-Spam_report": "(-1.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.54,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n FORGED_SPF_HELO=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001,\n SPF_NONE=0.001 autolearn=no autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Add an \"identifier\" property to the SMMUv3 device and use it when\nbuilding the ACPI IORT SMMUv3 node Identifier field.\n\nThis avoids relying on device enumeration order and provides a stable\nper-device identifier. A subsequent patch will use the same identifier\nwhen generating the DSDT description for Tegra241 CMDQV, ensuring that\nthe IORT and DSDT entries refer to the same SMMUv3 instance.\n\nThe identifier is assigned at pre-plug time, accounting for the ITS Group\nnode that build_iort() places before SMMUv3 nodes in the IORT table, so\nthat identifiers are globally unique across all IORT nodes.\n\nNo functional change: IORT blob content for bios-tables qtest is identical\nto before.\n\nReviewed-by: Eric Auger <eric.auger@redhat.com>\nSigned-off-by: Shameer Kolothum <skolothumtho@nvidia.com>\n---\n include/hw/arm/smmuv3.h | 1 +\n hw/arm/smmuv3.c | 2 ++\n hw/arm/virt-acpi-build.c | 5 ++++-\n hw/arm/virt.c | 12 ++++++++++++\n 4 files changed, 19 insertions(+), 1 deletion(-)", "diff": "diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h\nindex aa6a79237a..0fce564619 100644\n--- a/include/hw/arm/smmuv3.h\n+++ b/include/hw/arm/smmuv3.h\n@@ -64,6 +64,7 @@ struct SMMUv3State {\n qemu_irq irq[4];\n QemuMutex mutex;\n char *stage;\n+ uint8_t identifier;\n \n /* SMMU has HW accelerator support for nested S1 + s2 */\n bool accel;\ndiff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c\nindex 682d89c3ea..1d6fdd776c 100644\n--- a/hw/arm/smmuv3.c\n+++ b/hw/arm/smmuv3.c\n@@ -2144,6 +2144,8 @@ static const Property smmuv3_properties[] = {\n * Defaults to stage 1\n */\n DEFINE_PROP_STRING(\"stage\", SMMUv3State, stage),\n+ /* Identifier used for ACPI IORT SMMUv3 (and DSDT for CMDQV) generation */\n+ DEFINE_PROP_UINT8(\"identifier\", SMMUv3State, identifier, 0),\n DEFINE_PROP_BOOL(\"accel\", SMMUv3State, accel, false),\n /* GPA of MSI doorbell, for SMMUv3 accel use. */\n DEFINE_PROP_UINT64(\"msi-gpa\", SMMUv3State, msi_gpa, 0),\ndiff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c\nindex 521443de87..65ccc96349 100644\n--- a/hw/arm/virt-acpi-build.c\n+++ b/hw/arm/virt-acpi-build.c\n@@ -342,6 +342,7 @@ static int iort_idmap_compare(gconstpointer a, gconstpointer b)\n typedef struct AcpiIortSMMUv3Dev {\n int irq;\n hwaddr base;\n+ uint8_t id;\n GArray *rc_smmu_idmaps;\n /* Offset of the SMMUv3 IORT Node relative to the start of the IORT */\n size_t offset;\n@@ -404,6 +405,7 @@ static int populate_smmuv3_dev(VirtMachineState *vms, GArray *sdev_blob)\n &error_abort));\n sdev.accel = object_property_get_bool(obj, \"accel\", &error_abort);\n sdev.ats = smmuv3_ats_enabled(ARM_SMMUV3(obj));\n+ sdev.id = object_property_get_uint(obj, \"identifier\", &error_abort);\n pbus = PLATFORM_BUS_DEVICE(vms->platform_bus_dev);\n sbdev = SYS_BUS_DEVICE(obj);\n sdev.base = platform_bus_get_mmio_addr(pbus, sbdev, 0);\n@@ -630,7 +632,8 @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)\n (ID_MAPPING_ENTRY_SIZE * smmu_mapping_count);\n build_append_int_noprefix(table_data, node_size, 2); /* Length */\n build_append_int_noprefix(table_data, 4, 1); /* Revision */\n- build_append_int_noprefix(table_data, id++, 4); /* Identifier */\n+ build_append_int_noprefix(table_data, sdev->id, 4); /* Identifier */\n+ id++; /* advance shared counter for RC/RMR node uniqueness */\n /* Number of ID mappings */\n build_append_int_noprefix(table_data, smmu_mapping_count, 4);\n /* Reference to ID Array */\ndiff --git a/hw/arm/virt.c b/hw/arm/virt.c\nindex 6c5e51af37..22d6b9eec9 100644\n--- a/hw/arm/virt.c\n+++ b/hw/arm/virt.c\n@@ -240,6 +240,9 @@ static MemMapEntry extended_memmap[] = {\n /* Any CXL Fixed memory windows come here */\n };\n \n+/* Counts SMMUv3 devices plugged; used to assign stable IORT identifiers */\n+static uint8_t smmuv3_dev_id;\n+\n static const int a15irqmap[] = {\n [VIRT_UART0] = 1,\n [VIRT_RTC] = 2,\n@@ -3226,6 +3229,15 @@ static void virt_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev,\n OBJECT(vms->sysmem), NULL);\n object_property_set_link(OBJECT(dev), \"secure-memory\",\n OBJECT(vms->secure_sysmem), NULL);\n+ /*\n+ * In build_iort(), the ITS node(id=0) precedes SMMUv3 nodes\n+ * when present. Account for it so this SMMUv3's identifier\n+ * is globally unique across all IORT nodes.\n+ */\n+ uint8_t its_offset = (vms->msi_controller == VIRT_MSI_CTRL_ITS)\n+ ? 1 : 0;\n+ object_property_set_uint(OBJECT(dev), \"identifier\",\n+ its_offset + smmuv3_dev_id++, NULL);\n }\n if (object_property_get_bool(OBJECT(dev), \"accel\", &error_abort)) {\n hwaddr db_start = 0;\n", "prefixes": [ "v4", "27/31" ] }