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GET /api/1.2/patches/2223467/?format=api
{ "id": 2223467, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2223467/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260415105552.622421-18-skolothumtho@nvidia.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.2/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260415105552.622421-18-skolothumtho@nvidia.com>", "list_archive_url": null, "date": "2026-04-15T10:55:38", "name": "[v4,17/31] hw/arm/tegra241-cmdqv: mmap VINTF Page0 for CMDQV", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "9dae0a50bb4354b5b792081ceefdea08bd529765", "submitter": { "id": 91580, "url": "http://patchwork.ozlabs.org/api/1.2/people/91580/?format=api", "name": "Shameer Kolothum Thodi", "email": "skolothumtho@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260415105552.622421-18-skolothumtho@nvidia.com/mbox/", "series": [ { "id": 499965, "url": "http://patchwork.ozlabs.org/api/1.2/series/499965/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=499965", "date": "2026-04-15T10:55:21", "name": "hw/arm/virt: Introduce Tegra241 CMDQV support for accelerated SMMUv3", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/499965/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2223467/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2223467/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=bYE9fVwF;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail.nvidia.com; pr=C", "permerror client-ip=2a01:111:f403:c10d::3;\n envelope-from=skolothumtho@nvidia.com;\n helo=SN4PR0501CU005.outbound.protection.outlook.com" ], "From": "Shameer Kolothum <skolothumtho@nvidia.com>", "To": "<qemu-arm@nongnu.org>, <qemu-devel@nongnu.org>", "CC": "<eric.auger@redhat.com>, <peter.maydell@linaro.org>, <clg@redhat.com>,\n <alex@shazbot.org>, <nicolinc@nvidia.com>, <nathanc@nvidia.com>,\n <mochs@nvidia.com>, <jan@nvidia.com>, <jgg@nvidia.com>,\n <jonathan.cameron@huawei.com>, <zhenzhong.duan@intel.com>,\n <kjaju@nvidia.com>, <phrdina@redhat.com>, <skolothumtho@nvidia.com>", "Subject": "[PATCH v4 17/31] hw/arm/tegra241-cmdqv: mmap VINTF Page0 for CMDQV", "Date": "Wed, 15 Apr 2026 11:55:38 +0100", "Message-ID": "<20260415105552.622421-18-skolothumtho@nvidia.com>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260415105552.622421-1-skolothumtho@nvidia.com>", "References": "<20260415105552.622421-1-skolothumtho@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.230.37]", "X-ClientProxiedBy": "rnnvmail203.nvidia.com (10.129.68.9) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "BL02EPF00021F6B:EE_|SA0PR12MB4431:EE_", "X-MS-Office365-Filtering-Correlation-Id": "f71560e3-b2d4-44e7-527f-08de9addd866", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;\n ARA:13230040|36860700016|376014|82310400026|1800799024|56012099003|22082099003|18002099003;", "X-Microsoft-Antispam-Message-Info": "\n nLjso9eo5CY86I39Mylgpsbz9O0+tvqYu6H1NbW+0+Co6ITsGdPGvWD7qh4u5hF7E1dcnsxOwTyg4e6UTl5xru+1vME80ghuAf36FuUa/xfErV4upfk4c9TlN83HGFPE/Wta6KNhJvUFujajqOD5Qivt4LXqbU2WMc316dqPl/prZ2jxV0lbXxsLt9hlKk4hPkh9U8b+11TNAj15jOLWfSoJ91x7C+F7kM1zsyJ7Mrf276g7l6dmdhIecQQSMloUt4KU641IVdNHL1JmynMZlEkdMxLNRHKqMhuRoL8Ot9lkBiB/lFCUslojYqMNkbJSZjuyJa9rhVpyz3NFcjkm/Aur5LO/EUM8JmJuZikGFZtS6mngSLIciCwAWFIXbm/4xt/UhhozrJDq7g3aYq0Y3he6tc7I4rVST5f04ZwMsgkviFgZ5230TTH8jQ+ZwazU9xLYbZO90QY0wgdvDXC9p6Vu58VehuM7JLC/U9rSNCWzMKE9arlPhdW6ke+H7qtH/olwBqXwcsguoS3KFt+ZhQU5Tc2u9rQWPs3tkhvsEMuJeKy67NwBmggjkQ5x/2C6MbPUMbzAbVEEJA6tScqVhUKd4qdZvgrJZjYHI1p63nMAwyeDMNChZzZJoZYCZbY/JSTCcJsJMasArjM92l9UzhnU0ZAWVf9yn5w/Q+PJM90acquqI91tV8/jy87Y2Zqmshs85oh8jL9tt1jrsHWiVuifo3cNNLNIZbxONOt6bBsd1KoCVzsN68hTR0shuXac1c2ijM0sjEv9kMj3eCzp4A==", "X-Forefront-Antispam-Report": "CIP:216.228.117.161; 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Ip=[216.228.117.161];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BL02EPF00021F6B.namprd02.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "SA0PR12MB4431", "X-Spam_score_int": "-25", "X-Spam_score": "-2.6", "X-Spam_bar": "--", "X-Spam_report": "(-2.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.54,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "From: Nicolin Chen <nicolinc@nvidia.com>\n\nThe CMDQ-V CMDQ pages provide a VM wide view of all VCMDQs, while the\nVINTF pages expose a logical view local to a given VINTF. Although real\nhardware may support multiple VINTFs, the kernel currently exposes a\nsingle VINTF per VM.\n\nThe kernel provides an mmap offset for the VINTF Page0 region during\nvIOMMU allocation. However, the logical-to-physical association between\nVCMDQs and a VINTF is only established after HW_QUEUE allocation. Prior\nto that, the mapped Page0 does not back any real VCMDQ state.\n\nWhen VINTF is enabled, mmap the kernel provided Page0 region and set\nENABLE_OK only if the mmap succeeds. Unmap it when VINTF is disabled.\nThis prepares the VINTF mapping in advance of subsequent patches that\nadd VCMDQ allocation support.\n\nSigned-off-by: Nicolin Chen <nicolinc@nvidia.com>\nCo-developed-by: Shameer Kolothum <skolothumtho@nvidia.com>\nSigned-off-by: Shameer Kolothum <skolothumtho@nvidia.com>\n---\n hw/arm/tegra241-cmdqv.h | 3 +++\n hw/arm/tegra241-cmdqv.c | 47 ++++++++++++++++++++++++++++++++++++++---\n 2 files changed, 47 insertions(+), 3 deletions(-)", "diff": "diff --git a/hw/arm/tegra241-cmdqv.h b/hw/arm/tegra241-cmdqv.h\nindex b8bd8cd8ff..88572ad939 100644\n--- a/hw/arm/tegra241-cmdqv.h\n+++ b/hw/arm/tegra241-cmdqv.h\n@@ -18,6 +18,8 @@\n \n #define TEGRA241_CMDQV_MAX_CMDQ (1U << CMDQV_NUM_CMDQ_LOG2)\n \n+#define VINTF_PAGE_SIZE 0x10000\n+\n /*\n * Tegra241 CMDQV MMIO layout (64KB pages)\n *\n@@ -42,6 +44,7 @@ typedef struct Tegra241CMDQV {\n MemoryRegion mmio_cmdqv;\n qemu_irq irq;\n IOMMUFDVeventq *veventq;\n+ void *vintf_page0;\n \n /* Register Cache */\n uint32_t config;\ndiff --git a/hw/arm/tegra241-cmdqv.c b/hw/arm/tegra241-cmdqv.c\nindex d4ba2ada92..cdd941cec9 100644\n--- a/hw/arm/tegra241-cmdqv.c\n+++ b/hw/arm/tegra241-cmdqv.c\n@@ -119,6 +119,39 @@ static void tegra241_cmdqv_write_vcmdq(Tegra241CMDQV *cmdqv, hwaddr offset0,\n }\n }\n \n+static bool\n+tegra241_cmdqv_munmap_vintf_page0(Tegra241CMDQV *cmdqv, Error **errp)\n+{\n+ if (!cmdqv->vintf_page0) {\n+ return true;\n+ }\n+\n+ if (munmap(cmdqv->vintf_page0, VINTF_PAGE_SIZE) < 0) {\n+ error_setg_errno(errp, errno, \"Failed to unmap VINTF page0\");\n+ return false;\n+ }\n+ cmdqv->vintf_page0 = NULL;\n+ return true;\n+}\n+\n+static bool tegra241_cmdqv_mmap_vintf_page0(Tegra241CMDQV *cmdqv, Error **errp)\n+{\n+ IOMMUFDViommu *viommu = cmdqv->s_accel->viommu;\n+\n+ if (cmdqv->vintf_page0) {\n+ return true;\n+ }\n+\n+ if (!iommufd_backend_viommu_mmap(viommu->iommufd, viommu->viommu_id,\n+ VINTF_PAGE_SIZE,\n+ cmdqv->cmdqv_data.out_vintf_mmap_offset,\n+ &cmdqv->vintf_page0, errp)) {\n+ return false;\n+ }\n+\n+ return true;\n+}\n+\n static uint64_t tegra241_cmdqv_config_vintf_read(Tegra241CMDQV *cmdqv,\n hwaddr offset)\n {\n@@ -151,7 +184,8 @@ static uint64_t tegra241_cmdqv_config_vintf_read(Tegra241CMDQV *cmdqv,\n }\n \n static void tegra241_cmdqv_config_vintf_write(Tegra241CMDQV *cmdqv,\n- hwaddr offset, uint64_t value)\n+ hwaddr offset, uint64_t value,\n+ Error **errp)\n {\n int i;\n \n@@ -166,8 +200,11 @@ static void tegra241_cmdqv_config_vintf_write(Tegra241CMDQV *cmdqv,\n \n cmdqv->vintf_config = value;\n if (value & R_VINTF0_CONFIG_ENABLE_MASK) {\n- cmdqv->vintf_status |= R_VINTF0_STATUS_ENABLE_OK_MASK;\n+ if (tegra241_cmdqv_mmap_vintf_page0(cmdqv, errp)) {\n+ cmdqv->vintf_status |= R_VINTF0_STATUS_ENABLE_OK_MASK;\n+ }\n } else {\n+ tegra241_cmdqv_munmap_vintf_page0(cmdqv, errp);\n cmdqv->vintf_status &= ~R_VINTF0_STATUS_ENABLE_OK_MASK;\n }\n break;\n@@ -276,6 +313,7 @@ static void tegra241_cmdqv_write_mmio(void *opaque, hwaddr offset,\n uint64_t value, unsigned size)\n {\n Tegra241CMDQV *cmdqv = (Tegra241CMDQV *)opaque;\n+ Error *local_err = NULL;\n int index;\n \n if (offset >= TEGRA241_CMDQV_IO_LEN) {\n@@ -301,7 +339,7 @@ static void tegra241_cmdqv_write_mmio(void *opaque, hwaddr offset,\n cmdqv->cmdq_alloc_map[(offset - A_CMDQ_ALLOC_MAP_0) / 4] = value;\n break;\n case A_VINTF0_CONFIG ... A_VINTF0_LVCMDQ_ERR_MAP_3:\n- tegra241_cmdqv_config_vintf_write(cmdqv, offset, value);\n+ tegra241_cmdqv_config_vintf_write(cmdqv, offset, value, &local_err);\n break;\n case A_VI_VCMDQ0_CONS_INDX ... A_VI_VCMDQ1_GERRORN:\n /*\n@@ -343,6 +381,9 @@ static void tegra241_cmdqv_write_mmio(void *opaque, hwaddr offset,\n }\n \n out:\n+ if (local_err) {\n+ error_report_err(local_err);\n+ }\n trace_tegra241_cmdqv_write_mmio(offset, value, size);\n }\n \n", "prefixes": [ "v4", "17/31" ] }