Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/1.2/patches/2223466/?format=api
{ "id": 2223466, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2223466/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260415105552.622421-4-skolothumtho@nvidia.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.2/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260415105552.622421-4-skolothumtho@nvidia.com>", "list_archive_url": null, "date": "2026-04-15T10:55:24", "name": "[v4,03/31] backends/iommufd: Introduce iommufd_backend_alloc_hw_queue", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "d0aee5a8c93fe87d8b3114c135041c0773cfc1c2", "submitter": { "id": 91580, "url": "http://patchwork.ozlabs.org/api/1.2/people/91580/?format=api", "name": "Shameer Kolothum Thodi", "email": "skolothumtho@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260415105552.622421-4-skolothumtho@nvidia.com/mbox/", "series": [ { "id": 499965, "url": "http://patchwork.ozlabs.org/api/1.2/series/499965/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=499965", "date": "2026-04-15T10:55:21", "name": "hw/arm/virt: Introduce Tegra241 CMDQV support for accelerated SMMUv3", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/499965/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2223466/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2223466/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=ZiyzNEWL;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fwdWq0Vrtz1yDF\n\tfor <incoming@patchwork.ozlabs.org>; Wed, 15 Apr 2026 21:02:15 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1wCxw8-0000hG-Fp; Wed, 15 Apr 2026 06:57:36 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <skolothumtho@nvidia.com>)\n id 1wCxvp-0000ZO-Ed; Wed, 15 Apr 2026 06:57:17 -0400", "from mail-westus3azlp170120001.outbound.protection.outlook.com\n ([2a01:111:f403:c107::1] helo=PH8PR06CU001.outbound.protection.outlook.com)\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <skolothumtho@nvidia.com>)\n id 1wCxvn-0003vb-R0; Wed, 15 Apr 2026 06:57:17 -0400", "from PH0P220CA0019.NAMP220.PROD.OUTLOOK.COM (2603:10b6:510:d3::32)\n by IA1PR12MB6530.namprd12.prod.outlook.com (2603:10b6:208:3a5::20) with\n Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9769.48; Wed, 15 Apr\n 2026 10:57:08 +0000", "from CY4PEPF0000EE3E.namprd03.prod.outlook.com\n (2603:10b6:510:d3:cafe::63) by PH0P220CA0019.outlook.office365.com\n (2603:10b6:510:d3::32) with Microsoft SMTP Server (version=TLS1_3,\n cipher=TLS_AES_256_GCM_SHA384) id 15.20.9769.48 via Frontend Transport; Wed,\n 15 Apr 2026 10:57:08 +0000", "from mail.nvidia.com (216.228.117.160) by\n CY4PEPF0000EE3E.mail.protection.outlook.com (10.167.242.16) with Microsoft\n SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n 15.20.9769.17 via Frontend Transport; Wed, 15 Apr 2026 10:57:07 +0000", "from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com\n (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Wed, 15 Apr\n 2026 03:56:43 -0700", "from NV-2Y5XW94.nvidia.com (10.126.230.37) by rnnvmail201.nvidia.com\n (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Wed, 15 Apr\n 2026 03:56:40 -0700" ], "ARC-Seal": "i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none;\n b=qxWCe5fnVwQ0153CGF9HJkgvIOfn/Uz1ZqEqxfDOZWq7cHP3e7rFIroqPykAVr1ty1HN9e06Z8yDNCn0w7fpf8ih6fkjE97lQWqo8JV4eOMqcU9h9nfbu3zcYOT2NEUFjFqMo2scC+iBqbsfiRu/cxOBjMggMOgnz5SGxLbaq8eCybtoetNVqa78OfcaQ0uS2XUsU7VTyHgo+gHQXV8QZOAZX27wXl7A1U6GGfzvVvWWV2EdQuRWMMnX+xsNUntAHyhCpXoaJ/5BU/vZ5wXoIkYdAmnhBKYkh3mSjJ2NV+naLXLY5FHb7ZHjKAWkD2fewlqxmWuR8LRiXh2pJTobsQ==", "ARC-Message-Signature": "i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;\n s=arcselector10001;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1;\n bh=PC2i2AaQFQeA2wlDdXGRP3iXccK6xjdagJvYwAFr88s=;\n b=NtL4ecXZCtEihXHKfNbETRZA04zzOKV/pUQpV2nMGyS47hK0416EvZkGv7JJwm5ZJGLBCTl5GrbgZZ0I5yCx59sW9130UPDNjDEV7I0YG5Cr46dJ1NjTafxEp97lTuzxI+RJDZ0o915A76Y+aXAJozjS0fKu5r0d4caQ/2UcxD5XY2JC7cTL0vEj6QlZYxxslDapjYGAw/SuZxxlJzfvrKYtBJf4gU76NvjVgDJP2oL2+Rczg7WRrXQcU9gOxDAoCIEsFolM8ADWtRPkcxLw/BboA4BwBmxmqikBkaCQ3z3YXG6WJgle01UUkE73xt5Fq/U91V0TXnxyvbYMxzY15g==", "ARC-Authentication-Results": "i=1; mx.microsoft.com 1; spf=pass (sender ip is\n 216.228.117.160) smtp.rcpttodomain=nongnu.org smtp.mailfrom=nvidia.com;\n dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com;\n dkim=none (message not signed); arc=none (0)", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=PC2i2AaQFQeA2wlDdXGRP3iXccK6xjdagJvYwAFr88s=;\n b=ZiyzNEWLGCvg2l4qexC9j7vYVTQpyKsquVAYs/K8LE5pX/yemjGaef5y01B2ZrlLCI9vnU6rZ4x8tuSoPd2IJY0jl/hi1Lv13XkihwgdexsfYu1epPvg/GmaV//GHLuFRJkuO3a1JJPll8yAw+Se7XSH3EjzFcGUXZ95nCmiZhDhZtG1n4N/lD09YysQaat1/hwdxlrsIt1vEbTCWWFPohUcCNM0rF58DOyzVtiA1agcXrk4kxsD77xiscSq/TZXRRBXa3EpmC7U5IBt/IK/GE4GbsTrXVjnIGOsg2fD/c8FTR7YHhfJ6WDwFYyJKIzLHykE4IgQqprDNA4oM0DccA==", "X-MS-Exchange-Authentication-Results": "spf=pass (sender IP is 216.228.117.160)\n smtp.mailfrom=nvidia.com;\n dkim=none (message not signed)\n header.d=none;dmarc=pass action=none header.from=nvidia.com;", "Received-SPF": [ "Pass (protection.outlook.com: domain of nvidia.com designates\n 216.228.117.160 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C", "permerror client-ip=2a01:111:f403:c107::1;\n envelope-from=skolothumtho@nvidia.com;\n helo=PH8PR06CU001.outbound.protection.outlook.com" ], "From": "Shameer Kolothum <skolothumtho@nvidia.com>", "To": "<qemu-arm@nongnu.org>, <qemu-devel@nongnu.org>", "CC": "<eric.auger@redhat.com>, <peter.maydell@linaro.org>, <clg@redhat.com>,\n <alex@shazbot.org>, <nicolinc@nvidia.com>, <nathanc@nvidia.com>,\n <mochs@nvidia.com>, <jan@nvidia.com>, <jgg@nvidia.com>,\n <jonathan.cameron@huawei.com>, <zhenzhong.duan@intel.com>,\n <kjaju@nvidia.com>, <phrdina@redhat.com>, <skolothumtho@nvidia.com>", "Subject": "[PATCH v4 03/31] backends/iommufd: Introduce\n iommufd_backend_alloc_hw_queue", "Date": "Wed, 15 Apr 2026 11:55:24 +0100", "Message-ID": "<20260415105552.622421-4-skolothumtho@nvidia.com>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260415105552.622421-1-skolothumtho@nvidia.com>", "References": "<20260415105552.622421-1-skolothumtho@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.230.37]", "X-ClientProxiedBy": "rnnvmail203.nvidia.com (10.129.68.9) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "CY4PEPF0000EE3E:EE_|IA1PR12MB6530:EE_", "X-MS-Office365-Filtering-Correlation-Id": "8fa78ae7-ee30-4cc5-0567-08de9addbcea", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;\n ARA:13230040|376014|1800799024|36860700016|82310400026|56012099003|22082099003|18002099003;", "X-Microsoft-Antispam-Message-Info": "\n 6L/13Rn3574vdzADHRepjluxYkCBeoVnzljeGlTQIF3ZSx4Fl1IcQZo9mYNaLa1f8vjRRVmcySQicLulYiWVo2E+I4yVxwTMj0DWS+jHHDpp+1jclbPzJ3+mVYNF1ar/3kyAq97k0P8OfJqXb/jkieSt5y9Ob24ORGOnpwauFUACkqumLISi8SryybJiai7lpg6/hXg3B6wwsX7aMkryjCFthK5sHtTdZXF3ZCnbHdXGagFb9iKVoVxxccx9U5xxyxXx4feZDOMxcGtouTzPQ9EVVHp/CklS9NNZ0Bq72Ibd9t/sRaTcbTLLQpJAnzmQvv5pttLTkgsDwQXWKmfSAIRPYd4bSUJSBcOrDJVOV3sIQCspZnS61Bjn84OtCkFeWSMpZWUtoI4eApX4Dspm+fdlQjHuHtBakEFOuJc2KDKyLu6cZzXNk8fGpJ978LdYGT/Uw2HEI/9DMM3aCHOCzcsi/y+6nYxtr89ngyX/rw/fz5Mi+W1LfWX+E/zDaJmTR0LoETGh6GBZ75rmjZWBU+4FAlD95Qm90e2gCdt1W8yPXK86P/COemmOTMEAuASTAo3GTjiKZpuyuTUP/BJY7LMhqKpqqq1hExFPYXPvTVw8jaomKc0vMe+6NmGJlih6ucXD0gLZ0kEKJMvADr9wD7FLTdrMAYq4JXZ4M22skmAHMSGiJoyCX2Mh+eWnSGVCTSe3s0frc1PsqXMtrpSLEGFr6LVtVDzShLFom1KTby7kKGluF+vOPSAzH7+ZDE0vofXeKFngdKSdoDL9SVmosw==", "X-Forefront-Antispam-Report": "CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE;\n SFS:(13230040)(376014)(1800799024)(36860700016)(82310400026)(56012099003)(22082099003)(18002099003);\n DIR:OUT; SFP:1101;", "X-MS-Exchange-AntiSpam-MessageData-ChunkCount": "1", "X-MS-Exchange-AntiSpam-MessageData-0": "\n XnlDj5mCIIgySILEcHjoPu9lJLiqSxh7VPCEe626ub1cyqQ7y0UXFgzprGga8f2w4hUitregu2hOWSV0nI9R+ewxBJq6BrksQLdnT7yo2o58m82G8DsWB10AbjTQEqM8LZuM5cN06WJ89WYbozQsBOqEn/65dG5Pb7PulzgANyvLytvm6GGY3C/odwYou3MimWJqfdyPJIcpCbiW0F0a+GjaAX0veKgs7xB1OKaH3A9C0BNX056qj7F1sJWj5y3U/sje5B6BarDRXHfmRmD+v1qbD/PxAKXYlLyX1i7DZrLTMtKY4aOYZYevNUTZWx8jcbRnjkvXJ5/HJ5ESf/stRRxAUKe7QeYa8RD9vADwF378vtsUteQ6Cn9NQE9hDq6SKFyH/hxCTISer7cRH/fGZBlnYs5B5es2KLHK8yTSmAPyfpeZlLjKJYMTieHF64FU", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "15 Apr 2026 10:57:07.9619 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 8fa78ae7-ee30-4cc5-0567-08de9addbcea", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CY4PEPF0000EE3E.namprd03.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "IA1PR12MB6530", "X-Spam_score_int": "-25", "X-Spam_score": "-2.6", "X-Spam_bar": "--", "X-Spam_report": "(-2.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.54,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "From: Nicolin Chen <nicolinc@nvidia.com>\n\nAdd a helper to allocate an iommufd backed HW queue for a vIOMMU.\n\nWhile at it, define a struct IOMMUFDHWqueue for use by vendor\nimplementations.\n\nSigned-off-by: Nicolin Chen <nicolinc@nvidia.com>\nReviewed-by: Eric Auger <eric.auger@redhat.com>\nSigned-off-by: Shameer Kolothum <skolothumtho@nvidia.com>\n---\n include/system/iommufd.h | 11 +++++++++++\n backends/iommufd.c | 31 +++++++++++++++++++++++++++++++\n backends/trace-events | 1 +\n 3 files changed, 43 insertions(+)", "diff": "diff --git a/include/system/iommufd.h b/include/system/iommufd.h\nindex e027800c91..8009ce3d31 100644\n--- a/include/system/iommufd.h\n+++ b/include/system/iommufd.h\n@@ -65,6 +65,12 @@ typedef struct IOMMUFDVeventq {\n bool event_start; /* True after first valid event; cleared on overflow */\n } IOMMUFDVeventq;\n \n+/* HW queue object for a vIOMMU-specific HW-accelerated queue */\n+typedef struct IOMMUFDHWqueue {\n+ IOMMUFDViommu *viommu;\n+ uint32_t hw_queue_id;\n+} IOMMUFDHWqueue;\n+\n bool iommufd_backend_connect(IOMMUFDBackend *be, Error **errp);\n void iommufd_backend_disconnect(IOMMUFDBackend *be);\n \n@@ -101,6 +107,11 @@ bool iommufd_backend_alloc_veventq(IOMMUFDBackend *be, uint32_t viommu_id,\n uint32_t *out_veventq_id,\n uint32_t *out_veventq_fd, Error **errp);\n \n+bool iommufd_backend_alloc_hw_queue(IOMMUFDBackend *be, uint32_t viommu_id,\n+ uint32_t queue_type, uint32_t index,\n+ uint64_t addr, uint64_t length,\n+ uint32_t *out_hw_queue_id, Error **errp);\n+\n bool iommufd_backend_set_dirty_tracking(IOMMUFDBackend *be, uint32_t hwpt_id,\n bool start, Error **errp);\n bool iommufd_backend_get_dirty_bitmap(IOMMUFDBackend *be, uint32_t hwpt_id,\ndiff --git a/backends/iommufd.c b/backends/iommufd.c\nindex 9b07ac19c2..3be7b07eec 100644\n--- a/backends/iommufd.c\n+++ b/backends/iommufd.c\n@@ -556,6 +556,37 @@ bool iommufd_backend_alloc_veventq(IOMMUFDBackend *be, uint32_t viommu_id,\n return true;\n }\n \n+bool iommufd_backend_alloc_hw_queue(IOMMUFDBackend *be, uint32_t viommu_id,\n+ uint32_t queue_type, uint32_t index,\n+ uint64_t addr, uint64_t length,\n+ uint32_t *out_hw_queue_id, Error **errp)\n+{\n+ int ret;\n+ struct iommu_hw_queue_alloc alloc_hw_queue = {\n+ .size = sizeof(alloc_hw_queue),\n+ .flags = 0,\n+ .viommu_id = viommu_id,\n+ .type = queue_type,\n+ .index = index,\n+ .nesting_parent_iova = addr,\n+ .length = length,\n+ };\n+\n+ ret = ioctl(be->fd, IOMMU_HW_QUEUE_ALLOC, &alloc_hw_queue);\n+\n+ trace_iommufd_backend_alloc_hw_queue(be->fd, viommu_id, queue_type,\n+ index, addr, length,\n+ alloc_hw_queue.out_hw_queue_id, ret);\n+ if (ret) {\n+ error_setg_errno(errp, errno, \"IOMMU_HW_QUEUE_ALLOC failed\");\n+ return false;\n+ }\n+\n+ g_assert(out_hw_queue_id);\n+ *out_hw_queue_id = alloc_hw_queue.out_hw_queue_id;\n+ return true;\n+}\n+\n bool host_iommu_device_iommufd_attach_hwpt(HostIOMMUDeviceIOMMUFD *idev,\n uint32_t hwpt_id, Error **errp)\n {\ndiff --git a/backends/trace-events b/backends/trace-events\nindex 3ba0c3503c..c5c1d95aad 100644\n--- a/backends/trace-events\n+++ b/backends/trace-events\n@@ -24,6 +24,7 @@ iommufd_backend_invalidate_cache(int iommufd, uint32_t id, uint32_t data_type, u\n iommufd_backend_alloc_viommu(int iommufd, uint32_t dev_id, uint32_t type, uint32_t hwpt_id, uint64_t data_ptr, uint32_t data_len, uint32_t viommu_id, int ret) \" iommufd=%d type=%u dev_id=%u hwpt_id=%u data_ptr=0x%\"PRIx64\" data_len=0x%x viommu_id=%u (%d)\"\n iommufd_backend_alloc_vdev(int iommufd, uint32_t dev_id, uint32_t viommu_id, uint64_t virt_id, uint32_t vdev_id, int ret) \" iommufd=%d dev_id=%u viommu_id=%u virt_id=0x%\"PRIx64\" vdev_id=%u (%d)\"\n iommufd_viommu_alloc_eventq(int iommufd, uint32_t viommu_id, uint32_t type, uint32_t veventq_id, uint32_t veventq_fd, int ret) \" iommufd=%d viommu_id=%u type=%u veventq_id=%u veventq_fd=%u (%d)\"\n+iommufd_backend_alloc_hw_queue(int iommufd, uint32_t viommu_id, uint32_t queue_type, uint32_t index, uint64_t addr, uint64_t size, uint32_t queue_id, int ret) \" iommufd=%d viommu_id=%u queue_type=%u index=%u addr=0x%\"PRIx64\" size=0x%\"PRIx64\" queue_id=%u (%d)\"\n \n # igvm-cfg.c\n igvm_reset_enter(int type) \"type=%u\"\n", "prefixes": [ "v4", "03/31" ] }