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GET /api/1.2/patches/2223464/?format=api
{ "id": 2223464, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2223464/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260415105552.622421-31-skolothumtho@nvidia.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.2/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260415105552.622421-31-skolothumtho@nvidia.com>", "list_archive_url": null, "date": "2026-04-15T10:55:51", "name": "[v4,30/31] hw/arm/smmuv3-accel: Enforce viommu association when CMDQV is active", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "0f8a097b417b9b869d3ed9e5d5f87f38516dbdc6", "submitter": { "id": 91580, "url": "http://patchwork.ozlabs.org/api/1.2/people/91580/?format=api", "name": "Shameer Kolothum Thodi", "email": "skolothumtho@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260415105552.622421-31-skolothumtho@nvidia.com/mbox/", "series": [ { "id": 499965, "url": "http://patchwork.ozlabs.org/api/1.2/series/499965/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=499965", "date": "2026-04-15T10:55:21", "name": "hw/arm/virt: Introduce Tegra241 CMDQV support for accelerated SMMUv3", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/499965/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2223464/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2223464/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=VpyK852k;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail.nvidia.com; pr=C", "permerror client-ip=2a01:111:f403:c112::7;\n envelope-from=skolothumtho@nvidia.com;\n helo=CY3PR05CU001.outbound.protection.outlook.com" ], "From": "Shameer Kolothum <skolothumtho@nvidia.com>", "To": "<qemu-arm@nongnu.org>, <qemu-devel@nongnu.org>", "CC": "<eric.auger@redhat.com>, <peter.maydell@linaro.org>, <clg@redhat.com>,\n <alex@shazbot.org>, <nicolinc@nvidia.com>, <nathanc@nvidia.com>,\n <mochs@nvidia.com>, <jan@nvidia.com>, <jgg@nvidia.com>,\n <jonathan.cameron@huawei.com>, <zhenzhong.duan@intel.com>,\n <kjaju@nvidia.com>, <phrdina@redhat.com>, <skolothumtho@nvidia.com>", "Subject": "[PATCH v4 30/31] hw/arm/smmuv3-accel: Enforce viommu association when\n CMDQV is active", "Date": "Wed, 15 Apr 2026 11:55:51 +0100", "Message-ID": "<20260415105552.622421-31-skolothumtho@nvidia.com>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260415105552.622421-1-skolothumtho@nvidia.com>", "References": "<20260415105552.622421-1-skolothumtho@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.230.37]", "X-ClientProxiedBy": "rnnvmail203.nvidia.com (10.129.68.9) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "CY4PEPF0000EE3D:EE_|LV3PR12MB9266:EE_", "X-MS-Office365-Filtering-Correlation-Id": "dad373cd-1b35-474d-d566-08de9addf704", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;\n ARA:13230040|36860700016|82310400026|376014|1800799024|56012099003|18002099003|22082099003;", "X-Microsoft-Antispam-Message-Info": "\n fCneFk8T7P0f3Jr6YUpC+p2k8REBIs5xeLSqyTrUou7kaVjTYHcwMi8isU9YtAuk1H91MMHQixj6imQC3TNoWHac5L0pROvHszoHC7GExPhfqD8REp2PDN43Z9yh9neE6POG2pIDU84RrT4mojPgGSgBDNljIA1hbtcn7wHz5C2pOVwml0cEQkvBkUPILgcVwS8kQratSYNRJODtgHRwtzve/+T9A9ik8X+WRI1dlRqHbsd42UczfxV5Irb1FCsiqs3PaJNG2dW0bTZd5vjQLAq4CUh0UySpVdcE53wTB8gi9D7bkc8ebefklsm1vsEG/K/8BlRWcqIoY3+k4Qo/4E7l5i06nOyNwainP8z1RCLH9nv6e2/t8zAvZzAnERH7XXVq2NWkdAceLMBncs3yJAVSoHqZDjL9fVK0DY1zPhx3cy5iJ0fAktFibFdcW5vK9uTfS5R+mN6CoKFMVSlbn+o9/NQz6RS3pQyiFuFW98U4y2L0Ha9FuGoeFHUNfKI7PXKXqxTT0zURa204oECo3o+x5tjr2YXIKAjoZWb0bFdFtLe9Lriq4WXRX82329Cu7MbcudkflTUxQG9S8ui3+Y8m+kVJJQFWWmLCD3Rz9ivs72/2W0YmM4wQtc9MaiVO5veWJ7DH1vE/PfJ1y8vn2LwmcCDVSAdCZsD56iwRdZoNrISuM9dVlg1gaO6GxBzMjHJQXG5tv7x1Jn9CYxARpVxTsUj2NuB2EMHDPZzRXjQqidSecjzztXwa/rjK+NtvSH5ScHwTOkePYoU8yF8W5A==", "X-Forefront-Antispam-Report": "CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE;\n SFS:(13230040)(36860700016)(82310400026)(376014)(1800799024)(56012099003)(18002099003)(22082099003);\n DIR:OUT; SFP:1101;", "X-MS-Exchange-AntiSpam-MessageData-ChunkCount": "1", "X-MS-Exchange-AntiSpam-MessageData-0": "\n PQ38sbHAyQ+irDqTaxLMCsEwYetuARZMdKHTMPYspQDtwFSBYfcXEgRkRXHRcLdAHp7Ms6sfLzi0GspvHGhDuQmdzJyudxvTqF75/1Zq43JwynJbHpNmHY9wgXSZ7EGpFZ0pNr+nSw9JIY9eMdliDgoZJ5SVB/rX48lZMhUPTIJU1JWj9iRoIgs9SM1CStVBJZq316y7a0OZvQ4FWsiP8t1iEa/AA4/a/l3D9Sz5VfWhDgc2ouzeqsorHq//D2oZtjVCd4iNbu6VOd/6j1hv3nbet08TvF/ZvuFRctsxeZpyYgAhiUcY6AEmsUANsnPPitbSs6Tjm9j8R7TrJ4AQbNwhH9c+dGHcFk7keh8XM2q2XYZNhbijsjWmGBNBkvZKIZnxl12Po0mnfInyLab7aef0rrqxSHATp+oqB6CHKSsAIy6cbGwbTZKj1GfzkYEQ", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "15 Apr 2026 10:58:45.4577 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n dad373cd-1b35-474d-d566-08de9addf704", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CY4PEPF0000EE3D.namprd03.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "LV3PR12MB9266", "X-Spam_score_int": "-15", "X-Spam_score": "-1.6", "X-Spam_bar": "-", "X-Spam_report": "(-1.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.54,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n FORGED_SPF_HELO=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001,\n SPF_NONE=0.001 autolearn=no autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "When CMDQV is active, the first cold-plugged VFIO device establishes the\nviommu to host SMMUv3 association. Block its hot-unplug to preserve this\nassociation and the guest's boot time CMDQV configuration.\n\nAlso abort at machine_done if cmdqv=on is requested but no cold-plugged\nVFIO device was present to initialize it.\n\nSigned-off-by: Shameer Kolothum <skolothumtho@nvidia.com>\n---\n hw/arm/smmuv3-accel.h | 1 +\n hw/arm/smmuv3-accel.c | 12 ++++++++++++\n hw/arm/smmuv3.c | 6 ++++++\n 3 files changed, 19 insertions(+)", "diff": "diff --git a/hw/arm/smmuv3-accel.h b/hw/arm/smmuv3-accel.h\nindex 3ed94ed05c..c4441d5b3f 100644\n--- a/hw/arm/smmuv3-accel.h\n+++ b/hw/arm/smmuv3-accel.h\n@@ -65,6 +65,7 @@ typedef struct SMMUv3AccelDevice {\n IOMMUFDVdev *vdev;\n QLIST_ENTRY(SMMUv3AccelDevice) next;\n SMMUv3AccelState *s_accel;\n+ Error *unplug_blocker; /* set when CMDQV is active to block hot-unplug */\n } SMMUv3AccelDevice;\n \n bool smmuv3_accel_init(SMMUv3State *s, Error **errp);\ndiff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c\nindex a58815ded2..f381702a08 100644\n--- a/hw/arm/smmuv3-accel.c\n+++ b/hw/arm/smmuv3-accel.c\n@@ -754,6 +754,18 @@ static bool smmuv3_accel_set_iommu_device(PCIBus *bus, void *opaque, int devfn,\n return false;\n }\n \n+ /*\n+ * CMDQV is active: block hot-unplug of the device that established the\n+ * viommu association. Removing it would cause the vIOMMU to host SMMUv3\n+ * association be changed via device hot-plug.\n+ */\n+ if (s->s_accel->cmdqv_ops) {\n+ PCIDevice *pdev = pci_find_device(bus, pci_bus_num(bus), devfn);\n+ error_setg(&accel_dev->unplug_blocker,\n+ \"CMDQV is active: removing the device that established the \"\n+ \"viommu association would break the guest CMDQV\");\n+ qdev_add_unplug_blocker(DEVICE(pdev), accel_dev->unplug_blocker);\n+ }\n done:\n accel_dev->idev = idev;\n accel_dev->s_accel = s->s_accel;\ndiff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c\nindex 1d6fdd776c..c9ff6298f5 100644\n--- a/hw/arm/smmuv3.c\n+++ b/hw/arm/smmuv3.c\n@@ -2020,6 +2020,12 @@ static void smmuv3_machine_done(Notifier *notifier, void *data)\n \"at least one cold-plugged VFIO device\");\n exit(1);\n }\n+\n+ if (s->cmdqv == ON_OFF_AUTO_ON && !accel->cmdqv) {\n+ error_report(\"arm-smmuv3 cmdqv=on requires at least one cold-plugged \"\n+ \"VFIO device\");\n+ exit(1);\n+ }\n }\n \n static void smmu_realize(DeviceState *d, Error **errp)\n", "prefixes": [ "v4", "30/31" ] }