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GET /api/1.2/patches/2223463/?format=api
{ "id": 2223463, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2223463/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260415105552.622421-29-skolothumtho@nvidia.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.2/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260415105552.622421-29-skolothumtho@nvidia.com>", "list_archive_url": null, "date": "2026-04-15T10:55:49", "name": "[v4,28/31] hw/arm/smmuv3-accel: Introduce helper to query CMDQV type", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "aa03aad757e47eb73b74216bd73ff97fbf8e4878", "submitter": { "id": 91580, "url": "http://patchwork.ozlabs.org/api/1.2/people/91580/?format=api", "name": "Shameer Kolothum Thodi", "email": "skolothumtho@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260415105552.622421-29-skolothumtho@nvidia.com/mbox/", "series": [ { "id": 499965, "url": "http://patchwork.ozlabs.org/api/1.2/series/499965/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=499965", "date": "2026-04-15T10:55:21", "name": "hw/arm/virt: Introduce Tegra241 CMDQV support for accelerated SMMUv3", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/499965/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2223463/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2223463/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=aC9OSMGz;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail.nvidia.com; pr=C", "permerror client-ip=2a01:111:f403:c105::5;\n envelope-from=skolothumtho@nvidia.com;\n helo=CH5PR02CU005.outbound.protection.outlook.com" ], "From": "Shameer Kolothum <skolothumtho@nvidia.com>", "To": "<qemu-arm@nongnu.org>, <qemu-devel@nongnu.org>", "CC": "<eric.auger@redhat.com>, <peter.maydell@linaro.org>, <clg@redhat.com>,\n <alex@shazbot.org>, <nicolinc@nvidia.com>, <nathanc@nvidia.com>,\n <mochs@nvidia.com>, <jan@nvidia.com>, <jgg@nvidia.com>,\n <jonathan.cameron@huawei.com>, <zhenzhong.duan@intel.com>,\n <kjaju@nvidia.com>, <phrdina@redhat.com>, <skolothumtho@nvidia.com>", "Subject": "[PATCH v4 28/31] hw/arm/smmuv3-accel: Introduce helper to query CMDQV\n type", "Date": "Wed, 15 Apr 2026 11:55:49 +0100", "Message-ID": "<20260415105552.622421-29-skolothumtho@nvidia.com>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260415105552.622421-1-skolothumtho@nvidia.com>", "References": "<20260415105552.622421-1-skolothumtho@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.230.37]", "X-ClientProxiedBy": "rnnvmail203.nvidia.com (10.129.68.9) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "BL02EPF00021F69:EE_|MN0PR12MB5908:EE_", "X-MS-Office365-Filtering-Correlation-Id": "012b1764-ed97-4cbd-c35a-08de9addf0de", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;\n ARA:13230040|36860700016|376014|82310400026|1800799024|18002099003|56012099003|22082099003;", "X-Microsoft-Antispam-Message-Info": "\n HtmOg1eAk37/kfsnoD2lEHZ4+BXAIExJRIwLYh8+p8/xwPzRhtYc1dMYLGNTjEqBzm/b3eN36z3S4R5QFtW8YBi+A7m7IHDNNwJqPMGW3Cae8B8+6fh+CDdKvvoOtbnTI4iAw9lpldOHH7RdGexukEP0bkQrULTiNySyFrpW9h2g6OPhgWmzsmqqsNmDzEKPBpmDC8LAeUAw/h0U3xx3nEEDhHTzmglNJX2yuy8zzQgnaX5AgoGSLIKx8/LWoAEzr3eZ3cbbxY4pTruB9IxLHJ/TUDyDkdL+MqPMG9ko11pBaLZpgYFJQOE3435Z1bJU4/+LTAt+UBjWLhR1/tTJ/19361akiAAI+doJRYIjaYoy6OkUT+SD/rmbTtiMMliGzT1GprGnrsT0hZA2l8UwCcEQD/o55kyIsWXdGlX8yTEdemBEEGNg2Z1uliUIqUZkMFwNgSAq2AJpVG0cCH3vyd+MixxEQ5BpUMNyvFiadoHkpsntFjTZQaXEbBmCzxoTYzIJNxtSwthquhvHLNQGMy01whd+wW2gtxYhn/Cwwh4sYIirWmzpba5pj8bKhfd8zrMLcPLSjy7o4C83cuAi9XBkxvFbEvAA2Wtv6TcioomwdjoIgbKQF7QsX9RFXkKiuDyB5Q9Bz8KLnb6fIbYyglGTnukbTJ72Lm8kcs4A5eT9x7fGpbjq4sDKKPMxca70KBSqqpWFSkKLm/3VUPOSvykITjQB4I8+rFXWtnXpSFrR3B5IG9o6SF+bHKD5D+iKX7ocfvKyfu/+1C1QvOCCSg==", "X-Forefront-Antispam-Report": "CIP:216.228.117.161; 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Ip=[216.228.117.161];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BL02EPF00021F69.namprd02.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "MN0PR12MB5908", "X-Spam_score_int": "-15", "X-Spam_score": "-1.6", "X-Spam_bar": "-", "X-Spam_report": "(-1.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.54,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n FORGED_SPF_HELO=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001,\n SPF_NONE=0.001 autolearn=no autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Introduce a SMMUv3AccelCmdqvType enum and a helper to query the\nCMDQV implementation type associated with an accelerated SMMUv3\ninstance.\n\nA subsequent patch will use this helper when generating the\nTegra241 CMDQV DSDT.\n\nReviewed-by: Eric Auger <eric.auger@redhat.com>\nSigned-off-by: Shameer Kolothum <skolothumtho@nvidia.com>\n---\n hw/arm/smmuv3-accel.h | 7 +++++++\n hw/arm/smmuv3-accel-stubs.c | 5 +++++\n hw/arm/smmuv3-accel.c | 12 ++++++++++++\n hw/arm/tegra241-cmdqv.c | 6 ++++++\n 4 files changed, 30 insertions(+)", "diff": "diff --git a/hw/arm/smmuv3-accel.h b/hw/arm/smmuv3-accel.h\nindex 448f47c0ca..3ed94ed05c 100644\n--- a/hw/arm/smmuv3-accel.h\n+++ b/hw/arm/smmuv3-accel.h\n@@ -16,6 +16,11 @@\n #include <linux/iommufd.h>\n #endif\n \n+typedef enum SMMUv3AccelCmdqvType {\n+ SMMUV3_CMDQV_NONE = 0,\n+ SMMUV3_CMDQV_TEGRA241,\n+} SMMUv3AccelCmdqvType;\n+\n /*\n * CMDQ-Virtualization (CMDQV) hardware support, extends the SMMUv3 to\n * support multiple VCMDQs with virtualization capabilities.\n@@ -29,6 +34,7 @@ typedef struct SMMUv3AccelCmdqvOps {\n uint32_t *out_viommu_id,\n Error **errp);\n void (*free_viommu)(SMMUv3State *s);\n+ SMMUv3AccelCmdqvType (*get_type)(void);\n void (*reset)(SMMUv3State *s);\n } SMMUv3AccelCmdqvOps;\n \n@@ -74,5 +80,6 @@ bool smmuv3_accel_alloc_veventq(SMMUv3State *s, Error **errp);\n bool smmuv3_accel_event_read_validate(IOMMUFDVeventq *veventq, uint32_t type,\n void *buf, size_t size, Error **errp);\n void smmuv3_accel_reset(SMMUv3State *s);\n+SMMUv3AccelCmdqvType smmuv3_accel_cmdqv_type(Object *obj);\n \n #endif /* HW_ARM_SMMUV3_ACCEL_H */\ndiff --git a/hw/arm/smmuv3-accel-stubs.c b/hw/arm/smmuv3-accel-stubs.c\nindex e8f08dc833..08de01d909 100644\n--- a/hw/arm/smmuv3-accel-stubs.c\n+++ b/hw/arm/smmuv3-accel-stubs.c\n@@ -55,3 +55,8 @@ bool smmuv3_accel_event_read_validate(IOMMUFDVeventq *veventq, uint32_t type,\n void smmuv3_accel_reset(SMMUv3State *s)\n {\n }\n+\n+SMMUv3AccelCmdqvType smmuv3_accel_cmdqv_type(Object *obj)\n+{\n+ return SMMUV3_CMDQV_NONE;\n+}\ndiff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c\nindex 230f608f03..a58815ded2 100644\n--- a/hw/arm/smmuv3-accel.c\n+++ b/hw/arm/smmuv3-accel.c\n@@ -1049,6 +1049,18 @@ static void smmuv3_accel_as_init(SMMUv3State *s)\n address_space_init(shared_as_sysmem, &root, \"smmuv3-accel-as-sysmem\");\n }\n \n+SMMUv3AccelCmdqvType smmuv3_accel_cmdqv_type(Object *obj)\n+{\n+ SMMUv3State *s = ARM_SMMUV3(obj);\n+ SMMUv3AccelState *accel = s->s_accel;\n+\n+ if (!accel || !accel->cmdqv_ops || !accel->cmdqv_ops->get_type) {\n+ return SMMUV3_CMDQV_NONE;\n+ }\n+\n+ return accel->cmdqv_ops->get_type();\n+}\n+\n bool smmuv3_accel_init(SMMUv3State *s, Error **errp)\n {\n SMMUState *bs = ARM_SMMU(s);\ndiff --git a/hw/arm/tegra241-cmdqv.c b/hw/arm/tegra241-cmdqv.c\nindex 2870886783..71f89abcb4 100644\n--- a/hw/arm/tegra241-cmdqv.c\n+++ b/hw/arm/tegra241-cmdqv.c\n@@ -762,6 +762,11 @@ static bool tegra241_cmdqv_init(SMMUv3State *s, Error **errp)\n return true;\n }\n \n+static SMMUv3AccelCmdqvType tegra241_cmdqv_get_type(void)\n+{\n+ return SMMUV3_CMDQV_TEGRA241;\n+}\n+\n static bool tegra241_cmdqv_probe(SMMUv3State *s, HostIOMMUDeviceIOMMUFD *idev,\n Error **errp)\n {\n@@ -802,6 +807,7 @@ static const SMMUv3AccelCmdqvOps tegra241_cmdqv_ops = {\n .init = tegra241_cmdqv_init,\n .alloc_viommu = tegra241_cmdqv_alloc_viommu,\n .free_viommu = tegra241_cmdqv_free_viommu,\n+ .get_type = tegra241_cmdqv_get_type,\n .reset = tegra241_cmdqv_reset,\n };\n \n", "prefixes": [ "v4", "28/31" ] }