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GET /api/1.2/patches/2223462/?format=api
{ "id": 2223462, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2223462/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260415105552.622421-14-skolothumtho@nvidia.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.2/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260415105552.622421-14-skolothumtho@nvidia.com>", "list_archive_url": null, "date": "2026-04-15T10:55:34", "name": "[v4,13/31] hw/arm/tegra241-cmdqv: Implement CMDQV vIOMMU alloc/free", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "ad43cef100215e6e72f23989a97782ec0ff4b4b4", "submitter": { "id": 91580, "url": "http://patchwork.ozlabs.org/api/1.2/people/91580/?format=api", "name": "Shameer Kolothum Thodi", "email": "skolothumtho@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260415105552.622421-14-skolothumtho@nvidia.com/mbox/", "series": [ { "id": 499965, "url": "http://patchwork.ozlabs.org/api/1.2/series/499965/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=499965", "date": "2026-04-15T10:55:21", "name": "hw/arm/virt: Introduce Tegra241 CMDQV support for accelerated SMMUv3", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/499965/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2223462/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2223462/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=shbxpAZ/;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail.nvidia.com; pr=C", "permerror client-ip=2a01:111:f403:c105::5;\n envelope-from=skolothumtho@nvidia.com;\n helo=CH5PR02CU005.outbound.protection.outlook.com" ], "From": "Shameer Kolothum <skolothumtho@nvidia.com>", "To": "<qemu-arm@nongnu.org>, <qemu-devel@nongnu.org>", "CC": "<eric.auger@redhat.com>, <peter.maydell@linaro.org>, <clg@redhat.com>,\n <alex@shazbot.org>, <nicolinc@nvidia.com>, <nathanc@nvidia.com>,\n <mochs@nvidia.com>, <jan@nvidia.com>, <jgg@nvidia.com>,\n <jonathan.cameron@huawei.com>, <zhenzhong.duan@intel.com>,\n <kjaju@nvidia.com>, <phrdina@redhat.com>, <skolothumtho@nvidia.com>", "Subject": "[PATCH v4 13/31] hw/arm/tegra241-cmdqv: Implement CMDQV vIOMMU\n alloc/free", "Date": "Wed, 15 Apr 2026 11:55:34 +0100", "Message-ID": "<20260415105552.622421-14-skolothumtho@nvidia.com>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260415105552.622421-1-skolothumtho@nvidia.com>", "References": "<20260415105552.622421-1-skolothumtho@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.230.37]", "X-ClientProxiedBy": "rnnvmail203.nvidia.com (10.129.68.9) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "CY4PEPF0000EE3E:EE_|MN6PR12MB8567:EE_", "X-MS-Office365-Filtering-Correlation-Id": "5669c509-ab61-47e3-9c6e-08de9addcdfe", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;\n ARA:13230040|1800799024|36860700016|376014|82310400026|56012099003|18002099003|22082099003;", "X-Microsoft-Antispam-Message-Info": "\n hsBcelog3D3P2Q4UH8bZOtGqRJU4M9OSlMarZzJGn8BCXkkhdlPFXO+LB5rhCWEibWX04uzflXpsm3zBjYMDE9JllMayNJ52cE8tvabLBw67D9MdWn0n1uv7Mf0NMBmb3wxncGsx0sAFp9J+LYvK6xeebrPjvZOP6fkzS3rRo+bpFt6k2TMPXBTyUX1/XCtKvgrUgBsEg4OcFIK6hpBLUikJIzI7c0XbN1J3tjkX/MuNZAcdxFQv7YmVpqp1NiGuLFLa4v/tFWZxwwU+0kMpz4fw6hYioZiKsFoG0e4Wf09gGvl44fJkdViYoalE9A1P0prm1CTM3pv/JSsrB0cWGGPySHEoFGnZFaLalNhWl26z8RMn0kxPwChauPQKKjQcdhNHxOGaV4KvxAhmLYYS/DNS08CGC7yeFRu7cTrzVmslNmMXbfN7+18I+xdcIDUKDypmb8lx+o50jYejSr31tp0O2BintxpizSOx79tCyNQ9lsKkDaQ6stopO125qwnzwhatF10sLEtuDoltxxEB6cmz5DgKtpQOvgvb6+za7tbkUok2lbFjzdymEndnzMMTQZzBZRA3DSvM1TSOK+heXr6UbrYKEJ4NGRWZfFUW2xO3sOV7rtanlBSTCBrX3/3Raj/Tph5dB4r+oo5XbF98cK2AsHba6kW5U9JjdU0a3JGuIwJMhs2ny1slzOCwclCdmfQB8dNqlyO4fauJPpzqSjUGOUZHtPeoyZIn2CYjq/ZtnRuuspOIm1uf7U32UrbbI1Vga2zfXK4JE/5ZJ1mW5A==", "X-Forefront-Antispam-Report": "CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE;\n SFS:(13230040)(1800799024)(36860700016)(376014)(82310400026)(56012099003)(18002099003)(22082099003);\n DIR:OUT; SFP:1101;", "X-MS-Exchange-AntiSpam-MessageData-ChunkCount": "1", "X-MS-Exchange-AntiSpam-MessageData-0": "\n ejYrnnYN5S1GKONujhmHPsWUg1RIA8u2Vyxlw8hPXeR04Wn2HYgYRzIu++yB8Vh/eCqby8sZwhuDa3QLZDDiiv3J6EL+EY5RcAVgzUOr1ibYsNLp6TsCPxDEsL5hISO5vsFNfiwSlLaWfP2lvFD74oO+9NIFc6TzRQa1y0dtcAWV5w/E+1N6yZi8/kg7GkrJN5xOl3xuY33ug/Iydi00xGqMI6kVnwUE+59OK9wN7IQDLf31rBUr3AnHLaRdpA692ctxhHxlbkpc4ohjuZDXDDrsyh/2by7lxjEZuGXOrzxmIm8Z8iXPELXjLirbFR20Y79jyHW56X1YMfdvgv6r3QK26I2gsyqpNC5YYcLSuif1OaoR970sZPBXvsYDEaTedf+/eTONTQCpsYBS1R5vNZKLHauj1tuF3we7UJEoIlvjvhRkZjUyVZb7RgwrC7FT", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "15 Apr 2026 10:57:36.6212 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 5669c509-ab61-47e3-9c6e-08de9addcdfe", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CY4PEPF0000EE3E.namprd03.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "MN6PR12MB8567", "X-Spam_score_int": "-15", "X-Spam_score": "-1.6", "X-Spam_bar": "-", "X-Spam_report": "(-1.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.54,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n FORGED_SPF_HELO=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001,\n SPF_NONE=0.001 autolearn=no autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "From: Nicolin Chen <nicolinc@nvidia.com>\n\nReplace the stub implementation with real vIOMMU allocation for\nTegra241 CMDQV.\n\nAllocate a matching vEVENTQ together with the vIOMMU, since it is\nspecific to the Tegra241 CMDQV vIOMMU and used to receive CMDQV\nevents.\n\nFree both objects on teardown.\n\nSigned-off-by: Nicolin Chen <nicolinc@nvidia.com>\nCo-developed-by: Shameer Kolothum <skolothumtho@nvidia.com>\nSigned-off-by: Shameer Kolothum <skolothumtho@nvidia.com>\n---\n hw/arm/tegra241-cmdqv.h | 1 +\n hw/arm/tegra241-cmdqv.c | 46 ++++++++++++++++++++++++++++++++++++++++-\n 2 files changed, 46 insertions(+), 1 deletion(-)", "diff": "diff --git a/hw/arm/tegra241-cmdqv.h b/hw/arm/tegra241-cmdqv.h\nindex 2a34a4b6b4..fa0aa3ab04 100644\n--- a/hw/arm/tegra241-cmdqv.h\n+++ b/hw/arm/tegra241-cmdqv.h\n@@ -30,6 +30,7 @@ typedef struct Tegra241CMDQV {\n SMMUv3AccelState *s_accel;\n MemoryRegion mmio_cmdqv;\n qemu_irq irq;\n+ IOMMUFDVeventq *veventq;\n } Tegra241CMDQV;\n \n const SMMUv3AccelCmdqvOps *tegra241_cmdqv_get_ops(void);\ndiff --git a/hw/arm/tegra241-cmdqv.c b/hw/arm/tegra241-cmdqv.c\nindex ccd3c6d275..2f1084b55f 100644\n--- a/hw/arm/tegra241-cmdqv.c\n+++ b/hw/arm/tegra241-cmdqv.c\n@@ -25,13 +25,57 @@ static void tegra241_cmdqv_write(void *opaque, hwaddr offset, uint64_t value,\n \n static void tegra241_cmdqv_free_viommu(SMMUv3State *s)\n {\n+ SMMUv3AccelState *accel = s->s_accel;\n+ IOMMUFDViommu *viommu = accel->viommu;\n+ Tegra241CMDQV *cmdqv = accel->cmdqv;\n+ IOMMUFDVeventq *veventq = cmdqv->veventq;\n+\n+ if (!viommu) {\n+ return;\n+ }\n+ if (veventq) {\n+ close(veventq->veventq_fd);\n+ iommufd_backend_free_id(viommu->iommufd, veventq->veventq_id);\n+ g_free(veventq);\n+ cmdqv->veventq = NULL;\n+ }\n+ iommufd_backend_free_id(viommu->iommufd, viommu->viommu_id);\n }\n \n static bool\n tegra241_cmdqv_alloc_viommu(SMMUv3State *s, HostIOMMUDeviceIOMMUFD *idev,\n uint32_t *out_viommu_id, Error **errp)\n {\n- error_setg(errp, \"NVIDIA Tegra241 CMDQV is unsupported\");\n+ Tegra241CMDQV *cmdqv = s->s_accel->cmdqv;\n+ uint32_t viommu_id, veventq_id, veventq_fd;\n+ IOMMUFDVeventq *veventq;\n+\n+ if (!iommufd_backend_alloc_viommu(idev->iommufd, idev->devid,\n+ IOMMU_VIOMMU_TYPE_TEGRA241_CMDQV,\n+ idev->hwpt_id, &cmdqv->cmdqv_data,\n+ sizeof(cmdqv->cmdqv_data), &viommu_id,\n+ errp)) {\n+ return false;\n+ }\n+\n+ if (!iommufd_backend_alloc_veventq(idev->iommufd, viommu_id,\n+ IOMMU_VEVENTQ_TYPE_TEGRA241_CMDQV,\n+ 1 << 16, &veventq_id, &veventq_fd,\n+ errp)) {\n+ error_append_hint(errp, \"Tegra241 CMDQV: failed to alloc veventq\");\n+ goto free_viommu;\n+ }\n+\n+ veventq = g_new(IOMMUFDVeventq, 1);\n+ veventq->veventq_id = veventq_id;\n+ veventq->veventq_fd = veventq_fd;\n+ cmdqv->veventq = veventq;\n+\n+ *out_viommu_id = viommu_id;\n+ return true;\n+\n+free_viommu:\n+ iommufd_backend_free_id(idev->iommufd, viommu_id);\n return false;\n }\n \n", "prefixes": [ "v4", "13/31" ] }