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GET /api/1.2/patches/2223459/?format=api
{ "id": 2223459, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2223459/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260415105552.622421-30-skolothumtho@nvidia.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.2/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260415105552.622421-30-skolothumtho@nvidia.com>", "list_archive_url": null, "date": "2026-04-15T10:55:50", "name": "[v4,29/31] hw/arm/virt-acpi: Advertise Tegra241 CMDQV nodes in DSDT", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "7ec40915f49cf3394912076aad2161b3305f3497", "submitter": { "id": 91580, "url": "http://patchwork.ozlabs.org/api/1.2/people/91580/?format=api", "name": "Shameer Kolothum Thodi", "email": "skolothumtho@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260415105552.622421-30-skolothumtho@nvidia.com/mbox/", "series": [ { "id": 499965, "url": "http://patchwork.ozlabs.org/api/1.2/series/499965/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=499965", "date": "2026-04-15T10:55:21", "name": "hw/arm/virt: Introduce Tegra241 CMDQV support for accelerated SMMUv3", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/499965/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2223459/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2223459/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=kB8Ob2Dp;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail.nvidia.com; pr=C", "permerror client-ip=2a01:111:f403:c105::1;\n envelope-from=skolothumtho@nvidia.com;\n helo=CH1PR05CU001.outbound.protection.outlook.com" ], "From": "Shameer Kolothum <skolothumtho@nvidia.com>", "To": "<qemu-arm@nongnu.org>, <qemu-devel@nongnu.org>", "CC": "<eric.auger@redhat.com>, <peter.maydell@linaro.org>, <clg@redhat.com>,\n <alex@shazbot.org>, <nicolinc@nvidia.com>, <nathanc@nvidia.com>,\n <mochs@nvidia.com>, <jan@nvidia.com>, <jgg@nvidia.com>,\n <jonathan.cameron@huawei.com>, <zhenzhong.duan@intel.com>,\n <kjaju@nvidia.com>, <phrdina@redhat.com>, <skolothumtho@nvidia.com>", "Subject": "[PATCH v4 29/31] hw/arm/virt-acpi: Advertise Tegra241 CMDQV nodes in\n DSDT", "Date": "Wed, 15 Apr 2026 11:55:50 +0100", "Message-ID": "<20260415105552.622421-30-skolothumtho@nvidia.com>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260415105552.622421-1-skolothumtho@nvidia.com>", "References": "<20260415105552.622421-1-skolothumtho@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.230.37]", "X-ClientProxiedBy": "rnnvmail203.nvidia.com (10.129.68.9) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "BL02EPF00021F69:EE_|DSSPR12MB999211:EE_", "X-MS-Office365-Filtering-Correlation-Id": "863a11a1-791c-4408-6a43-08de9addf4db", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;\n ARA:13230040|1800799024|82310400026|376014|36860700016|56012099003|22082099003|18002099003;", "X-Microsoft-Antispam-Message-Info": "\n Faenl6VGC/YQ/M6hqfBRlZ6Whhibh/BKOTiaE0TeS4hVr5aMOYsjBUyos+eQrUdvIITHcc34Tm12j9xztzj+99Zut1gPdpxQ1/AkrFuH8EQXZOXXgf/rBPIy2vTO61rZ5RgJ9HntmoVtYJQuGIEgrtqn6PgVFiUrmpp7s3/uWA5M2uDvgl8Dy0130ZBmlstsBpAkCW9HGsbfy9HqX878TaqNM6ZjSF7XwH0Bpv/bxpNqGekUHYLmuXc+sw/njT3I5MRRdv9oxzwq/Cu2DUYxShHiMTb6jTht3996Q6fND96r9C30TGMIiQPSNx7BLQ9UrMrBoVV3x9ceV1mnxNH0c6frGuqz1tLa9Ie7vkfpsFXnZsaWC3XhCUjUrGFO1G5MbSIp1eonLWSjDzGdLdfIvy7vX81KmC3EpD9HDkJN7DAby9c0u5Dy1a9KHxEztfGwEVwzrYfB+zOmFUYByellSCPJEDtM1zu8UlJY11x0rFWjiLxpHJGNpFSnqexaKhl+ecDDzQmkv5RLp5FWTtyarE2yUOGbdFI3UG4zcDx9nvBf4j8YiTA0/iNOYxpWXQT7pc0gJyLX5srJmAt3Ww98dfNMNAdQMLZWdO9OHQApwDicby56xMqe1AeauM2sO1G35mtedE/6SJ6aO12Dmuv49oxZ8gLOsuHMA6xJ408bpdRmiJysoLSTJM34nsiF0BEWqQFfhzMVJpLDEa8ccmyRh4D0LjvyT3N5ds1nhsUMH1sOP+GAgvU0uDfAJF5wpu+Nxt5jlf5E5qJ/utQJ5jSSqg==", "X-Forefront-Antispam-Report": "CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE;\n SFS:(13230040)(1800799024)(82310400026)(376014)(36860700016)(56012099003)(22082099003)(18002099003);\n DIR:OUT; SFP:1101;", "X-MS-Exchange-AntiSpam-MessageData-ChunkCount": "1", "X-MS-Exchange-AntiSpam-MessageData-0": "\n 7VUpbsw446BKa3rJl0fPqoB/gvK2bBoYqj/m7OJeIZN/bMdhHoFyiePAK9rjwpxcy4vS8yvEAnC8jLOxWsOC2e3sFoKv/qum0FCNOMfPt1T7K/iEL7wzD93narwoB7dnv3TPtHlFShoxLeHOChvvrTeMNsHPslkXyosASr4tJs7d+jSSJgrEpbuTzN50rhJv68ViXUOwa7NhpI2mUO50ect/lZGgptzv3ZzprbzouLvpBejsKgueCVsfMDl24fyjE40CmvYJkkDCwYYZKEIVmD21QPT1v9PmXWvjCRkW/JmrxA8+EzttUqYAiHnqdb7O2unDnibQxQGHYbKps70koWBbpwW1I2gzD0szC8NWMCKot/ANOy0EP4xi4Ta5ybvcyijMpPrU52MQCE8/RHjSWEv3aK31sC2o/x4cD5R5dk742WJKBK/DLKcZ//TjLVEc", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "15 Apr 2026 10:58:41.7856 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 863a11a1-791c-4408-6a43-08de9addf4db", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BL02EPF00021F69.namprd02.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DSSPR12MB999211", "X-Spam_score_int": "-15", "X-Spam_score": "-1.6", "X-Spam_bar": "-", "X-Spam_report": "(-1.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.54,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n FORGED_SPF_HELO=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001,\n SPF_NONE=0.001 autolearn=no autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "From: Nicolin Chen <nicolinc@nvidia.com>\n\nAdd ACPI DSDT support for Tegra241 CMDQV when the SMMUv3 instance is\ncreated with tegra241-cmdqv.\n\nThe SMMUv3 device identifier is used as the ACPI _UID. This matches\nthe Identifier field of the corresponding SMMUv3 IORT node, allowing\nthe CMDQV DSDT device to be correctly associated with its SMMU.\n\nSigned-off-by: Nicolin Chen <nicolinc@nvidia.com>\nCo-developed-by: Shameer Kolothum <skolothumtho@nvidia.com>\nSigned-off-by: Shameer Kolothum <skolothumtho@nvidia.com>\n---\n hw/arm/virt-acpi-build.c | 52 ++++++++++++++++++++++++++++++++++++++++\n hw/arm/trace-events | 1 +\n 2 files changed, 53 insertions(+)", "diff": "diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c\nindex 65ccc96349..fbc793d06e 100644\n--- a/hw/arm/virt-acpi-build.c\n+++ b/hw/arm/virt-acpi-build.c\n@@ -65,6 +65,9 @@\n #include \"target/arm/cpu.h\"\n #include \"target/arm/multiprocessing.h\"\n \n+#include \"smmuv3-accel.h\"\n+#include \"tegra241-cmdqv.h\"\n+\n #define ARM_SPI_BASE 32\n \n #define ACPI_BUILD_TABLE_SIZE 0x20000\n@@ -1114,6 +1117,51 @@ static void build_fadt_rev6(GArray *table_data, BIOSLinker *linker,\n build_fadt(table_data, linker, &fadt, vms->oem_id, vms->oem_table_id);\n }\n \n+static void acpi_dsdt_add_tegra241_cmdqv(Aml *scope, VirtMachineState *vms)\n+{\n+ for (int i = 0; i < vms->smmuv3_devices->len; i++) {\n+ Object *obj = OBJECT(g_ptr_array_index(vms->smmuv3_devices, i));\n+ PlatformBusDevice *pbus;\n+ Aml *dev, *crs, *addr;\n+ SysBusDevice *sbdev;\n+ hwaddr base;\n+ uint32_t id;\n+ int irq;\n+\n+ if (smmuv3_accel_cmdqv_type(obj) != SMMUV3_CMDQV_TEGRA241) {\n+ continue;\n+ }\n+ id = object_property_get_uint(obj, \"identifier\", &error_abort);\n+ pbus = PLATFORM_BUS_DEVICE(vms->platform_bus_dev);\n+ sbdev = SYS_BUS_DEVICE(obj);\n+ base = platform_bus_get_mmio_addr(pbus, sbdev, 1);\n+ base += vms->memmap[VIRT_PLATFORM_BUS].base;\n+ irq = platform_bus_get_irqn(pbus, sbdev, NUM_SMMU_IRQS);\n+ irq += vms->irqmap[VIRT_PLATFORM_BUS];\n+ irq += ARM_SPI_BASE;\n+\n+ dev = aml_device(\"CV%.02u\", id);\n+ aml_append(dev, aml_name_decl(\"_HID\", aml_string(\"NVDA200C\")));\n+ aml_append(dev, aml_name_decl(\"_UID\", aml_int(id)));\n+ aml_append(dev, aml_name_decl(\"_CCA\", aml_int(1)));\n+\n+ crs = aml_resource_template();\n+ addr = aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,\n+ AML_CACHEABLE, AML_READ_WRITE, 0x0, base,\n+ base + TEGRA241_CMDQV_IO_LEN - 0x1, 0x0,\n+ TEGRA241_CMDQV_IO_LEN);\n+ aml_append(crs, addr);\n+ aml_append(crs, aml_interrupt(AML_CONSUMER, AML_EDGE,\n+ AML_ACTIVE_HIGH, AML_EXCLUSIVE,\n+ (uint32_t *)&irq, 1));\n+ aml_append(dev, aml_name_decl(\"_CRS\", crs));\n+\n+ aml_append(scope, dev);\n+\n+ trace_virt_acpi_dsdt_tegra241_cmdqv(id, base, irq);\n+ }\n+}\n+\n /* DSDT */\n static void\n build_dsdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)\n@@ -1178,6 +1226,10 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)\n acpi_dsdt_add_tpm(scope, vms);\n #endif\n \n+ if (!vms->legacy_smmuv3_present) {\n+ acpi_dsdt_add_tegra241_cmdqv(scope, vms);\n+ }\n+\n aml_append(dsdt, scope);\n \n pci0_scope = aml_scope(\"\\\\_SB.PCI0\");\ndiff --git a/hw/arm/trace-events b/hw/arm/trace-events\nindex 6f602b9eda..e5e4e93324 100644\n--- a/hw/arm/trace-events\n+++ b/hw/arm/trace-events\n@@ -9,6 +9,7 @@ omap1_lpg_led(const char *onoff) \"omap1 LPG: LED is %s\"\n \n # virt-acpi-build.c\n virt_acpi_setup(void) \"No fw cfg or ACPI disabled. Bailing out.\"\n+virt_acpi_dsdt_tegra241_cmdqv(int smmu_id, uint64_t base, uint32_t irq) \"DSDT: add cmdqv node for (id=%d), base=0x%\" PRIx64 \", irq=%d\"\n \n # smmu-common.c\n smmu_add_mr(const char *name) \"%s\"\n", "prefixes": [ "v4", "29/31" ] }