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GET /api/1.2/patches/2223458/?format=api
{ "id": 2223458, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2223458/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260415105552.622421-23-skolothumtho@nvidia.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.2/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260415105552.622421-23-skolothumtho@nvidia.com>", "list_archive_url": null, "date": "2026-04-15T10:55:43", "name": "[v4,22/31] hw/arm/tegra241-cmdqv: Map VINTF page0 into guest MMIO space", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "dd103541ceebf5f10d39b1fd4afcac42b9b5728e", "submitter": { "id": 91580, "url": "http://patchwork.ozlabs.org/api/1.2/people/91580/?format=api", "name": "Shameer Kolothum Thodi", "email": "skolothumtho@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260415105552.622421-23-skolothumtho@nvidia.com/mbox/", "series": [ { "id": 499965, "url": "http://patchwork.ozlabs.org/api/1.2/series/499965/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=499965", "date": "2026-04-15T10:55:21", "name": "hw/arm/virt: Introduce Tegra241 CMDQV support for accelerated SMMUv3", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/499965/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2223458/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2223458/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=JHWKaeTq;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail.nvidia.com; pr=C", "permerror client-ip=2a01:111:f403:c10d::1;\n envelope-from=skolothumtho@nvidia.com;\n helo=SN4PR2101CU001.outbound.protection.outlook.com" ], "From": "Shameer Kolothum <skolothumtho@nvidia.com>", "To": "<qemu-arm@nongnu.org>, <qemu-devel@nongnu.org>", "CC": "<eric.auger@redhat.com>, <peter.maydell@linaro.org>, <clg@redhat.com>,\n <alex@shazbot.org>, <nicolinc@nvidia.com>, <nathanc@nvidia.com>,\n <mochs@nvidia.com>, <jan@nvidia.com>, <jgg@nvidia.com>,\n <jonathan.cameron@huawei.com>, <zhenzhong.duan@intel.com>,\n <kjaju@nvidia.com>, <phrdina@redhat.com>, <skolothumtho@nvidia.com>", "Subject": "[PATCH v4 22/31] hw/arm/tegra241-cmdqv: Map VINTF page0 into guest\n MMIO space", "Date": "Wed, 15 Apr 2026 11:55:43 +0100", "Message-ID": "<20260415105552.622421-23-skolothumtho@nvidia.com>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260415105552.622421-1-skolothumtho@nvidia.com>", "References": "<20260415105552.622421-1-skolothumtho@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.230.37]", "X-ClientProxiedBy": "rnnvmail203.nvidia.com (10.129.68.9) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "CY4PEPF0000EE3D:EE_|SA1PR12MB7341:EE_", "X-MS-Office365-Filtering-Correlation-Id": "9218c1ad-ae1c-4d79-f97a-08de9adde3b7", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;\n ARA:13230040|1800799024|376014|36860700016|82310400026|56012099003|18002099003|22082099003;", "X-Microsoft-Antispam-Message-Info": "\n bMr+PLK1VjbLqq+wwtw3MyEWrZbX3AwORsqfJV1+3oaP6hHuCnTIgR6Qtw+yGII0WEWwGOmClXwzxumHehE2cl/y9ishcjLjohXlCZ5YzHdg5Ie9KeQQ9+lcA7baDQ5fKyeTeL9AG+NLpxklhgZ5FNDEtZYF/kJgVwBN9etr/Z2K9jD6IuNwXJQ3gQZCQA5TdO5P+7uq0dCGlbR5p6fyBqP3syT/FbSuc85UldaAZM6smK/5hq40A0Pf4q4Nt5FixYVH+YUym1TlZhj0yz9Y2DIiX2Ie9SyL1SmNnqllJ0qLvApy7C7k6qT+geQVfiSD/pqJGwqSl0o4YB9MYLlCptpEfE4EkjvzNzwDegMXGdjyVlqCXpeoWlXR4hOJR5RAW53wMDcpLfJOaJueHhUxaye+wsSDPUQNRPMYdvSPiq/oy3iq124Sy/cz6wqlXzNIa1BQPjatS9/KWj8Krg4gsEXPJc7N+Co3SI5pRZh9x+xy+x7svg40JS5UWmGPe/E5xCs3RL+lCSnYk3EiKZLM2x7MWzhzrm7sEsyeIIYdBjqnSnoKrv2mIcX5UKDeiM3e1w9YN3lmC852pjicV4OEx8u5L5VU6Mf9lFdpYz9AkUpwcMy992FegzT2PwkxOdqi25nxvJTr11O5Icx7PQ2QBk61RNsy11JKGvHi3LH3oRp4wSLJxsa5ayLcU8cfUqrMWZ1lCXXt06BC/tKY2+Y6jQdhgH81qU42FIHQyLJBFRSVMoe++yYRKcYW34FjP9mgprei0HN6n5YR1o0rQvrWZg==", "X-Forefront-Antispam-Report": "CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE;\n SFS:(13230040)(1800799024)(376014)(36860700016)(82310400026)(56012099003)(18002099003)(22082099003);\n DIR:OUT; SFP:1101;", "X-MS-Exchange-AntiSpam-MessageData-ChunkCount": "1", "X-MS-Exchange-AntiSpam-MessageData-0": "\n jDWVI0OSMeWOZxbxsw5IShnXFIWHK3xM+uGAYRws8A4UkLHBDj7xHE/JouxyYTuIkVGPy4C7dbfolWBLo1fAc3ww239h3Y0YGfelfFHpdSDiilbnQ+/W5eK/mqA4yyZCWGNEGsO4DtS/BrmW+prEtHHE9zM9O7GsXHqS+dohAbKsI7rplgMFyB4MXYJ14fT+ivXiVpii0yOY5ctBxaO8tF00bQudbSalprVIjiBfhjvjBMt6wWUEEp2Ql60XKGe0DLQ0CTOeD4iJkZgVkkkEI+GhgfViQUghPqhz9/JwuPBbmRPDvQltk1OTXvF5UvRSGqEpwcG/nkTJ6TY8wDHU2toMSpSe6lbIoVuqYzBzwp1C/6fh08jCrs4Ve3jdrWJlVrBsILvmfZQQNqA+6yd2Lxf2SvZwzaxxwGC94Dqu4nti9Avtx9ZE87rEaSP+x/dw", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "15 Apr 2026 10:58:13.0826 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 9218c1ad-ae1c-4d79-f97a-08de9adde3b7", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CY4PEPF0000EE3D.namprd03.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "SA1PR12MB7341", "X-Spam_score_int": "-15", "X-Spam_score": "-1.6", "X-Spam_bar": "-", "X-Spam_report": "(-1.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.54,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n FORGED_SPF_HELO=1, SPF_HELO_PASS=-0.001,\n SPF_NONE=0.001 autolearn=no autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "From: Nicolin Chen <nicolinc@nvidia.com>\n\nOnce a VCMDQ is allocated, map the mmap'd vintf_page0 region directly\ninto the guest-visible MMIO space at offset 0x30000 as a RAM-backed\nMemoryRegion. This eliminates QEMU trapping for hot-path CONS/PROD\nindex updates.\n\nAfter this patch, the two VCMDQ apertures use different access paths:\nthe direct aperture (0x10000) remains QEMU-trapped and writes via\nvintf_ptr, while the VI aperture (0x30000) is a direct guest RAM\nmapping. Both paths write to the same underlying vintf_page0 memory,\nso no synchronisation between the apertures is needed.\n\nThe mapping is installed lazily on first successful VCMDQ hardware\nqueue allocation and removed when CMDQV or VINTF is disabled.\n\nSigned-off-by: Nicolin Chen <nicolinc@nvidia.com>\nCo-developed-by: Shameer Kolothum <skolothumtho@nvidia.com>\nSigned-off-by: Shameer Kolothum <skolothumtho@nvidia.com>\n---\n hw/arm/tegra241-cmdqv.h | 1 +\n hw/arm/tegra241-cmdqv.c | 37 +++++++++++++++++++++++++++++++++++++\n 2 files changed, 38 insertions(+)", "diff": "diff --git a/hw/arm/tegra241-cmdqv.h b/hw/arm/tegra241-cmdqv.h\nindex 039d86374f..2befa6205e 100644\n--- a/hw/arm/tegra241-cmdqv.h\n+++ b/hw/arm/tegra241-cmdqv.h\n@@ -46,6 +46,7 @@ typedef struct Tegra241CMDQV {\n IOMMUFDVeventq *veventq;\n IOMMUFDHWqueue *vcmdq[TEGRA241_CMDQV_MAX_CMDQ];\n void *vintf_page0;\n+ MemoryRegion *mr_vintf_page0;\n \n /* Register Cache */\n uint32_t config;\ndiff --git a/hw/arm/tegra241-cmdqv.c b/hw/arm/tegra241-cmdqv.c\nindex eb619e1134..bf989dd51f 100644\n--- a/hw/arm/tegra241-cmdqv.c\n+++ b/hw/arm/tegra241-cmdqv.c\n@@ -15,6 +15,40 @@\n #include \"tegra241-cmdqv.h\"\n #include \"trace.h\"\n \n+static void tegra241_cmdqv_guest_unmap_vintf_page0(Tegra241CMDQV *cmdqv)\n+{\n+ if (!cmdqv->mr_vintf_page0) {\n+ return;\n+ }\n+\n+ memory_region_del_subregion(&cmdqv->mmio_cmdqv, cmdqv->mr_vintf_page0);\n+ object_unparent(OBJECT(cmdqv->mr_vintf_page0));\n+ g_free(cmdqv->mr_vintf_page0);\n+ cmdqv->mr_vintf_page0 = NULL;\n+}\n+\n+static void tegra241_cmdqv_guest_map_vintf_page0(Tegra241CMDQV *cmdqv)\n+{\n+ char *name;\n+\n+ if (cmdqv->mr_vintf_page0) {\n+ return;\n+ }\n+\n+ name = g_strdup_printf(\"%s vintf-page0\",\n+ memory_region_name(&cmdqv->mmio_cmdqv));\n+ cmdqv->mr_vintf_page0 = g_malloc0(sizeof(*cmdqv->mr_vintf_page0));\n+ memory_region_init_ram_device_ptr(cmdqv->mr_vintf_page0,\n+ memory_region_owner(&cmdqv->mmio_cmdqv),\n+ name, VINTF_PAGE_SIZE,\n+ cmdqv->vintf_page0);\n+ cmdqv->mr_vintf_page0->ram_device_skip_iommu_map = true;\n+ memory_region_add_subregion_overlap(&cmdqv->mmio_cmdqv,\n+ CMDQV_VINTF_PAGE0_BASE,\n+ cmdqv->mr_vintf_page0, 1);\n+ g_free(name);\n+}\n+\n static void tegra241_cmdqv_free_vcmdq(Tegra241CMDQV *cmdqv, int index)\n {\n IOMMUFDViommu *viommu = cmdqv->s_accel->viommu;\n@@ -72,6 +106,7 @@ static bool tegra241_cmdqv_setup_vcmdq(Tegra241CMDQV *cmdqv, int index,\n hw_queue->viommu = viommu;\n cmdqv->vcmdq[index] = hw_queue;\n \n+ tegra241_cmdqv_guest_map_vintf_page0(cmdqv);\n return true;\n }\n \n@@ -312,6 +347,7 @@ static void tegra241_cmdqv_config_vintf_write(Tegra241CMDQV *cmdqv,\n cmdqv->vintf_status |= R_VINTF0_STATUS_ENABLE_OK_MASK;\n }\n } else {\n+ tegra241_cmdqv_guest_unmap_vintf_page0(cmdqv);\n tegra241_cmdqv_free_all_vcmdq(cmdqv);\n tegra241_cmdqv_munmap_vintf_page0(cmdqv, errp);\n cmdqv->vintf_status &= ~R_VINTF0_STATUS_ENABLE_OK_MASK;\n@@ -438,6 +474,7 @@ static void tegra241_cmdqv_write_mmio(void *opaque, hwaddr offset,\n if (value & R_CONFIG_CMDQV_EN_MASK) {\n cmdqv->status |= R_STATUS_CMDQV_ENABLED_MASK;\n } else {\n+ tegra241_cmdqv_guest_unmap_vintf_page0(cmdqv);\n tegra241_cmdqv_free_all_vcmdq(cmdqv);\n cmdqv->status &= ~R_STATUS_CMDQV_ENABLED_MASK;\n }\n", "prefixes": [ "v4", "22/31" ] }